JP4011693B2 - Manufacturing method of semiconductor package - Google Patents

Manufacturing method of semiconductor package Download PDF

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Publication number
JP4011693B2
JP4011693B2 JP29833697A JP29833697A JP4011693B2 JP 4011693 B2 JP4011693 B2 JP 4011693B2 JP 29833697 A JP29833697 A JP 29833697A JP 29833697 A JP29833697 A JP 29833697A JP 4011693 B2 JP4011693 B2 JP 4011693B2
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Japan
Prior art keywords
manufacturing
semiconductor package
circuit board
chip
reference member
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JP29833697A
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JPH11135523A (en
Inventor
芳弘 石田
博之 江頭
齋藤　　亨
順生 井口
正之 石木田
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Citizen Holdings Co Ltd
Citizen Watch Co Ltd
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Citizen Holdings Co Ltd
Citizen Watch Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は半導体パッケージの製造方法に係わり、更に詳しくは外部接続用の突起電極を有する半導体パッケージの製造方法に関するものである。
【０００２】
【従来の技術】
近年、半導体パッケージの小型化、高密度化に伴いベア・チップを直接フェイスダウンで、基板上に実装するフリップチップボンディングが開発されている。カメラ一体型ＶＴＲや携帯電話機等の登場により、ベア・チップと略同じ寸法の小型パッケージ、所謂ＣＳＰ（チップサイズ／スケール・パッケージ）を載せた携帯機器が相次いで登場してきている。最近ＣＳＰの開発は急速に進み、その市場要求が本格化している。
【０００３】
多数個取りし、高密度実装化した従来技術が特開平８−１５３８１９号公報に開示されており、図４に示す。以下図面に基づいてその概要を説明する。
【０００４】
図４において、短冊状の回路基板１にスルーホール２を形成後、銅メッキ層を施す工程と、全ての回路パターンと接続する共通電極１４を含む複数個、例えば２個のＢＧＡを構成する回路パターンを形成する回路パターン形成工程と、前記回路基板１の上下両面に感光性樹脂皮膜を施した後、エッチングにより、共通電極１４及びＩＣチップ、ボンディングワイヤ、半田バンプの各接続部を除くようにドライフイルムを形成するドライフイルムラミネート工程と、前記共通電極１４を利用して前記回路基板１の上下両面の露出している電極の銅メッキ層の表面に、Ｎｉ−Ａｕメッキ層を形成する。
【０００５】
次に、共通電極１４と回路パターンとを分離するパターン分離工程は、製品分離ライン１５の四辺に沿って、その四隅に回路基板１と連結する連結部１５ａを残すように、ルータ加工により長穴１６を穴明けする。その後、ワイヤーボンディング及びトランスファーモールドにより樹脂封止し、回路基板１の下面に半田バンプを形成する。
【０００６】
製品分離工程は、前記四隅に残した連結部は狭隘なため、プレス抜き等の切り離し手段で余分な負荷をかけることなく極めて容易に分離することにより、単個のＢＧＡを製造することができる。
【０００７】
しかしながら、前述した短冊状の複数個取りする半導体パッケージの製造方法は、単個の半導体パッケージの製造方法に比較して生産性は若干向上するが、小型パッケージであるＣＳＰにおいては、回路基板製造時の基板取り個数が少なく、生産コストが高くなる。また、前記ＣＳＰのように、前記回路基板の外縁から最外周に位置するボール電極の中心までの距離が差が無くなると、製品分離工程でプレス抜き等の切り離し手段で分離する時の金型押さえ代が無くなる等の問題があった。
【０００８】
そこで、小型携帯機器等に搭載するＣＳＰの従来の半導体パッケージの製造方法について以下その概要を図５、図６に基づいて説明する。
【０００９】
先ず図５（ａ）に示す多数個取りする回路基板形成工程は、両面銅張りされた集合回路基板１Ａにスルーホール（図示しない）を形成した後、無電解銅メッキ及び電解銅メッキにより銅メッキ層を形成し、更にメッキレジストをラミネートし、露光現像してパターンマスクを形成した後、エッチング液を用いてパターンエッチングを行うことにより、前記集合回路基板１Ａの上面側にはＣＳＰを複数個分配列したＩＣ接続用電極３、下面側にもＣＳＰ複数個分のパッド電極である外部接続電極４を形成する。次にソルダーレジスト処理を行い、所定の部分にレジスト膜を形成することにより、前記集合回路基板１Ａの下面側には外部接続電極４を露呈するように、マトリックス状に多数の同一形状の半田付け可能な表面であるレジスト膜の開口部を形成し、多数個取りする集合回路基板１Ａが完成される。２はＸ、Ｙ方向に直交するカットラインである。
【００１０】
図５（ｂ）に示すＩＣチップ実装工程は、先ず、ＩＣウエハーをバンプ工程に流して前記ＩＣウエハーのパッド電極面に半田バンプ５を形成する。前記半田バンプ５の形成方法には、一般に、スタッドバンプ方式、ボールバンプ方式、及びメッキバンプ方式等があるが、その中で、パッド電極位置にレジストにて窓を形成し半田浴槽中に浸漬してメッキにて半田バンプを形成するメッキバンプ方式は、パッド電極間の狭い配列でバンプを形成することが可能で、ＩＣチップの小型化には有効な半田バンプの形成手段である。
【００１１】
前記半田バンプ５を形成後、前記ＩＣウエハーを粘着テープ等で貼着した状態で、所定のチップサイズにダイシングソー等の装置でウエハーの厚みをフルカット方式でＸ、Ｙ方向に切断した後、ＩＣチップ６を単体に分割する。
【００１２】
前記半田バンプ付きＩＣチップ６、又は前述した集合回路基板１Ａの前記配線パターンの所定位置にフラックスを塗布して、単体に分割した前記ＩＣチップ６を１個づつ複数個分配列した集合回路基板１Ａの個々の回路基板１上の所定位置に搭載した後、半田リフロー工程を経て、フリップチップ実装を行う。
【００１３】
図５（ｃ）に示す封止工程は、熱硬化性の封止樹脂７で前記隣接する複数個のＩＣチップ５に跨がった状態で、サイドポッティングにより一体的に樹脂封止することにより、ＩＣチップ６はフェイスダウンで集合回路基板１Ａの個々の回路基板１上に固定される。
【００１４】
図６（ａ）に示す基準部材張り付け工程は、ＩＣチップ６を実装した集合回路基板１Ａの平坦な底面を、基準部材８上に接着剤又は粘着テープ等の固定手段で張り付ける。張り付け面が互いに平坦なため、確実に固定される。
【００１５】
図６（ｂ）は、ダイシング工程で、前述のＸ、Ｙ方向のカットライン２に沿って、ダイシングソー等の切削手段で単個に切削、分割した後、溶解液等により基準部材８より剥離する。
【００１６】
図６（ｃ）において、ボール電極を形成するボール形成工程は切削、分離された個々の回路基板１の下面側に形成された外部接続電極４の位置に、半田ボールを配置してリフローすることによりボール電極９を形成する。以上の工程により単個のフリップチップＢＧＡ２０が完成される。
【００１７】
【発明が解決しようとする課題】
しかしながら、前述した半導体パッケージの製造方法には次のような問題点がある。即ち、半田ボール付けは、単個に切削、分割された回路基板毎に半田ボールを配置して行うもので、小型パッケージであるＣＳＰにおいては、回路基板１の外縁から最外周に位置するボール電極の中心までの距離が無くなると、半田ボール付け時の治具スペースが取れなくなる。また、個々に半田ボール付けを行うので生産性が低く、コストアップ等の問題があった。
【００１８】
本発明は、上記従来の課題に鑑みなされたものであり、その目的は、小型携帯機器等に搭載する信頼性及び生産性に優れた、安価な半導体パッケージの製造方法を提供するものである。
【００１９】
【課題を解決するための手段】
上記目的を達成するために、本発明における半導体パッケージの製造方法は、回路基板の一方の面に外部接続電極を形成し、他方の面にＩＣチップを実装した半導体パッケージの製造方法において、前記ＩＣチップ実装用のボンディングパターンと外部接続電極を形成するための電極パターンとを集合回路基板面に複数個分配列して形成する回路基板形成工程と、前記ボンディングパターンと前記ＩＣチップを電気的に接続するＩＣチップ実装工程と、該ＩＣチップを樹脂封止する封止工程とによりパッケージ集合体を形成し、該パッケージ集合体の外部接続電極面を第１の基準部材に固定する第１保持工程と、保持されたパッケージ集合体の回路基板を切削して単個の半導体パッケージを形成する切削工程と、前記パッケージ集合体のＩＣ実装面を第２の基準部材に固定する第２保持工程と、前記第１の基準部材を前記パッケージ集合体より剥離する剥離工程と、前記外部接続電極に突起電極を形成する電極形成工程とからなることを特徴とするものである。
【００２０】
また、前記第１保持工程は、接着剤で固着することを特徴とするものである。
【００２１】
また、前記接着剤は、紫外線反応型樹脂であることを特徴とするものである。
【００２２】
また、前記第２保持工程は、接着剤で固着することを特徴とするものである。
【００２３】
また、前記接着剤は、熱反応型樹脂であることを特徴とするものである。
【００２４】
また、前記突起電極は、半田バンプであることを特徴とするものである。
【００２５】
また、前記切削工程は、ダイシングソーによる切削で行うことを特徴とするものである。
【００２６】
【発明の実施の形態】
以下図面に基づいて本発明における半導体パッケージの製造方法について説明する。図１、図２及び図３は本発明の実施の形態で、突起電極付きの半導体パッケージの製造工程を示す説明図である。従来技術と同一部材は同一符号で示す。
【００２７】
先ず、図１（ａ）の回路基板形成工程、図１（ｂ）のＩＣ実装工程、図１（ｃ）の樹脂封止工程は、前述の従来技術と同様であるので、説明は省略する。
【００２８】
図２（ａ）の第１基準部材張り付け工程、図２（ｂ）のダイシング工程は、前述の従来技術と同様であるので、説明は省略する。
【００２９】
図３（ａ）は第２基準部材張り付け工程を示しており、前記集合回路基板１Ａが第１基準部材上で、単個に切削、分割された状態で、ＩＣチップ実装面を、第２基準部材１２上に接着剤で張り付ける。つまりこの状態では、ダイシング工程によって集合回路基板１Ａが単個に分割されているものの、第１基準部材１１を介してまだ連結されているので、全体を一括して第２基準部材１２上へ接着できる。
【００３０】
図３（ｂ）は第１基準部材剥離工程を示しており、図２（ａ）の第１基準部材張り付け工程で使った接着剤、例えば、リンテック（株）製の紫外線剥離テープ「Ｄ６３８」の接着力を紫外線で低下させ、第１基準部材と前記集合回路基板１Ａの製品以外の部分を製品部分から剥離する。
【００３１】
図３（ｃ）はボール電極を形成するボール付け工程を示しており、前記集合回路基板１Ａの下面側に形成された外部接続電極４と同じ位置にある回路基板第２基準部材に張り付けられた個々の回路基板１の下面側に形成された外部接続電極４の位置に、半田ボールを配置してリフローすることにより突起電極であるボール電極９が形成される。この時、複数のパッケージに対し、同時に半田ボールを供給できるので、生産性を高めることができる。
【００３２】
その後、半導体パッケージを第２基準部材１２より剥離する。以上の工程により単個のフリップチップＢＧＡ１０が完成される。
【００３３】
【発明の効果】
以上説明したように、本発明の半導体パッケージの製造方法によれば、前記集合回路基板の上面側に複数個分配列して回路基板にＩＣチップを実装し、封止樹脂でサイドモールドして、下面側の外部接続電極を第１基準部材に固定し、切削して単個にし、ＩＣ実装部を第２基準部材に固定し、第１基準部材を剥離し、下面側の外部接続電極に突起電極を形成後、第２基準部材を剥離して単個の半導体パッケージを製造することにより、小型携帯機器等に搭載する信頼性及び生産性の優れた半導体パッケージの製造方法を提供することが可能である。
【図面の簡単な説明】
【図１】本発明の実施の形態に係わる半導体パッケージの製造工程で、回路基板形成工程、ＩＣ実装工程、樹脂封止工程を示す説明図である。
【図２】図１の製造工程後の第１基準部材張り付け工程、ダイシング工程を示す説明図である。
【図３】図２の製造工程後の第２基準部材張り付け工程、第１基準部材剥離工程、ボール付け工程を示す説明図である。
【図４】従来の短冊状のＢＧＡの平面図である。
【図５】従来のＢＧＡの製造工程で、回路基板形成工程、ＩＣ実装工程、樹脂封止工程を示す説明図である。
【図６】従来のＢＧＡの製造工程で、図５の製造工程後の基準部材張り付け工程、ダイシング工程、ボール付け工程を示す説明図である。
【符号の説明】
１ 回路基板
１Ａ 集合回路基板
２ カットライン
３ ＩＣ接続用電極
４ 外部接続電極
５ 半田ボール
６ ＩＣチップ
７ 封止樹脂
８ 基準部材
９ ボール電極（突起電極）
１０ フリップチップＢＧＡ
１１ 第１基準部材
１２ 第２基準部材[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a semiconductor package having protruding electrodes for external connection.
[0002]
[Prior art]
2. Description of the Related Art In recent years, flip chip bonding has been developed in which a bare chip is directly mounted face-down on a substrate as semiconductor packages become smaller and higher in density. With the advent of camera-integrated VTRs, mobile phones, and the like, mobile devices on which small packages of approximately the same dimensions as bare chips, so-called CSP (chip size / scale packages), have appeared one after another. Recently, the development of CSP is progressing rapidly, and the market demand is in full swing.
[0003]
Japanese Patent Laid-Open No. 8-1553819 discloses a conventional technique in which a large number of chips are taken and mounted in high density, and is shown in FIG. The outline will be described below with reference to the drawings.
[0004]
In FIG. 4, after forming the through hole 2 in the strip-shaped circuit board 1, a step of applying a copper plating layer, and a circuit constituting a plurality of, for example, two BGAs including a common electrode 14 connected to all circuit patterns. A circuit pattern forming process for forming a pattern, and after applying a photosensitive resin film on both the upper and lower surfaces of the circuit board 1, the common electrode 14 and the connecting portions of the IC chip, bonding wires, and solder bumps are removed by etching. A Ni-Au plating layer is formed on the surface of the exposed copper plating layer of the upper and lower surfaces of the circuit board 1 by using the common electrode 14 and a dry film laminating process for forming a dry film.
[0005]
Next, in the pattern separation process for separating the common electrode 14 and the circuit pattern, a long hole is formed by router processing so that the connection portions 15a connected to the circuit board 1 are left at the four corners along the four sides of the product separation line 15. 16 is drilled. Thereafter, resin sealing is performed by wire bonding and transfer molding, and solder bumps are formed on the lower surface of the circuit board 1.
[0006]
In the product separation process, since the connecting portions left at the four corners are narrow, a single BGA can be manufactured by separating very easily without applying an extra load by a separating means such as press punching.
[0007]
However, although the above-described method for manufacturing a plurality of strip-shaped semiconductor packages is slightly improved in productivity as compared to a method for manufacturing a single semiconductor package, in a CSP which is a small package, a circuit board is manufactured. This reduces the number of substrates that can be produced and increases the production cost. Further, as in the case of the CSP, when there is no difference in the distance from the outer edge of the circuit board to the center of the ball electrode located on the outermost periphery, the mold holder when separating by a separating means such as press punching in the product separation process. There was a problem such as a lack of money.
[0008]
An outline of a method for manufacturing a conventional semiconductor package of a CSP mounted on a small portable device will be described with reference to FIGS.
[0009]
First, in the circuit board forming step for taking a large number of pieces as shown in FIG. 5 (a), a through hole (not shown) is formed in the collective circuit board 1A covered with copper on both sides, and then copper plating is performed by electroless copper plating and electrolytic copper plating. After forming a layer, laminating a plating resist, exposing and developing to form a pattern mask, pattern etching is performed using an etchant, whereby a plurality of CSPs are distributed on the upper surface side of the collective circuit board 1A. The external connection electrodes 4 which are pad electrodes corresponding to a plurality of CSPs are also formed on the arranged IC connection electrodes 3 and the lower surface side. Next, solder resist processing is performed, and a resist film is formed on a predetermined portion, so that the external connection electrodes 4 are exposed on the lower surface side of the collective circuit board 1A. An opening portion of a resist film, which is a possible surface, is formed, and a collective circuit board 1A in which a large number are taken is completed. Reference numeral 2 denotes a cut line orthogonal to the X and Y directions.
[0010]
In the IC chip mounting process shown in FIG. 5B, first, an IC wafer is passed through a bump process to form solder bumps 5 on the pad electrode surface of the IC wafer. The solder bumps 5 are generally formed by a stud bump method, a ball bump method, a plated bump method, etc., in which a window is formed with a resist at the pad electrode position and immersed in a solder bath. The plating bump method of forming solder bumps by plating can form bumps with a narrow arrangement between pad electrodes, and is an effective means for forming solder bumps for miniaturization of IC chips.
[0011]
After forming the solder bumps 5, with the IC wafer attached with an adhesive tape or the like, the wafer thickness is cut in the X and Y directions by a full-cut method with a device such as a dicing saw to a predetermined chip size, The IC chip 6 is divided into single pieces.
[0012]
The integrated circuit board 1A in which the IC chips 6 with solder bumps or the above-described integrated circuit board 1A are coated with a flux at a predetermined position of the wiring pattern, and the IC chips 6 divided into a single piece are arranged one by one. After mounting at a predetermined position on each of the circuit boards 1, flip chip mounting is performed through a solder reflow process.
[0013]
In the sealing step shown in FIG. 5C, the resin is integrally sealed by side potting while straddling the plurality of adjacent IC chips 5 with the thermosetting sealing resin 7. The IC chip 6 is fixed face-down on each circuit board 1 of the collective circuit board 1A.
[0014]
In the reference member attaching step shown in FIG. 6A, the flat bottom surface of the collective circuit board 1A on which the IC chip 6 is mounted is attached onto the reference member 8 by a fixing means such as an adhesive or an adhesive tape. Since the pasting surfaces are flat with each other, they are securely fixed.
[0015]
FIG. 6B shows a dicing process that is cut and divided into pieces by a cutting means such as a dicing saw along the X and Y cut lines 2 described above, and then peeled off from the reference member 8 by a solution or the like. To do.
[0016]
In FIG. 6C, in the ball forming process for forming the ball electrode, the solder balls are arranged at the position of the external connection electrode 4 formed on the lower surface side of each of the cut and separated circuit boards 1 and reflowed. Thus, the ball electrode 9 is formed. A single flip chip BGA 20 is completed through the above steps.
[0017]
[Problems to be solved by the invention]
However, the semiconductor package manufacturing method described above has the following problems. That is, soldering is performed by arranging solder balls for each circuit board that is cut and divided into individual pieces. In a CSP that is a small package, ball electrodes located on the outermost periphery from the outer edge of the circuit board 1. If the distance to the center is lost, the jig space for solder ball attachment cannot be taken. In addition, since solder balls are individually attached, productivity is low and there is a problem of cost increase.
[0018]
The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide an inexpensive method for manufacturing a semiconductor package which is excellent in reliability and productivity mounted on a small portable device or the like.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention includes a method of manufacturing a semiconductor package in which an external connection electrode is formed on one surface of a circuit board and an IC chip is mounted on the other surface. A circuit board forming step of forming a plurality of bonding patterns for chip mounting and electrode patterns for forming external connection electrodes on the surface of the collective circuit board; and electrically connecting the bonding pattern and the IC chip A first holding step of forming a package assembly by an IC chip mounting step of sealing and a sealing step of resin-sealing the IC chip, and fixing the external connection electrode surface of the package assembly to the first reference member; A cutting step of cutting a circuit board of the held package assembly to form a single semiconductor package, and an IC of the package assembly From a second holding step for fixing the mounting surface to the second reference member, a peeling step for peeling the first reference member from the package assembly, and an electrode forming step for forming a protruding electrode on the external connection electrode It is characterized by.
[0020]
The first holding step is characterized by being fixed with an adhesive.
[0021]
Further, the adhesive is an ultraviolet reaction type resin.
[0022]
Further, the second holding step is characterized by being fixed with an adhesive.
[0023]
Further, the adhesive is a heat-reactive resin.
[0024]
Further, the protruding electrode is a solder bump.
[0025]
The cutting step is performed by cutting with a dicing saw.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a method for manufacturing a semiconductor package according to the present invention will be described with reference to the drawings. FIG. 1, FIG. 2 and FIG. 3 are explanatory views showing a manufacturing process of a semiconductor package with protruding electrodes according to the embodiment of the present invention. The same members as those in the prior art are denoted by the same reference numerals.
[0027]
First, the circuit board forming process of FIG. 1A, the IC mounting process of FIG. 1B, and the resin sealing process of FIG.
[0028]
Since the first reference member attaching step in FIG. 2A and the dicing step in FIG. 2B are the same as those in the above-described conventional technology, the description thereof is omitted.
[0029]
FIG. 3A shows a second reference member attaching step, in which the collective circuit board 1A is cut and divided into single pieces on the first reference member, and the IC chip mounting surface is changed to the second reference member. Affixed on the member 12 with an adhesive. In other words, in this state, the collective circuit board 1A is divided into a single piece by the dicing process, but is still connected through the first reference member 11, so that the whole is bonded onto the second reference member 12 all at once. it can.
[0030]
FIG. 3 (b) shows the first reference member peeling step. For example, the adhesive used in the first reference member attaching step in FIG. 2 (a), for example, an ultraviolet peeling tape “D638” manufactured by Lintec Corporation. The adhesive force is lowered with ultraviolet rays, and the first reference member and the part other than the product of the collective circuit board 1A are peeled off from the product part.
[0031]
FIG. 3C shows a ball attaching process for forming a ball electrode, which is attached to the circuit board second reference member at the same position as the external connection electrode 4 formed on the lower surface side of the collective circuit board 1A. A ball electrode 9 that is a protruding electrode is formed by placing a solder ball at the position of the external connection electrode 4 formed on the lower surface side of each circuit board 1 and performing reflow. At this time, solder balls can be simultaneously supplied to a plurality of packages, so that productivity can be improved.
[0032]
Thereafter, the semiconductor package is peeled off from the second reference member 12. A single flip chip BGA 10 is completed through the above steps.
[0033]
【The invention's effect】
As described above, according to the semiconductor package manufacturing method of the present invention, a plurality of IC chips are arranged on the upper surface side of the collective circuit board, IC chips are mounted on the circuit board, side-molded with a sealing resin, The external connection electrode on the lower surface side is fixed to the first reference member, cut into a single piece, the IC mounting portion is fixed to the second reference member, the first reference member is peeled off, and the external connection electrode on the lower surface side is projected. After the electrode is formed, the second reference member is peeled off to manufacture a single semiconductor package, thereby providing a method for manufacturing a semiconductor package with excellent reliability and productivity mounted on a small portable device or the like. It is.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a circuit board forming process, an IC mounting process, and a resin sealing process in a manufacturing process of a semiconductor package according to an embodiment of the present invention.
2 is an explanatory view showing a first reference member attaching step and a dicing step after the manufacturing step of FIG. 1; FIG.
3 is an explanatory view showing a second reference member attaching step, a first reference member peeling step, and a ball attaching step after the manufacturing step of FIG. 2; FIG.
FIG. 4 is a plan view of a conventional strip-shaped BGA.
FIG. 5 is an explanatory view showing a circuit board forming process, an IC mounting process, and a resin sealing process in a conventional BGA manufacturing process;
6 is an explanatory diagram showing a reference member pasting step, a dicing step, and a ball attaching step after the manufacturing step of FIG. 5 in the conventional BGA manufacturing step.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Circuit board 1A Collective circuit board 2 Cut line 3 IC connection electrode 4 External connection electrode 5 Solder ball 6 IC chip 7 Sealing resin 8 Reference member 9 Ball electrode (projection electrode)
10 Flip chip BGA
11 First reference member 12 Second reference member

Claims (7)

回路基板の一方の面に外部接続電極を形成し、他方の面にＩＣチップを実装した半導体パッケージの製造方法において、前記ＩＣチップ実装用のボンディングパターンと外部接続電極を形成するための電極パターンとを集合回路基板面に複数個分配列して形成する回路基板形成工程と、前記ボンディングパターンと前記ＩＣチップを電気的に接続するＩＣチップ実装工程と、該ＩＣチップを樹脂封止する封止工程とによりパッケージ集合体を形成し、該パッケージ集合体の外部接続電極を第１の基準部材に固定する第１保持工程と、保持されたパッケージ集合体の回路基板を切削して単個の半導体パッケージを形成する切削工程と、前記パッケージ集合体のＩＣ実装面を第２の基準部材に固定する第２保持工程と、前記第１の基準部材を前記パッケージ集合体より剥離する剥離工程と、前記外部接続電極に突起電極を形成する電極形成工程とからなることを特徴とする半導体パッケージの製造方法。  In a semiconductor package manufacturing method in which an external connection electrode is formed on one surface of a circuit board and an IC chip is mounted on the other surface, the bonding pattern for mounting the IC chip and an electrode pattern for forming the external connection electrode Circuit board forming step in which a plurality of the circuit boards are arranged on the surface of the collective circuit board, an IC chip mounting step for electrically connecting the bonding pattern and the IC chip, and a sealing step for resin-sealing the IC chip Forming a package assembly and fixing the external connection electrode of the package assembly to the first reference member; and cutting the circuit board of the held package assembly to form a single semiconductor package A second holding step of fixing the IC mounting surface of the package assembly to a second reference member, and the first reference member A peeling step of peeling from Kkeji aggregate, a method of manufacturing a semiconductor package, characterized in that comprising the electrode forming step of forming protruding electrodes to the external connection electrode. 前記第１保持工程は、接着剤で固着することを特徴とする請求項１記載の半導体パッケージの製造方法。  The method of manufacturing a semiconductor package according to claim 1, wherein the first holding step is fixed by an adhesive. 前記接着剤は、紫外線反応型樹脂であることを特徴とする請求項２記載の半導体パッケージの製造方法。  3. The method of manufacturing a semiconductor package according to claim 2, wherein the adhesive is an ultraviolet reactive resin. 前記第２保持工程は、接着剤で固着することを特徴とする請求項１記載の半導体パッケージの製造方法。  The method of manufacturing a semiconductor package according to claim 1, wherein the second holding step is fixed by an adhesive. 前記接着剤は、熱反応型樹脂であることを特徴とする請求項４記載の半導体パッケージの製造方法。  5. The method of manufacturing a semiconductor package according to claim 4, wherein the adhesive is a heat-reactive resin. 前記突起電極は、半田バンプであることを特徴とする請求項１から５のいずれか１項に記載の半導体パッケージの製造方法。The protrusion electrodes, a method of manufacturing a semiconductor package according to claim 1, any one of 5, which is a solder bump. 前記切削工程は、ダイシングソーによる切削で行うことを特徴とする請求項１から６のいずれか１項に記載の半導体パッケージの製造方法。The cutting step is a method of manufacturing a semiconductor package according to any one of claims 1 6, characterized in that the cutting by the dicing saw.
JP29833697A 1997-10-30 1997-10-30 Manufacturing method of semiconductor package Expired - Fee Related JP4011693B2 (en)

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