JPH10156821A - Ceramic base having division grooves and resistor using the same - Google Patents
Ceramic base having division grooves and resistor using the sameInfo
- Publication number
- JPH10156821A JPH10156821A JP8320504A JP32050496A JPH10156821A JP H10156821 A JPH10156821 A JP H10156821A JP 8320504 A JP8320504 A JP 8320504A JP 32050496 A JP32050496 A JP 32050496A JP H10156821 A JPH10156821 A JP H10156821A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- holes
- hole
- diameter
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Devices For Post-Treatments, Processing, Supply, Discharge, And Other Processes (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
【０００１】[0001]
【発明が属する技術分野】本発明は、分割溝を有するセ
ラミック基板と、これを用いて製造したネットワーク抵
抗器等の抵抗器用に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic substrate having a dividing groove and to a resistor for a network resistor or the like manufactured using the ceramic substrate.
【０００２】[0002]
【従来の技術】従来、セラミック基板に複数の分割線を
形成し、抵抗体や電極等を印刷した後で分割してチップ
抵抗器を作製することが行われている。近年、プリント
基板等の配線の微細化やプリント基板等の小型化に伴
い、チップ抵抗器の単体の寸法が３．２×１．６ｍｍか
ら２．０×１．２５ｍｍ、１．６×０．８ｍｍ、１．０
×０．５ｍｍと小型化が図られている。2. Description of the Related Art Conventionally, a chip resistor is manufactured by forming a plurality of dividing lines on a ceramic substrate, printing a resistor, an electrode, and the like, and then dividing the printed circuit. In recent years, with the miniaturization of wiring such as a printed circuit board and the miniaturization of a printed circuit board and the like, the size of a single chip resistor has been changed from 3.2 × 1.6 mm to 2.0 × 1.25 mm, 1.6 × 0. 8mm, 1.0
The size is reduced to 0.5 mm.
【０００３】一方、電子部品実装の密度を向上させるた
めに、図３（ａ）に示すように、１個の基体１３上に２
〜８個の抵抗体２２と電極２１を備えた多連チップ抵抗
器や、図３（ｂ）（ｃ）に示すように、各抵抗体２２を
接続したネットワーク抵抗器が使用されている。これら
の抵抗器２０も、図４（ａ）に示す複数の分割溝１１を
備えたセラミック基板１２を用いて、多数個取りの手法
で製造されるものである。On the other hand, in order to increase the density of electronic component mounting, as shown in FIG.
A multiple chip resistor having up to eight resistors 22 and electrodes 21 and a network resistor connecting each resistor 22 as shown in FIGS. 3B and 3C are used. These resistors 20 are also manufactured by a multi-cavity method using a ceramic substrate 12 having a plurality of division grooves 11 shown in FIG.
【０００４】具体的な抵抗器２０の製造方法は、まず、
ドクターブレード法等によりセラミックスのスラリーを
シート状に成形する。得られたグリーンシートを金型を
用いて打ち抜くと同時に複数の分割線とスルーホールを
形成する。これを所定条件で焼成することによって、図
４（ａ）に示すように、縦横の分割線１１とこの分割線
１１上に備えられたスルーホール１２を有するセラミッ
ク基板１０を得る。このセラミック基板１０上に図３に
示すような電極２１、抵抗体２２、保護膜等を印刷、焼
き付けし、所定の抵抗値となるようにトリミングした
後、図３（ｂ）に示す単体の基板１３となるように、分
割線１１に沿って分割し、抵抗器２０を得ることができ
る（特開平５−２４３０２０号、実公平６−３２６５０
号公報等参照）。A specific method of manufacturing the resistor 20 is as follows.
The ceramic slurry is formed into a sheet by a doctor blade method or the like. The obtained green sheet is punched out using a mold, and a plurality of division lines and through holes are formed at the same time. By firing this under predetermined conditions, a ceramic substrate 10 having vertical and horizontal dividing lines 11 and through holes 12 provided on the dividing lines 11 is obtained as shown in FIG. An electrode 21, a resistor 22, a protective film, and the like as shown in FIG. 3 are printed and baked on the ceramic substrate 10 and trimmed to have a predetermined resistance value, and then a single substrate as shown in FIG. The resistor 20 can be obtained by dividing the resistor 20 along the dividing line 11 so as to be 13 (Japanese Patent Laid-Open No. 5-243020, Japanese Utility Model Publication No. 6-32650)
Reference).
【０００５】[0005]
【発明が解決しようとする課題】ところで、上記製造工
程のうち、セラミック基板１０上に電極２１を印刷する
工程では、図５に示すように、スルーホール１２の周囲
にペーストを印刷し、下から吸引することでスルーホー
ル１２の内面にもペーストを塗布して電極２１を形成す
る。この時ペーストが分割溝１１に流れ込み、隣合う電
極２１同士が短絡してしまうという問題があった。In the process of printing the electrodes 21 on the ceramic substrate 10 in the above manufacturing process, a paste is printed around the through holes 12 as shown in FIG. The electrode 21 is formed by applying the paste to the inner surface of the through hole 12 by suction. At this time, there is a problem that the paste flows into the dividing grooves 11 and adjacent electrodes 21 are short-circuited.
【０００６】特に、近年、抵抗器２０の小型化が求めら
れているが、抵抗器２０を小型化しようとすると、スル
ーホール１２の間隔が狭くなって、上記の問題が顕著に
なっていた。この問題点を解決するためには、スルーホ
ール１２の径φを小さくすれば良いが、従来の抵抗器２
０では、スルーホール１２の径φは０．３ｍｍ、ピッチ
ｐは０．８ｍｍ程度が限界であった。そのため、抵抗器
２０の寸法は３．２×１．５ｍｍが限界であり、これ以
上小型化すると、上記ペーストの短絡のために極めて歩
留りが悪いものとなっていた。In particular, in recent years, downsizing of the resistor 20 has been demanded. However, if the resistor 20 is to be downsized, the distance between the through holes 12 becomes narrow, and the above-mentioned problem has become remarkable. In order to solve this problem, the diameter φ of the through-hole 12 may be reduced.
At 0, the diameter φ of the through hole 12 was limited to 0.3 mm, and the pitch p was limited to about 0.8 mm. Therefore, the size of the resistor 20 is limited to 3.2 × 1.5 mm. If the size is further reduced, the yield is extremely poor due to the short circuit of the paste.
【０００７】また、抵抗器２０の小型化に伴い、基体１
３の厚みｔは０．３ｍｍ程度と薄くなっているため、得
られた抵抗器２０をプリント基板等に搭載する際に、ス
ルーホール１２近傍から割れてしまうという問題もあっ
た。Further, with the downsizing of the resistor 20, the base 1
3 has a thickness of about 0.3 mm, so that when the obtained resistor 20 is mounted on a printed circuit board or the like, there is also a problem that the resistor 20 is broken from the vicinity of the through hole 12.
【０００８】[0008]
【課題を解決するための手段】そこで本発明は、表面に
縦横の分割溝と、この分割溝上の複数のスルーホールを
備えてなるセラミック基板であって、基板厚みｔ、スル
ーホール径φ、分割後の短辺の長さｃ、スルーホールの
ピッチｐが、 ｃ≦１．０ｍｍ ｐ≦０．５ｍｍ であり、かつ φ／ｃ≦０．１９ 及び／又は ｔ／ｃ≧０．３２ を満たすことを特徴とする。SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a ceramic substrate having vertical and horizontal dividing grooves on the surface and a plurality of through holes on the dividing groove, wherein the substrate thickness t, the through hole diameter φ, the dividing The length c of the rear short side and the pitch p of the through holes are c ≦ 1.0 mm, p ≦ 0.5 mm, and φ / c ≦ 0.19 and / or t / c ≧ 0.32 are satisfied. It is characterized by.
【０００９】また本発明は、セラミックス製基体の外周
に複数の半円状の凹部を有し、該凹部の周囲に電極を備
え、各電極間に抵抗体を備えてなる抵抗器であって、基
体厚みｔ、凹部の径φ、基体の短辺の長さｃ、凹部のピ
ッチｐが、 ｃ≦１．０ｍｍ ｐ≦０．５ｍｍ であり、かつ φ／ｃ≦０．１９ 及び／又は ｔ／ｃ≧０．３２ を満たすことを特徴とする。The present invention is also a resistor comprising a plurality of semicircular recesses on an outer periphery of a ceramic base, electrodes provided around the recesses, and a resistor between the electrodes. The thickness t of the base, the diameter φ of the recess, the length c of the short side of the base, and the pitch p of the recess are c ≦ 1.0 mm, p ≦ 0.5 mm, and φ / c ≦ 0.19 and / or t / It is characterized by satisfying c ≧ 0.32.
【００１０】[0010]
【発明の実施の形態】以下本発明の実施形態を図によっ
て説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.
【００１１】図１（ａ）に示すように本発明のセラミッ
ク基板１０は、表面に縦横の分割溝１１を備え、この分
割溝１１上にスルーホール１２を形成したものであり、
分割線１１に沿って分割することによって、図１（ｂ）
に示すように、長辺に複数の凹部１３ａを有する単体の
基体１３とすることができる。As shown in FIG. 1A, a ceramic substrate 10 according to the present invention is provided with vertical and horizontal dividing grooves 11 on the surface, and through holes 12 are formed on the dividing grooves 11.
By dividing along the dividing line 11, FIG.
As shown in FIG. 5, a single base 13 having a plurality of recesses 13a on the long side can be obtained.
【００１２】このセラミック基板１０は、Ａｌ2 Ｏ3 を
主成分としＳｉＯ2 やＭｇＯ等を含むアルミナセラミッ
クスからなるが、その他に、窒化アルミニウム、ムライ
ト、ジルコニア等を主成分とするセラミックスを用いる
こともできる。そして、これらの原料粉末をドクターブ
レード法等によってシート状に成形し、得られたグリー
ンシートを金型を用いて打ち抜くと同時に分割溝１１と
スルーホール１２を形成し、その後、所定条件で焼成す
ることによって得られる。The ceramic substrate 10 is made of alumina ceramics containing Al 2 O 3 as a main component and containing SiO 2 , MgO or the like. In addition, ceramics containing aluminum nitride, mullite, zirconia or the like as a main component may be used. it can. Then, these raw material powders are formed into a sheet shape by a doctor blade method or the like, and the obtained green sheet is punched out using a mold, and at the same time, a dividing groove 11 and a through hole 12 are formed. Obtained by:
【００１３】また、このセラミック基板１０を用いて抵
抗器を製造する場合は、図２に示すようにスルーホール
１２の周囲にＡｇ−Ｐｄ等からなるペーストを印刷して
電極２１を形成し、各電極２１間に図３に示すような抵
抗体２２及び保護膜（不図示）等を形成した後、分割線
１１に沿って分割することによって、長辺に備えた凹部
１３ａの周囲を電極２１とした抵抗器２０を得ることが
できる。When a resistor is manufactured using the ceramic substrate 10, a paste made of Ag-Pd or the like is printed around the through hole 12 to form an electrode 21 as shown in FIG. After a resistor 22 and a protective film (not shown) as shown in FIG. 3 are formed between the electrodes 21 and the like, they are divided along the dividing line 11 so that the periphery of the concave portion 13a provided on the long side is formed with the electrode 21. Resistor 20 can be obtained.
【００１４】このようなセラミック基板１０及び抵抗器
２０において、抵抗器２０を小型化しようとすると、電
極２１の印刷時に隣合う電極２１間の短絡の問題や、プ
リント基板上への実装時の破損の問題があるが、以下に
詳述するように、各部の寸法を所定範囲内とすれば良い
ことを見出した。In such a ceramic substrate 10 and the resistor 20, if the resistor 20 is to be miniaturized, a problem of a short circuit between the adjacent electrodes 21 at the time of printing the electrodes 21 and a breakage at the time of mounting on the printed circuit board. However, as described in detail below, it has been found that the dimensions of each part may be within a predetermined range.
【００１５】即ち、本発明では、上記セラミック基板１
０（基体１３）の厚みをｔ、スルーホール１２の径を
φ、分割後の基体１３の短辺の長さをｃ、スルーホール
１２のピッチをｐとしたとき、 ｃ≦１．０ｍｍ・・・式１ ｐ≦０．５ｍｍ・・・式２ を満たすようにしてある。これは、小型の抵抗器２０で
あることを意味しており、式１、２の範囲外の寸法であ
れば、近年の小型化の要求に応えることができないため
である。なお、製造可能とするためには、 ｃ≧０．６ｍｍ ｐ≧０．３ｍｍ とすることが好ましい。That is, in the present invention, the ceramic substrate 1
When the thickness of the substrate 0 (base 13) is t, the diameter of the through hole 12 is φ, the length of the short side of the divided base 13 is c, and the pitch of the through holes 12 is p, c ≦ 1.0 mm Formula 1 p ≦ 0.5 mm Formula 2 is satisfied. This means that the resistor 20 is small, and if the size is out of the range of Expressions 1 and 2, it cannot meet the recent demand for miniaturization. In addition, in order to enable manufacture, it is preferable that c ≧ 0.6 mm and p ≧ 0.3 mm.
【００１６】さらに本発明では、上記式１、２に加えて φ／ｃ≦０．１９・・・式３ としてある。これは、スルーホール１２の径φを小さく
することによってスルーホール１２の間隔を広くし、電
極２１形成時の短絡を防止するためであり、式３の範囲
外の寸法であれば、電極２１の形成時の短絡のために極
めて歩留りが悪くなってしまう。なお、製造可能とする
ためには、 φ／ｃ≧０．１ とすることが好ましい。Further, in the present invention, φ / c ≦ 0.19... This is to reduce the diameter φ of the through-hole 12 to increase the interval between the through-holes 12 and prevent a short circuit when the electrode 21 is formed. The yield is extremely poor due to the short circuit during the formation. Note that it is preferable that φ / c ≧ 0.1 in order to enable manufacture.
【００１７】また、本発明では、上記式１、２に加えて ｔ／ｃ≧０．３２・・・式４ としてある。これは、厚みｔを大きくすることによっ
て、抵抗器２０の実装時の破損を防止するようにしたも
のであり、式４の範囲外では実装時の破損のために歩留
りが悪くなってしまう。ただし、抵抗器２０の小型化の
ためには、 ｔ／ｃ≦０．４７ とすることが好ましい。Further, in the present invention, t / c ≧ 0.32... This is to prevent the resistor 20 from being damaged at the time of mounting by increasing the thickness t. Outside the range of Expression 4, the yield at the time of mounting is deteriorated due to the damage at the time of mounting. However, in order to reduce the size of the resistor 20, it is preferable that t / c ≦ 0.47.
【００１８】なお、式３と式４については、いずれか一
方を満たしていれば良いが、両方を満たしていることが
好ましい。It is sufficient that either of the equations (3) and (4) is satisfied, but it is preferable that both are satisfied.
【００１９】ところで、式３、４を合わせれば、セラミ
ック基板１０の厚みｔが大きく、スルーホール１２の径
φが非常に小さいことになる。このように小さい径のス
ルーホール１２を形成する場合、セラミック基板１０の
製造行程でグリーンシートを打ち抜く行程でピンが折れ
やすく、また打ち抜いたくずが金型内で詰まりやすいと
いう問題がある。そこで本発明では、セラミック基板１
０の製造行程で原料粉末に可塑剤等を適量添加して、柔
らかいグリーンシートを作製することによりピンの折れ
を防止した。また、ピンで打ち抜いたくずを吸引除去す
ることにより、金型内に詰まらないようにした。このよ
うに製造することによって、上記のような小径のスルー
ホール１２を作製することができる。By the way, when Expressions 3 and 4 are combined, the thickness t of the ceramic substrate 10 is large, and the diameter φ of the through hole 12 is very small. In the case where the through hole 12 having such a small diameter is formed, there is a problem that pins are easily broken in a process of punching a green sheet in a process of manufacturing the ceramic substrate 10, and the cut waste is easily clogged in a mold. Therefore, in the present invention, the ceramic substrate 1
In the manufacturing process of No. 0, a plasticizer or the like was added in an appropriate amount to the raw material powder to produce a soft green sheet, thereby preventing pin breakage. In addition, debris punched with a pin was removed by suction to prevent the die from being clogged. By manufacturing in this manner, the small-diameter through hole 12 as described above can be manufactured.
【００２０】このような本発明のセラミック基板１０を
用いた抵抗器２０は、その寸法が２．０×１．０ｍｍ以
下と極めて小型化することができ、電極２１印刷時の短
絡や実装時の破損を防止することができる。The size of the resistor 20 using the ceramic substrate 10 of the present invention can be extremely reduced to 2.0 × 1.0 mm or less. Damage can be prevented.
【００２１】また、図１、２の例では抵抗器２０を成す
基体１３の一つの長辺に多数の凹部１３ａを備えたもの
を示したが、一つの長辺に一つの凹部１３ａを有する形
状の抵抗器２０にも適用できる。In addition, in the example of FIGS. 1 and 2, the base 13 forming the resistor 20 has a plurality of recesses 13 a on one long side, but the base 13 has a shape having one recess 13 a on one long side. Of the resistor 20 can be applied.
【００２２】さらに、上記実施形態では円形のスルーホ
ール１２を示したが、これに限らず長円形や角形等のス
ルーホール１２とすることもできる。この場合のスルー
ホール１２の径φは、分割溝１１に沿った方向の長さと
する。Further, in the above embodiment, the circular through-hole 12 is shown, but the present invention is not limited to this, and the through-hole 12 may be an oval or a square. In this case, the diameter φ of the through hole 12 is the length in the direction along the division groove 11.
【００２３】[0023]
【実施例】図１、２に示すセラミック基板１０として、
アルミナセラミックスを用い、厚みｔを０．３２ｍｍ、
分割後の基体１３の短辺の長さｃを１．０ｍｍ、スルー
ホール１２のピッチｐを０．５ｍｍとして、スルーホー
ル１２の径φを種々に変化させたものを作製した。それ
ぞれ、図２に示すようにスルーホール１２の周囲に電極
２１を印刷する行程での、隣合う電極２１間の短絡によ
る不良発生率を調べた。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a ceramic substrate 10 shown in FIGS.
Using alumina ceramics, thickness t is 0.32 mm,
The length c of the short side of the base 13 after division was set to 1.0 mm, the pitch p of the through holes 12 was set to 0.5 mm, and the diameter φ of the through holes 12 was variously changed. In each of the processes of printing the electrode 21 around the through hole 12 as shown in FIG. 2, the defect occurrence rate due to a short circuit between the adjacent electrodes 21 was examined.
【００２４】結果は表１に示すように、φ／ｃが０．１
９を超えるもの（Ｎｏ．１，２）では短絡不良が発生し
たのに対し、φ／ｃを０．１９以下とした本発明実施例
（Ｎｏ．３，４）では全く短絡不良が生じなかった。The results are shown in Table 1, where φ / c is 0.1
In the case of the present invention in which φ / c was 0.19 or less (Nos. 3 and 4), no short-circuit failure occurred, whereas in cases exceeding 9 (Nos. 1 and 2), a short-circuit failure occurred. .
【００２５】[0025]
【表１】 [Table 1]
【００２６】次に、上記と同様にして、スルーホール１
２の径φを０．１９ｍｍとして、厚みｔを種々に変化さ
せた抵抗器２０を作製した。それぞれ、プリント基板へ
実装する際の割れの発生率を調べた。Next, in the same manner as above,
A resistor 20 having a diameter φ of 0.12 mm and a thickness t variously changed was manufactured. In each case, the incidence of cracking when mounted on a printed circuit board was examined.
【００２７】結果は表２に示すように、ｔ／ｃが０．３
２未満のもの（Ｎｏ．５，６）では実装時に割れが発生
したのに対し、ｔ／ｃを０．３２以上とした本発明実施
例（Ｎｏ．７，８）では全く割れが生じなかった。As shown in Table 2, t / c was 0.3
In the case of the present invention (Nos. 7 and 8) in which t / c was 0.32 or more, no cracks occurred in the case of the sample of less than 2 (Nos. 5 and 6), whereas in the case of t / c of 0.32 or more. .
【００２８】[0028]
【表２】 [Table 2]
【００２９】[0029]
【発明の効果】以上のように本発明によれば、表面に縦
横の分割溝と、この分割溝上の複数のスルーホールを備
えてなるセラミック基板であって、基板厚みｔ、スルー
ホール径φ、分割後の短辺の長さｃ、スルーホールのピ
ッチｐが、 ｃ≦１．０ｍｍ ｐ≦０．５ｍｍ であり、かつ φ／ｃ≦０．１９ 及び／又は ｔ／ｃ≧０．３２ を満たすことによって、スルーホールの周りに電極を印
刷する行程で隣合う電極間の短絡を防止することができ
る。また、このセラミック基板を用いて作製した抵抗器
は、プリント基板等への実装時の割れを防止することが
できる。As described above, according to the present invention, there is provided a ceramic substrate having vertical and horizontal dividing grooves on the surface and a plurality of through holes on the dividing grooves, wherein the substrate thickness t, the through hole diameter φ, The length c of the short side after division and the pitch p of the through holes are c ≦ 1.0 mm, p ≦ 0.5 mm, and satisfy φ / c ≦ 0.19 and / or t / c ≧ 0.32. This can prevent a short circuit between the adjacent electrodes in the process of printing the electrodes around the through holes. Further, a resistor manufactured using this ceramic substrate can prevent cracking when mounted on a printed circuit board or the like.
【００３０】その結果、製造行程の歩留りの高い小型の
抵抗器を得ることができる。As a result, it is possible to obtain a small-sized resistor having a high production yield.
【図１】（ａ）は本発明の分割溝を有するセラミック基
板の平面図、（ｂ）はこのセラミック基板を分割して得
られる基体の単体を示す斜視図である。FIG. 1A is a plan view of a ceramic substrate having a dividing groove according to the present invention, and FIG. 1B is a perspective view showing a single body of a base obtained by dividing the ceramic substrate.
【図２】本発明の分割溝を有するセラミック基板に電極
を印刷した状態の平面図である。FIG. 2 is a plan view showing a state in which electrodes are printed on a ceramic substrate having a dividing groove according to the present invention.
【図３】さまざまな抵抗器を示す平面図である。FIG. 3 is a plan view showing various resistors.
【図４】（ａ）は従来の分割溝を有するセラミック基板
の平面図、（ｂ）はこのセラミック基板を分割して得ら
れる基体の単体を示す斜視図である。FIG. 4A is a plan view of a conventional ceramic substrate having a dividing groove, and FIG. 4B is a perspective view showing a single body of a base obtained by dividing the ceramic substrate.
【図５】従来の分割溝を有するセラミック基板に電極を
印刷した状態の平面図である。FIG. 5 is a plan view showing a state in which electrodes are printed on a conventional ceramic substrate having a dividing groove.
１０：セラミック基板 １１：分割溝 １２：スルーホール １３：基体 ２０：抵抗器 ２１：電極 ２２：抵抗体 ｃ：基体の短辺の長さ ｔ：基体の厚み ｐ：スルーホールのピッチ φ：スルーホールの径 10: Ceramic substrate 11: Dividing groove 12: Through hole 13: Base 20: Resistor 21: Electrode 22: Resistor c: Length of short side of base t: Thickness of base p: Pitch of through hole φ: Through hole Diameter
Claims (2)
数のスルーホールを備えてなるセラミック基板であっ
て、基板厚みｔ、スルーホール径φ、分割後の短辺の長
さｃ、スルーホールのピッチｐが、 ｃ≦１．０ｍｍ ｐ≦０．５ｍｍ であり、かつ φ／ｃ≦０．１９ 及び／又は ｔ／ｃ≧０．３２ を満たすことを特徴とする分割溝を有するセラミック基
板。1. A ceramic substrate provided with vertical and horizontal dividing grooves on a surface and a plurality of through holes on the dividing grooves, the substrate thickness t, the through hole diameter φ, the length c of the short side after division, A ceramic having a divided groove, wherein the pitch p of the through holes is c ≦ 1.0 mm, p ≦ 0.5 mm, and satisfies φ / c ≦ 0.19 and / or t / c ≧ 0.32. substrate.
有し、該凹部の周囲に電極を備え、各電極間に抵抗体を
備えてなる抵抗器であって、基体厚みｔ、凹部の径φ、
基体の短辺の長さｃ、凹部のピッチｐが、 ｃ≦１．０ｍｍ ｐ≦０．５ｍｍ であり、かつ φ／ｃ≦０．１９ 及び／又は ｔ／ｃ≧０．３２ を満たすことを特徴とする抵抗器。2. A resistor comprising a plurality of recesses on an outer periphery of a ceramic base, electrodes provided around the recesses, and a resistor between the electrodes, wherein the thickness of the base is t, the diameter of the recesses is φ,
The length c of the short side of the base and the pitch p of the concave portion are c ≦ 1.0 mm, p ≦ 0.5 mm, and satisfy φ / c ≦ 0.19 and / or t / c ≧ 0.32. Characteristic resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8320504A JPH10156821A (en) | 1996-11-29 | 1996-11-29 | Ceramic base having division grooves and resistor using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8320504A JPH10156821A (en) | 1996-11-29 | 1996-11-29 | Ceramic base having division grooves and resistor using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10156821A true JPH10156821A (en) | 1998-06-16 |
Family
ID=18122196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8320504A Pending JPH10156821A (en) | 1996-11-29 | 1996-11-29 | Ceramic base having division grooves and resistor using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10156821A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001143913A (en) * | 1999-11-11 | 2001-05-25 | Matsushita Electric Ind Co Ltd | Multiple chip resistor |
| JP2002043717A (en) * | 2000-07-28 | 2002-02-08 | Matsushita Electric Ind Co Ltd | Electronic parts and its manufacturing method |
| CN102142308A (en) * | 2011-01-12 | 2011-08-03 | 深圳顺络电子股份有限公司 | Laminated voltage-sensitive resistor array |
-
1996
- 1996-11-29 JP JP8320504A patent/JPH10156821A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001143913A (en) * | 1999-11-11 | 2001-05-25 | Matsushita Electric Ind Co Ltd | Multiple chip resistor |
| JP2002043717A (en) * | 2000-07-28 | 2002-02-08 | Matsushita Electric Ind Co Ltd | Electronic parts and its manufacturing method |
| CN102142308A (en) * | 2011-01-12 | 2011-08-03 | 深圳顺络电子股份有限公司 | Laminated voltage-sensitive resistor array |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2000138455A (en) | Manufacture of ceramic multilayer board | |
| JPH08139230A (en) | Ceramic circuit board and its manufacture | |
| JPH10156821A (en) | Ceramic base having division grooves and resistor using the same | |
| JP5255899B2 (en) | Chip resistor manufacturing method and chip resistor | |
| JPH10156823A (en) | Ceramic base having division grooves and resistor using the same | |
| JP2001332857A (en) | Manufacturing method for wiring board | |
| JP2002223044A (en) | Method for manufacturing electronic component and aggregate board | |
| JP3610173B2 (en) | Ceramic substrate having dividing grooves | |
| JP3301927B2 (en) | Method of manufacturing ceramic substrate having divided grooves | |
| JP2000164451A (en) | Laminated ceramic capacitor | |
| JP2922685B2 (en) | Multi-cavity ceramic substrate | |
| JPH09306710A (en) | Chip network electronic component | |
| JP2003273272A (en) | Ceramic board and its manufacturing method | |
| JP3058999B2 (en) | Mejiro wiring board | |
| JP2005243704A (en) | Coupling ceramic wiring board and its manufacturing method | |
| JP3325483B2 (en) | Method of manufacturing glaze substrate for thermal head | |
| JPH11111502A (en) | Ceramic board for electronic component | |
| JPH0239586A (en) | Ceramic circuit board | |
| JP3840146B2 (en) | Multi-piece ceramic substrate | |
| JP2003338404A (en) | Ceramic substrate having dividing grooves and manufacturing method thereof | |
| JP2004022958A (en) | Multiple-demarcated ceramic substrate | |
| JPH03134974A (en) | Manufacture of jumper chip component | |
| JPH10107442A (en) | Method of manufacturing circuit substrate | |
| JP2005136172A (en) | Wiring substrate capable of being divided into a multitude of pieces | |
| JPH058971U (en) | Multi-cavity ceramic board |