JPH11111502A - Ceramic board for electronic component - Google Patents
Ceramic board for electronic componentInfo
- Publication number
- JPH11111502A JPH11111502A JP9267582A JP26758297A JPH11111502A JP H11111502 A JPH11111502 A JP H11111502A JP 9267582 A JP9267582 A JP 9267582A JP 26758297 A JP26758297 A JP 26758297A JP H11111502 A JPH11111502 A JP H11111502A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- groove
- primary
- thickness
- division groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
Landscapes
- Non-Adjustable Resistors (AREA)
- Manufacturing Cores, Coils, And Magnets (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップ抵抗器等の
チップ状の電子部品を製造する際に、母材として用いら
れるセラミック基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic substrate used as a base material when manufacturing chip-shaped electronic components such as chip resistors.
【０００２】[0002]
【従来の技術】従来より、チップ抵抗器は分割溝を有す
るセラミック基板上に抵抗体等を印刷し、分割すること
により製造している。2. Description of the Related Art Conventionally, a chip resistor is manufactured by printing a resistor or the like on a ceramic substrate having a dividing groove and dividing it.
【０００３】まず、セラミックス原料のスラリーより成
形したグリーンシートに縦横の分割溝を形成し、外辺打
ち抜き後、焼成して、図５（ａ）に示すセラミック基板
１０を得る。そして、このセラミック基板１０の一方又
は両方の面に導体と抵抗体を印刷し焼き付けた後、トリ
ミングを行って抵抗調整する。次に、オーバーコートガ
ラス等の保護層を印刷し焼き付けた後、一方方向の１次
分割溝１１より分割を行って、図５（ｂ）に示す短冊状
とする。その後、短冊状をしたセラミック基板１０の両
端を保持して、分割した破面１３に端面電極を成す導体
を印刷し焼き付けた後、更に他方向の２次分割溝１２で
分割し、図５（ｃ）に示すチップ抵抗器２０を得てい
た。First, vertical and horizontal dividing grooves are formed in a green sheet formed from a slurry of a ceramic raw material, and punching is performed on an outer side, followed by firing to obtain a ceramic substrate 10 shown in FIG. After printing and printing a conductor and a resistor on one or both surfaces of the ceramic substrate 10, trimming is performed to adjust the resistance. Next, after a protective layer such as overcoat glass is printed and baked, the protective layer is divided from the primary dividing grooves 11 in one direction to obtain a strip shape shown in FIG. 5B. Thereafter, while holding both ends of the strip-shaped ceramic substrate 10 and printing and printing a conductor forming an end surface electrode on the divided fractured surface 13, the substrate is further divided by the secondary division groove 12 in the other direction. The chip resistor 20 shown in c) was obtained.
【０００４】即ち、このチップ抵抗器２０は、セラミッ
ク基板１０の一方の面に、抵抗体２２とこれに接続する
導体２１及び保護層２３を有し、また端面に端面電極２
４を有している。そして、回路基板３０の所定位置に備
えた導体３１上にハンダ３２を盛り、マウンターを用い
て上記のチップ抵抗器２０を搭載し、各端面電極２４を
ハンダ３２と接続させて固定するようになっている。That is, this chip resistor 20 has a resistor 22, a conductor 21 connected thereto and a protective layer 23 on one surface of a ceramic substrate 10, and an end face electrode 2 on an end face.
Four. Then, the solder 32 is put on the conductor 31 provided at a predetermined position of the circuit board 30, the above-described chip resistor 20 is mounted using a mounter, and each end face electrode 24 is connected and fixed to the solder 32. ing.
【０００５】なお、上記セラミック基板１０は、アルミ
ナを主成分とするセラミックスからなり、その厚みは最
も薄いもので０．３４〜０．４８ｍｍ程度のものが使用
されている。The ceramic substrate 10 is made of a ceramic containing alumina as a main component, and has the thinnest thickness of about 0.34 to 0.48 mm.
【０００６】[0006]
【発明が解決しようとする課題】ところで、近年、電子
機器の小型化に伴って、各種電子部品も小型化が進んで
いる。例えば、チップ抵抗器２０の寸法は、３．２×
１．６ｍｍから２×１．２５ｍｍ、１．６×０．８ｍ
ｍ、１×０．５ｍｍ、さらには０．６×０．３ｍｍと非
常に小さなものが求められており、その母材となるセラ
ミック基板１０の要求特性も厳しいものとなっており、
さまざまな問題が生じている。In recent years, various electronic components have been miniaturized with the miniaturization of electronic devices. For example, the size of the chip resistor 20 is 3.2 ×
1.6 x 2 x 1.25 mm, 1.6 x 0.8 m
m, 1 × 0.5 mm, and further, very small ones of 0.6 × 0.3 mm are required, and the required characteristics of the ceramic substrate 10 as a base material thereof are also severe.
Various problems have arisen.
【０００７】例えば、セラミック基板１０を１次分割溝
１１に沿って短冊状に分割する際に、２次分割溝１２ま
で同時に割れてしまうという不都合があった。For example, when the ceramic substrate 10 is divided into strips along the primary dividing grooves 11, there is a disadvantage that the ceramic substrate 10 is simultaneously broken up to the secondary dividing grooves 12.
【０００８】即ち、図５（ｃ）に示すように、チップ抵
抗器２０には端面電極２４が必要であり、この端面電極
２４を効率的に印刷するために、図５（ｂ）に示すよう
にセラミック基板１０をまず１次分割溝１１のみで分割
して短冊状にし、その破面１３に導体を印刷する必要が
ある。この時、２次分割溝１２が同時に割れてしまう
と、導体を印刷する装置が頻繁に停止する等の問題が発
生する。That is, as shown in FIG. 5C, the chip resistor 20 requires an end face electrode 24. In order to print the end face electrode 24 efficiently, as shown in FIG. First, it is necessary to divide the ceramic substrate 10 into strips only by the primary division grooves 11, and to print a conductor on the broken surface 13. At this time, if the secondary division grooves 12 are broken at the same time, problems such as frequently stopping the apparatus for printing conductors occur.
【０００９】なお、この問題を解決するために、１次分
割溝１１と２次分割溝１２の深さを異ならせることも行
われている。しかし、分割溝の先端に存在するマイクロ
クラックのためにその深さが安定せず、またセラミック
基板１０に不均一な反りやうねり、あるいは厚みのばら
つきが生じると、ローラー等で分割する際に不均一な力
が基板に加わるために、やはり１次分割溝１１で分割す
る際に２次分割溝１２も割れる事があった。Incidentally, in order to solve this problem, the depth of the primary division groove 11 and the secondary division groove 12 are also made different. However, if the depth is not stable due to the microcracks existing at the tip of the dividing groove, and if the ceramic substrate 10 has uneven warpage, undulation, or uneven thickness, it is difficult to divide the ceramic substrate 10 with a roller or the like. Since a uniform force is applied to the substrate, the secondary division groove 12 may also be broken when the division is performed by the primary division groove 11.
【００１０】さらに、近年、上記チップ抵抗器２０をマ
ウンターで回路基板３０上に搭載する速度を極限まで高
めているために、搭載時に大きな圧力がチップ抵抗器２
０に加わり、セラミック基板１０に割れやクラックが発
生するという問題があり、その結果回路の信頼性を低下
させる原因となっていた。Further, in recent years, since the mounting speed of the chip resistor 20 on the circuit board 30 by the mounter has been increased to the utmost, a large pressure is applied during mounting.
In addition to the above, there is a problem that cracks and cracks occur in the ceramic substrate 10, and as a result, the reliability of the circuit is reduced.
【００１１】また、上記分割溝を形成する場合は、一定
間隔で並べた刃をセラミックグリーンシートに押し当て
て形成していたが、チップ抵抗器２０の小型化に伴い、
刃の間隔が小さくなると、押し当てた刃にグリーンシー
トが張りついてしまうことがあった。このような場合
は、空気を噴出して剥がすことが行われているが、特に
グリーンシートが薄くなると、均一に剥がすことが困難
になり、金型の二重押しや、最悪の場合金型破損等の問
題が生じていた。In the case of forming the above-mentioned divided grooves, the blades arranged at regular intervals are pressed against the ceramic green sheet.
When the distance between the blades was small, the green sheet sometimes stuck to the pressed blade. In such a case, air is blown off and peeled off.However, especially when the green sheet is thin, it is difficult to peel it off evenly, and double pressing of the mold or breakage of the mold in the worst case And other problems.
【００１２】さらに、チップ抵抗器等が小さくなると、
上記セラミック基板１０上に導体２１を印刷する際に、
分割溝を伝わって他の導体２１と繋がってしまい、トリ
ミング工程で正しく抵抗値を測定できなくなるという不
都合もあった。Further, when the chip resistor and the like become smaller,
When printing the conductor 21 on the ceramic substrate 10,
There is also an inconvenience that the resistance value cannot be measured correctly in the trimming process because the conductor is connected to another conductor 21 along the dividing groove.
【００１３】[0013]
【課題を解決するための手段】そこで本発明は、各種電
子部品の母材として用いられるセラミック基板におい
て、厚みが０．１〜０．３ｍｍであり、この厚みに対し
て３０〜７０％の深さの分割溝を有することを特徴とす
る。SUMMARY OF THE INVENTION Accordingly, the present invention provides a ceramic substrate used as a base material of various electronic parts, which has a thickness of 0.1 to 0.3 mm and a depth of 30 to 70% of this thickness. It is characterized in that it has a dividing groove.
【００１４】即ち、本発明では、セラミック基板の厚み
を０．１〜０．３ｍｍと非常に薄くすることによって、
一方側の面に備えた導体のみで回路基板上のハンダと接
続することができ、端面電極の必要をなくせることを見
出した。そのため、端面電極の印刷工程が必要ないこと
から、製造工程を簡略化できるとともに、１次分割溝の
分割時に２次分割溝まで割れてしまっても大きな問題と
なることはない。さらに、このように薄くすることによ
って、より小型の電子部品に好適に対応することができ
る。That is, in the present invention, by making the thickness of the ceramic substrate as very thin as 0.1 to 0.3 mm,
It has been found that only the conductor provided on one side can be connected to the solder on the circuit board, eliminating the need for an end face electrode. For this reason, since the step of printing the end face electrodes is not required, the manufacturing process can be simplified, and there is no significant problem even if the primary divisional grooves are broken down to the secondary divisional grooves. Furthermore, by making such a thinner, it is possible to suitably cope with smaller electronic components.
【００１５】また、本発明は、各種電子部品の母材とし
て用いられるセラミック基板において、縦横の分割溝を
有し、この分割溝に囲まれる最小領域の短辺に対する基
板の厚みの比を０．２５〜１．０の範囲にしたことを特
徴とする。Further, according to the present invention, a ceramic substrate used as a base material of various electronic components has vertical and horizontal dividing grooves, and a ratio of a thickness of the substrate to a short side of a minimum region surrounded by the dividing grooves is set to 0.1. The range is from 25 to 1.0.
【００１６】即ち、本発明は、非常に小型の電子部品で
あっても、その短辺と厚みの比を上記範囲内とすること
によって、高速で搭載する際に割れやクラックが生じる
ことを防止できるようにしたものである。That is, the present invention prevents the generation of cracks and cracks during high-speed mounting by setting the ratio of the short side to the thickness of the electronic component within the above range, even for a very small electronic component. It is made possible.
【００１７】さらに本発明は、各種電子部品の母材とし
て用いられるセラミック基板であって、縦横の１次分割
溝と２次分割溝を有し、１次分割溝の深さと角度をそれ
ぞれ２次分割溝よりも大きくしたことを特徴とする。Further, the present invention relates to a ceramic substrate used as a base material of various electronic components, comprising a vertical and horizontal primary division groove and a secondary division groove, wherein the depth and angle of the primary division groove are each set to a secondary value. It is characterized in that it is larger than the dividing groove.
【００１８】また、本発明は、上記１次分割溝の角度を
３０〜６０°、２次分割溝の角度を２５〜４０°の範囲
としたことを特徴とする。Further, the present invention is characterized in that the angle of the primary dividing groove is in the range of 30 to 60 ° and the angle of the secondary dividing groove is in the range of 25 to 40 °.
【００１９】即ち、より深く形成する１次分割溝の角度
を大きくすることによって、グリーンシートに刃を押し
当てて加工する際に、刃へのグリーンシートの張りつき
を防止できるようにしたものである。That is, by increasing the angle of the primary division groove formed deeper, it is possible to prevent the green sheet from sticking to the blade when the blade is pressed against the green sheet for processing. .
【００２０】さらに本発明は、上記１次分割溝の幅を、
２次分割溝との交点で狭くなるようにしたことによっ
て、印刷した導体が分割溝を伝わって他の導体と繋がる
ことを防止するようにしたものである。Further, according to the present invention, the width of the primary dividing groove is
By narrowing at the intersection with the secondary division groove, the printed conductor is prevented from traveling along the division groove and being connected to another conductor.
【００２１】また本発明は、上記セラミック基板が、９
３〜９７重量％のＡｌ2 Ｏ3 を主成分とし、添加成分の
重量比がＳｉＯ2 ５２〜６８％、ＣａＯ２〜１０．５
％、ＭｇＯ２５．５〜４２％であることを特徴とする。
さらに本発明は、上記セラミック基板が、平均粒径１２
μｍ以下のアルミナセラミックスからなることを特徴と
する。Further, according to the present invention, the ceramic substrate is preferably made of 9
The main component is 3 to 97% by weight of Al 2 O 3 , and the weight ratio of the additional components is 52 to 68% of SiO 2 and 2 to 10.5% of CaO.
%, And MgO 25.5 to 42%.
Further, the present invention provides the above-mentioned ceramic substrate, wherein the average particle diameter is 12
It is characterized by being made of alumina ceramics of μm or less.
【００２２】即ち、上記組成や平均粒径の範囲内とする
ことによって、強度の高いセラミック基板を得られるた
め、上述したように厚みを非常に薄くしても破損等を防
止することができる。また、電子部品を高速で搭載する
際にも割れやクラックの発生を防止できる。That is, by setting the composition and the average particle size within the above ranges, a ceramic substrate having a high strength can be obtained, so that breakage or the like can be prevented even if the thickness is extremely thin as described above. In addition, when electronic components are mounted at a high speed, generation of cracks and cracks can be prevented.
【００２３】[0023]
【発明の実施の形態】以下、本発明の実施形態を図に基
づいて詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.
【００２４】図１に示すセラミック基板１０は、表面に
互いに直交する１次分割溝１１と２次分割溝１２を有し
ており、このセラミック基板１０の表面に抵抗体や導体
等を印刷した後、１次分割溝１１と２次分割溝１２で分
割することによって、図２に示すようなチップ抵抗器２
０を製造することができる。The ceramic substrate 10 shown in FIG. 1 has a primary divisional groove 11 and a secondary divisional groove 12 which are orthogonal to each other on the surface, and after a resistor, a conductor or the like is printed on the surface of the ceramic substrate 10. The chip resistor 2 shown in FIG. 2 is divided by the primary division groove 11 and the secondary division groove 12.
0 can be produced.
【００２５】また、このセラミック基板１０は、その厚
みＴを０．１〜０．３ｍｍと非常に薄くしてあり、その
１次（２次）分割溝１１（１２）の深さＤを厚みＴの３
０〜７０％としてある。そのため、詳細を後述するよう
に、チップ抵抗器を構成する際に端面電極を省略するこ
とができる。The ceramic substrate 10 has a very thin thickness T of 0.1 to 0.3 mm, and the depth D of the primary (secondary) dividing groove 11 (12) is 3
0% to 70%. Therefore, as will be described later in detail, it is possible to omit the end face electrode when configuring the chip resistor.
【００２６】なお、ここで、厚みＴを上記範囲としたの
は、０．１ｍｍ未満では、薄すぎるために強度が非常に
小さくなり、取扱時等に破損が生じやすくなるためであ
り、０．３ｍｍを超えると端面電極を省略することがで
きなくなるためである。また、厚みＴに対する分割溝の
深さＤの比を上記範囲としたのは、３０％未満では分割
性が低下し、７０％を超えると搬送工程等で誤って分割
されてしまう恐れが生じるためである。Here, the reason why the thickness T is set in the above range is that if the thickness T is less than 0.1 mm, the strength is extremely small because it is too thin, and it is easy to be damaged during handling. If it exceeds 3 mm, it is impossible to omit the end face electrode. The reason why the ratio of the depth D of the dividing groove to the thickness T is set in the above range is that if the ratio is less than 30%, the dividing property is reduced, and if the ratio exceeds 70%, there is a possibility that the division may be erroneously performed in a transport process or the like. It is.
【００２７】さらに、このセラミック基板１０は、縦横
の１次分割溝１１と２次分割溝１２に囲まれる最小領域
の短辺の長さＸに対する基板の厚みＴの比Ｔ／Ｘを０．
２５〜１．０の範囲にしてある。そのため、分割後のセ
ラミック基板１０の強度を高め、高速でのマウント時に
破損等を生じることを防止できる。Further, in the ceramic substrate 10, the ratio T / X of the thickness T of the substrate to the length X of the short side of the minimum region surrounded by the vertical and horizontal primary division grooves 11 and the secondary division grooves 12 is set to 0.1.
The range is from 25 to 1.0. Therefore, the strength of the divided ceramic substrate 10 can be increased, and breakage or the like can be prevented during mounting at high speed.
【００２８】ここで、比Ｔ／Ｘを上記範囲としたのは、
０．２５未満では厚みが薄すぎるために高速マウント時
に破損しやすく、一方１．０を超えると厚すぎて分割性
が低下するためである。Here, the ratio T / X is set in the above range because:
If it is less than 0.25, the thickness is too thin and it is easily broken at the time of high-speed mounting. On the other hand, if it exceeds 1.0, the thickness is too thick and the dividing property is reduced.
【００２９】なお、このセラミック基板１０の製造方法
は、所定のセラミックス原料のスラリーより成形したグ
リーンシートに刃を押し当てて縦横の１次分割溝１１、
２次分割溝１２を形成し、外辺を打ち抜いた後、焼成す
ることによって得ることができる。The method of manufacturing the ceramic substrate 10 is such that a blade is pressed against a green sheet formed from a slurry of a predetermined ceramic raw material so as to form vertical and horizontal primary division grooves 11,
It can be obtained by forming the secondary division groove 12, punching the outer edge, and firing.
【００３０】次に、このセラミック基板１０を用いて図
２に示すようなチップ抵抗器２０を製造する場合は、セ
ラミック基板１０の一方の面に導体２１と抵抗体２２を
印刷し焼き付けた後、トリミングを行って抵抗調整す
る。次に、オーバーコートガラス等の保護層２３を印刷
し焼き付けた後、１次分割溝１１及び２次分割溝１２よ
り分割を行って、図２に示すようなチップ抵抗器２０を
得ることができる。Next, when a chip resistor 20 as shown in FIG. 2 is manufactured using the ceramic substrate 10, a conductor 21 and a resistor 22 are printed and baked on one surface of the ceramic substrate 10, and then printed. Adjust the resistance by trimming. Next, after a protective layer 23 such as overcoat glass is printed and baked, the chip is divided from the primary division groove 11 and the secondary division groove 12 to obtain the chip resistor 20 as shown in FIG. .
【００３１】この時、１次分割溝１１の深さＤは基板厚
みＴの３０〜７０％まで形成していることから、上記導
体２１の印刷時に、導体２１はこの１次分割溝１１の中
まで入り込み、更に焼き付けにより分割溝先端に発生し
ているマイクロクラックまで流れ込むため、最終的なチ
ップ抵抗器２０の端面上部まで塗布されることになる。
しかも、セラミック基板１０の厚みＴが０．１〜０．３
ｍｍと非常に薄いため、チップ抵抗器２０の端面にはか
なりの部分まで導体２１が存在することになり、従来の
ような端面電極を省略することができる。At this time, since the depth D of the primary division groove 11 is formed to be 30 to 70% of the thickness T of the substrate, the conductor 21 is inserted into the primary division groove 11 when the conductor 21 is printed. , And further flows to the microcracks generated at the tip of the dividing groove by baking, so that the final chip resistor 20 is applied to the upper end face.
Moreover, the thickness T of the ceramic substrate 10 is 0.1 to 0.3.
mm, the conductor 21 exists to a considerable extent at the end face of the chip resistor 20, and the end face electrode as in the conventional case can be omitted.
【００３２】即ち、回路基板３０上の所定位置に備えた
導体３１上にハンダ３２を盛り、この上に上記チップ抵
抗器２０を搭載し、熱をかけて接着する。この時、セラ
ミック基板１０が非常に薄く、また端面上部まで導体２
１が塗布されていることから、端面電極なしでもこの導
体２１とハンダ３２を接続することができるのである。That is, the solder 32 is put on the conductor 31 provided at a predetermined position on the circuit board 30, and the chip resistor 20 is mounted thereon, and bonded by applying heat. At this time, the ceramic substrate 10 is very thin, and the conductor
Since 1 is applied, the conductor 21 and the solder 32 can be connected without the end face electrode.
【００３３】このように、本発明のセラミック基板１０
を用いれば、端面電極を省略してチップ抵抗器２０を得
ることができる。そのため、図３（ｂ）に示すように短
冊状に分割して破面１３に導体印刷を行う必要がない。
したがって、チップ抵抗器２０の製造工程を簡略化でき
るとともに、一度短冊状とする必要もないため、１次分
割溝１１の分割時に２次分割溝１２が割れてしまっても
不都合が生じることはない。As described above, the ceramic substrate 10 of the present invention
Is used, the chip resistor 20 can be obtained by omitting the end face electrode. Therefore, as shown in FIG. 3B, there is no need to divide into strips and print the conductor on the broken surface 13.
Therefore, the manufacturing process of the chip resistor 20 can be simplified, and it is not necessary to form the chip resistor once into a strip shape. Therefore, no inconvenience occurs even if the secondary division groove 12 is broken when the primary division groove 11 is divided. .
【００３４】次に本発明の他の実施形態を説明する。Next, another embodiment of the present invention will be described.
【００３５】図３（ａ）（ｂ）に示すように、本発明の
セラミック基板１０は、１次分割溝１１の深さＤ1 、角
度θ1 をそれぞれ２次分割溝１２の深さＤ2 、角度θ2
よりも大きくしてある。As shown in FIGS. 3A and 3B, in the ceramic substrate 10 of the present invention, the depth D 1 of the primary dividing groove 11 and the angle θ 1 are respectively set to the depth D 2 of the secondary dividing groove 12. , Angle θ 2
It is larger than.
【００３６】これは、最初に分割する１次分割溝１１の
方を深くすることによって、１次分割溝１１での分割時
に２次分割溝１２で割れてしまうことを防止するためで
ある。また、１次分割溝１１側の角度θ1 を大きくして
おくことによって、グリーンシートの加工時における刃
への張りつきを防止することができる。This is to prevent the primary division groove 11 to be divided first from being broken by the secondary division groove 12 at the time of division by the primary division groove 11 by making it deeper. Further, by increasing the angle θ 1 on the side of the primary division groove 11, it is possible to prevent sticking to the blade during processing of the green sheet.
【００３７】即ち、図３（ｃ）に示すように、グリーン
シート１０’に刃１９を押し当てて分割溝を形成する場
合、その刃先角度θが小さいほど応力Ｆが横方向に伝わ
り、隣接する刃１９にグリーンシート１０’を押しつ
け、張りつきが生じやすくなる。そのため、刃先角度θ
を大きくするほど、グリーンシート１０’の張りつきを
防止できることになる。That is, as shown in FIG. 3 (c), when the blade 19 is pressed against the green sheet 10 'to form a dividing groove, the stress F is transmitted in the lateral direction as the cutting edge angle θ is smaller, and the adjacent groove is formed. The green sheet 10 'is pressed against the blade 19, and sticking is likely to occur. Therefore, the cutting edge angle θ
Is larger, the sticking of the green sheet 10 'can be prevented.
【００３８】ただし、チップ抵抗器等が小型化されるに
つれて、この刃先角度θも極力小さくすることが求めれ
ていることから、本発明では、より深く形成する１次分
割溝１１側のみ角度θ1 を大きくすることによって、グ
リーンシート１０’の張りつきを防止するようにしたの
である。However, as chip resistors and the like are miniaturized, it is required that the cutting edge angle θ be as small as possible. Therefore, in the present invention, the angle θ 1 is set only on the side of the primary division groove 11 which is formed deeper. Is increased to prevent sticking of the green sheet 10 '.
【００３９】しかも、２次分割溝１２側の角度θ2 を小
さくしておけば、導体２１が２次分割溝１２を伝わって
流れることを防止できる。Moreover, if the angle θ 2 on the side of the secondary division groove 12 is reduced, the conductor 21 can be prevented from flowing along the secondary division groove 12.
【００４０】なお、上記１次分割溝１１の角度θ1 は３
０〜６０°、２次分割溝１２の角度θ2 は２５〜４０°
とし、両者の差θ1 −θ2 は５〜２５°の範囲とするこ
とが好ましい。The angle θ 1 of the primary dividing groove 11 is 3
0 to 60 °, the angle θ 2 of the secondary dividing groove 12 is 25 to 40 °
It is preferable that the difference θ 1 −θ 2 be in the range of 5 to 25 °.
【００４１】また、上記１次分割溝１１の深さＤ1 と２
次分割溝１２の深さＤ2 の差Ｄ1 −Ｄ2 は０．０３〜
０．１ｍｍの範囲内とすることが好ましい。Further, the depths D 1 and D 2 of the primary
The difference D 1 -D 2 of the depth D 2 of the next dividing grooves 12 0.03
It is preferable to set it within the range of 0.1 mm.
【００４２】そして、上記のように１次分割溝１１と２
次分割溝１２の角度や深さを設定しておけば、１次分割
溝１１の分割時に２次分割溝１２が割れてしまうことを
防止できるため、図５（ｂ）に示すような短冊状に分割
して端面電極を印刷する工程を行っても不良が生じるこ
とを防止できる。Then, as described above, the primary division grooves 11 and 2
If the angle and the depth of the secondary division groove 12 are set, it is possible to prevent the secondary division groove 12 from being broken at the time of dividing the primary division groove 11, so that the rectangular shape as shown in FIG. Even if the step of printing the end face electrode is performed by dividing into two, the occurrence of defects can be prevented.
【００４３】さらに、本発明の他の実施形態を図４に示
すように、上記１次分割溝１１における２次分割溝１２
との交点近傍を狭くすることもできる。そのため、１次
分割溝１１上に印刷した導体ペーストが２次分割溝１２
側に伝わることを防止することができる。FIG. 4 shows another embodiment of the present invention, as shown in FIG.
Can be narrowed near the intersection with. Therefore, the conductive paste printed on the primary division grooves 11 is
It can be prevented from being transmitted to the side.
【００４４】なお、図４に示すような形状とするために
は、まずグリーンシート１０’に刃１９を押し当てて１
次分割溝１１側を先に形成した後、これと直角方向に刃
１９を押し当てて２次分割溝１２を形成し、この時に先
に形成した１次分割溝１１側がやや変形するように刃１
９を押し当てることによって、図４に示すように１次分
割溝１１側の交点近傍を狭くすることができる。In order to obtain the shape as shown in FIG. 4, first, the blade 19 is pressed against the green sheet 10 'to make the shape as shown in FIG.
After the side of the next divisional groove 11 is formed first, the blade 19 is pressed in a direction perpendicular to the side to form the secondary divisional groove 12, and the blade is formed so that the side of the primary divisional groove 11 formed at this time is slightly deformed. 1
By pressing 9, the vicinity of the intersection on the side of the primary division groove 11 can be narrowed as shown in FIG. 4.
【００４５】また、１次分割溝１１は、通常、セラミッ
ク基板１０上に形成される最小領域の短辺側を形成し、
多連チップ抵抗等を製造するためにスルーホールを有す
る場合は、スルーホール上に形成される分割溝が１次分
割溝１１となる。The primary division groove 11 usually forms a short side of a minimum region formed on the ceramic substrate 10,
When a through-hole is provided for manufacturing a multiple chip resistor or the like, the division groove formed on the through-hole becomes the primary division groove 11.
【００４６】以上の本発明のセラミック基板１０では、
上述したように厚みＴを非常に薄くしてあるため、搬送
や印刷、焼成工程での破損を防止するために、その組
成、粒径を以下のように設定する。In the above ceramic substrate 10 of the present invention,
Since the thickness T is extremely thin as described above, the composition and the particle size are set as follows in order to prevent breakage in the transporting, printing, and firing steps.
【００４７】即ち、上記セラミック基板１０は、９３〜
９７重量％のＡｌ2 Ｏ3 を主成分とし、添加成分の重量
比がＳｉＯ2 ５２〜６８％、ＣａＯ２〜１０．５％、Ｍ
ｇＯ２５．５〜４２％の範囲内となるようにしてある。
また、その平均粒径を１２μｍ以下としてある。That is, the ceramic substrate 10
97% by weight of Al 2 O 3 as a main component, and the weight ratio of added components is 52 to 68% of SiO 2, 2 to 10.5% of CaO,
gO is set to be in the range of 25.5 to 42%.
The average particle size is set to 12 μm or less.
【００４８】ここで、Ａｌ2 Ｏ3 含有量を上記範囲とし
たのは、９３重量％未満では強度が低下するために、分
割溝が入った状態で印刷時の圧力やその他の取り扱い時
の衝撃等により破損する恐れがあるためである。また、
９７重量％を超えると、製造コスト、主に焼成コストや
設備コストが高くなるともに、導体２１等との接着性が
低下するためである。The reason why the Al 2 O 3 content is set in the above range is that if the content is less than 93% by weight, the strength is reduced. This is because there is a risk of damage due to such factors. Also,
If the content exceeds 97% by weight, the manufacturing cost, mainly the sintering cost and the equipment cost are increased, and the adhesion to the conductor 21 and the like is reduced.
【００４９】また、添加成分の重量比を上記範囲内とす
ることにより、焼成時のαーアルミナやスピネル以外の
異常結晶の晶出を防止し、安定した分割性を維持するこ
とができる。Further, by setting the weight ratio of the added components within the above range, it is possible to prevent abnormal crystals other than α-alumina and spinel from being crystallized at the time of firing, and to maintain a stable splitting property.
【００５０】さらに、平均結晶粒径を上記範囲内とした
のは、１２μｍを超えると強度が低下して、印刷時や取
扱時等に破損する恐れが生じるためである。The reason why the average crystal grain size is set within the above range is that if the average crystal grain size exceeds 12 μm, the strength is reduced and there is a possibility that the crystal may be damaged during printing or handling.
【００５１】なお、上記実施形態ではセラミック基板１
０の片面側に１次分割溝１１、２次分割溝１２を形成し
た例を示したが、両面にこれらの分割溝を形成すること
もできる。この場合は、両面の深さの和を分割溝の深さ
Ｄとし、この深さＤをセラミック基板１０の厚みＴの３
０〜７０％の範囲内としておけば良い。In the above embodiment, the ceramic substrate 1
Although the example in which the primary division grooves 11 and the secondary division grooves 12 are formed on one side of the reference numeral 0 is shown, these division grooves may be formed on both sides. In this case, the sum of the depths on both sides is defined as the depth D of the dividing groove, and this depth D is set to 3 times the thickness T of the ceramic substrate 10.
What is necessary is just to set it in the range of 0-70%.
【００５２】また、以上の実施形態では、チップ抵抗器
２０を例にとって説明したが、本発明のセラミック基板
１０はその他に、チップコンデンサやハイブリッドＩＣ
用基板等の各種電子部品の製造に用いることができる。In the above embodiment, the chip resistor 20 has been described as an example. However, the ceramic substrate 10 of the present invention may be replaced by a chip capacitor or a hybrid IC.
It can be used for manufacturing various electronic components such as a substrate for use.
【００５３】[0053]
【実施例】実施例１ Ａｌ2 Ｏ3 含有量９６重量％のアルミナセラミックスを
用い、その厚みＴを表１に示すように種々に変化させ、
分割溝の深さＤは基板の厚みＴの６０％とし、分割溝で
囲まれる最小領域の大きさを０．６×０．３ｍｍとした
セラミック基板１０を作製した。 Example 1 Alumina ceramics having an Al 2 O 3 content of 96% by weight was used, and its thickness T was variously changed as shown in Table 1.
The ceramic substrate 10 was manufactured in which the depth D of the dividing groove was 60% of the thickness T of the substrate, and the size of the minimum region surrounded by the dividing groove was 0.6 × 0.3 mm.
【００５４】それぞれ、片面のみに導体２１と抵抗体２
２を印刷し、１次分割後の破面に導体印刷を行わずに２
次分割を行ってチップ抵抗器２０を作製した。それぞ
れ、回路基板３０上に搭載して、ハンダ３２との接続に
より導通が取れるかどうかを調べた。その結果、導通が
取れたものを○、とれないものを×として表１に示す。The conductor 21 and the resistor 2 are provided only on one side, respectively.
2 without printing conductor on the fractured surface after primary division
Next, the chip resistor 20 was manufactured. Each of them was mounted on the circuit board 30, and it was examined whether or not conduction was obtained by connection with the solder 32. As a result, Table 1 shows the case where conduction was obtained, and X the case where conduction was not obtained.
【００５５】この結果より、厚みＴが０．３ｍｍを超え
るものでは導通が取れなかったのに対し、厚みＴを０．
３ｍｍ以下とすれば導通を取ることができた。From these results, it was found that electrical conduction could not be obtained when the thickness T exceeded 0.3 mm.
If it was 3 mm or less, conduction could be obtained.
【００５６】[0056]
【表１】 [Table 1]
【００５７】実施例２ 次に、実施例１と同様にして、セラミック基板１０の厚
さＴと、これに対する１次分割溝１１の深さＤの比を表
２に示すように種々に変化させたものを作製した。 Embodiment 2 Next, in the same manner as in Embodiment 1, the ratio of the thickness T of the ceramic substrate 10 to the depth D of the primary division groove 11 relative thereto was varied as shown in Table 2. Was produced.
【００５８】それぞれのセラミック基板１０を、導体２
１や抵抗体２２を印刷する工程に流し、工程中にセラミ
ック基板１０の割れの評価を行った。その結果、工程中
に割れが生じたものを×、割れなかったものを○で示
す。Each ceramic substrate 10 is connected to the conductor 2
1 and the resistor 22 were printed, and cracking of the ceramic substrate 10 was evaluated during the process. As a result, x indicates that a crack occurred during the process, and o indicates that it did not.
【００５９】結果を表２に示すように、セラミック基板
１０の厚みＴが０．１ｍｍ未満では、他の工程で分割溝
の割れが発生しやすかった。したがって、実施例１の結
果と合わせて、厚みＴは０．１〜０．３ｍｍの範囲が好
ましいことがわかる。As shown in Table 2, when the thickness T of the ceramic substrate 10 was less than 0.1 mm, cracks in the division grooves were likely to occur in other steps. Therefore, it can be seen that the thickness T is preferably in the range of 0.1 to 0.3 mm in combination with the result of Example 1.
【００６０】また、厚みＴを０．１ｍｍ以上とし、１次
分割溝１１の深さＤをこの厚みＴの７０％以下としてお
けば、他の工程での分割溝の割れの発生を防止すること
ができる。If the thickness T is set to 0.1 mm or more and the depth D of the primary division groove 11 is set to 70% or less of the thickness T, it is possible to prevent the division groove from cracking in other steps. Can be.
【００６１】[0061]
【表２】 [Table 2]
【００６２】実施例３ 次に、実施例２と同様にセラミック基板１０の厚みＴと
１次分割溝１１の深さＤを変更し、導体２１や抵抗体２
２を印刷、焼き付けした後、１次分割溝１１より分割機
を用い、短冊状に分割した。この時、１次分割溝１１だ
けで分割できたものを○、他でも割れたものを×で示
す。 Embodiment 3 Next, similarly to Embodiment 2, the thickness T of the ceramic substrate 10 and the depth D of the primary division groove 11 were changed, and the conductor 21 and the resistor 2 were changed.
2 was printed and baked, and divided into strips from the primary dividing groove 11 using a dividing machine. At this time, those that could be divided only by the primary division grooves 11 are indicated by ○, and those that were otherwise broken are indicated by X.
【００６３】結果を表３に示すように、セラミック基板
１０の厚みＴを０．１〜０．３ｍｍの範囲とした場合、
Ｄ／Ｔを３０％以上としておけば、良好な分割性が得ら
れることがわかる。As shown in Table 3, when the thickness T of the ceramic substrate 10 is in the range of 0.1 to 0.3 mm,
It can be seen that if D / T is set to 30% or more, good division properties can be obtained.
【００６４】[0064]
【表３】 [Table 3]
【００６５】実施例４ 次に、Ａｌ2 Ｏ3 含有量９６重量％のアルミナセラミッ
クスを用い、その厚みＴを表４に示すように種々に変化
させ、分割溝の深さＤは基板の厚みＴの６０％とし、分
割溝で囲まれる最小領域の短辺の長さＸを種々に変化さ
せたセラミック基板１０を作製した。 Example 4 Next, an alumina ceramic having an Al 2 O 3 content of 96% by weight was used, and its thickness T was variously changed as shown in Table 4. The ceramic substrate 10 was manufactured in which the length X of the short side of the minimum region surrounded by the division grooves was variously changed.
【００６６】各セラミック基板１０を用いてチップ抵抗
器２０を製造し、分割性の評価を行った。次に、得られ
たチップ抵抗器２０を回路基板３０に高速マウントした
際の導通及びクラックの有無を調べた。なお、分割性に
ついては、分割溝に沿って正しく割れたものを○、割れ
なかったものを×で示す。また、導通及びクラックの検
査は、１０００個中１個でもクラック又は導通不良が発
生しているものを×、発生していないものを○で示す。A chip resistor 20 was manufactured using each of the ceramic substrates 10 and the dividability was evaluated. Next, conduction and cracks were examined when the obtained chip resistor 20 was mounted on the circuit board 30 at high speed. Regarding the dividability, those that were correctly broken along the dividing groove are indicated by ○, and those that were not broken are indicated by x. In the inspection of conduction and cracks, even one out of 1,000 cracks or conduction failures are indicated by x, and those not occurring are indicated by o.
【００６７】結果を表４に示すように、短辺の長さＸに
対する厚みＴの比Ｔ／Ｘを０．２５〜１．０の範囲とし
ておけば、分割性が良好で、マウント時のクラックや導
通不良を防止できることがわかる。As shown in Table 4, when the ratio T / X of the thickness T to the length X of the short side is set in the range of 0.25 to 1.0, the dividing property is good and the crack at the time of mounting is good. It can be seen that the continuity failure and the conduction failure can be prevented.
【００６８】[0068]
【表４】 [Table 4]
【００６９】実施例５ 次に、上記と同様のセラミック基板１０において、１次
分割溝１１の深さＤ1を厚みＴの６０％、２次分割溝１
２の深さＤ2 を厚みＴの５０％とし、１次分割溝１１の
角度θ1 を種々に変化させたものを作製した。なお、い
ずれも２次分割溝１２の角度θ2 はθ1 よりも小さくし
た。 Embodiment 5 Next, in the same ceramic substrate 10 as described above, the depth D 1 of the primary dividing groove 11 is set to 60% of the thickness T,
2 of the depth D 2 to 50% of the thickness T, to produce what is varied the angle theta 1 of the primary split grooves 11 in various ways. In each case, the angle θ 2 of the secondary division groove 12 was smaller than θ 1 .
【００７０】それぞれ、グリーンシート１０’に分割溝
を敷設する際に、刃１９にグリーンシート１０’が付着
しないものを○、付着するものを×で示す。また、導体
ペースト印刷時に隣の導体と１次分割溝１１を介して短
絡しないものを○、短絡するものを×で示す。When a dividing groove is laid in the green sheet 10 ′, the one to which the green sheet 10 ′ does not adhere to the blade 19 is indicated by 、, and the one to which it adheres is indicated by X. In addition, those that do not short-circuit with the adjacent conductor through the primary division groove 11 during printing of the conductor paste are indicated by ○, and those that short-circuit are indicated by x.
【００７１】結果を表５に示すように、１次分割溝１１
の角度θ1 を３０〜６０°としておけば、刃１９への付
着はなく、導体ペーストの短絡も防止できることがわか
る。As shown in Table 5, the results are shown in Table 5.
It can be seen that if the angle θ 1 is set to 30 to 60 °, there is no adhesion to the blade 19 and the short circuit of the conductive paste can be prevented.
【００７２】[0072]
【表５】 [Table 5]
【００７３】実施例６ 次に、実施例５と同様にして、２次分割溝１２の角度θ
2 を種々に変化させたものを作製した。 Embodiment 6 Next, in the same manner as in Embodiment 5, the angle θ
2 were variously changed.
【００７４】それぞれ、導体２１、抵抗体２２、オーバ
ーコートガラスの保護層２３を印刷、焼付けを行いトリ
ミング後、１次分割溝１１より分割を行い、破面１３に
導体ペーストを塗布して２次分割溝１２へのペーストの
はい上がりを確認した。はい上がりが顕著で２次分割溝
１２を介して両方の破面１３がペーストでつながったら
×、つながらなかったら○で示す。更に分割溝形成時に
刃１９にグリーンシート１０’が付着したものを×、付
着しなかったものを○で示す。The conductor 21, the resistor 22, and the protective layer 23 of the overcoat glass are printed, baked and trimmed, and then divided from the primary dividing groove 11, and a conductive paste is applied to the fracture surface 13 to apply a secondary paste. The rise of the paste into the dividing grooves 12 was confirmed. The rise is remarkable, and when both of the fractured surfaces 13 are connected by the paste via the secondary dividing grooves 12, it is indicated by x, and when not connected, it is indicated by ○. Further, those where the green sheet 10 ′ adhered to the blade 19 at the time of forming the dividing groove are indicated by x, and those not adhered are indicated by ○.
【００７５】結果を表６に示すように、２時分割溝１２
の角度θ2 を２５〜４０°の範囲内としておけば、導電
ペーストの短絡やグリーンシートの刃への付着を防止で
きることがわかる。なお、２次分割溝１２の深さＤ2 は
１次分割溝１１よりも小さいために、２次分割溝１２で
は角度θ2 を２５゜まで小さくしても付着が発生しなか
った。The results are shown in Table 6, as shown in FIG.
It can be seen that if the angle θ 2 is within the range of 25 to 40 °, short-circuiting of the conductive paste and adhesion of the green sheet to the blade can be prevented. Since the depth D 2 of the secondary division groove 12 is smaller than that of the primary division groove 11, no adhesion occurs in the secondary division groove 12 even if the angle θ 2 is reduced to 25 °.
【００７６】[0076]
【表６】 [Table 6]
【００７７】実施例７ 次に、本発明のセラミック基板１０を形成するアルミナ
セラミックスとして、セラミックスの平均結晶粒径とＡ
ｌ2 Ｏ3 含有量を変更し、抗折強度を測定した結果を表
７に示す。 Embodiment 7 Next, as an alumina ceramic for forming the ceramic substrate 10 of the present invention, the average crystal grain size of the ceramic and A
Table 7 shows the results obtained by changing the l 2 O 3 content and measuring the bending strength.
【００７８】一般に、搬送時等の破損を防止するために
は抗折強度が３０ｋｇ／ｍｍ2 以上必要であり、この点
から、平均結晶粒径１２μｍ以下、Ａｌ2 Ｏ3 含有量９
３重量％以上としておけば良いことがわかる。Generally, in order to prevent breakage during transportation or the like, a transverse rupture strength of 30 kg / mm 2 or more is required. From this point, the average crystal grain size is 12 μm or less, and the Al 2 O 3 content is 9 or less.
It can be seen that the content should be set to 3% by weight or more.
【００７９】[0079]
【表７】 [Table 7]
【００８０】実施例８ 次に、実施例７と同様にして、Ａｌ2 Ｏ3 含有量と添加
物の組成比を変更し、それぞれ焼結性と異常結晶の有無
を評価した。なお、焼結性については、比重が３．６５
以上のものを○、３．６５未満のものを焼結不良として
×で示す。また、異常結晶については、αアルミナとス
ピネル以外の結晶が析出したものを×、その他のものを
○とした。 Example 8 Next, in the same manner as in Example 7, the Al 2 O 3 content and the composition ratio of the additives were changed, and the sinterability and the presence or absence of abnormal crystals were evaluated. As for the sinterability, the specific gravity was 3.65.
Those described above are indicated by ○, and those with less than 3.65 are indicated by x as poor sintering. Regarding the abnormal crystals, those in which crystals other than α-alumina and spinel were precipitated were evaluated as x, and the others were evaluated as ○.
【００８１】結果を表８に示すように、Ａｌ2 Ｏ3 含有
量９３〜９７重量％で、添加成分の重量比がＳｉＯ2 ５
２〜６８％、ＣａＯ２〜１０．５％、ＭｇＯ２５．５〜
４２％の範囲内であれば、焼結性に優れ、異常結晶の発
生を防ぐことができる。As shown in Table 8, when the Al 2 O 3 content is 93 to 97% by weight and the weight ratio of the added components is SiO 2 5
2 to 68%, CaO 2 to 10.5%, MgO 25.5 to
When the content is within the range of 42%, the sinterability is excellent, and occurrence of abnormal crystals can be prevented.
【００８２】[0082]
【表８】 [Table 8]
【００８３】[0083]
【発明の効果】以上にように本発明によれば、各種電子
部品の母材として用いられるセラミック基板であって、
厚みを０．１〜０．３ｍｍとし、この厚みに対して３０
〜７０％の深さの分割溝を有することによって、このセ
ラミック基板を用いてチップ抵抗器等を製造する場合
は、基板の片側のみに導体や抵抗体等を塗布するだけで
よく、端面電極を塗布せずに回路基板上に搭載すること
ができる。そのため、チップ抵抗器等の製造工程を簡略
化できるとともに、１次分割溝の分割次に２時分割溝で
割れてしまっても不都合が生じることがなく、また、各
種電子部品の小型化に対応することができる。As described above, according to the present invention, there is provided a ceramic substrate used as a base material of various electronic components,
The thickness is set to 0.1 to 0.3 mm.
When a chip resistor or the like is manufactured using this ceramic substrate by having a dividing groove having a depth of about 70%, it is only necessary to apply a conductor, a resistor, or the like to only one side of the substrate. It can be mounted on a circuit board without coating. Therefore, the manufacturing process of the chip resistor and the like can be simplified, and there is no inconvenience even if the primary division groove is split and then the two-time division groove is broken. can do.
【００８４】また、本発明によれば、各種電子部品の母
材として用いられるセラミック基板であって、縦横の分
割溝を有し、この分割溝に囲まれる最小領域の短辺に対
する基板の厚みの比を０．２５〜１．０の範囲としたこ
とによって、優れた分割性を維持したまま、高速で回路
基板上にマウントした場合でも、クラック等の発生を防
止できる。Further, according to the present invention, there is provided a ceramic substrate used as a base material of various electronic components, which has vertical and horizontal dividing grooves, and a thickness of the substrate with respect to a short side of a minimum region surrounded by the dividing grooves. By setting the ratio in the range of 0.25 to 1.0, generation of cracks and the like can be prevented even when mounted on a circuit board at a high speed while maintaining excellent division performance.
【００８５】さらに本発明によれば、各種電子部品の母
材として用いられるセラミック基板であって、縦横の１
次分割溝と２次分割溝を有し、１次分割溝の深さと角度
をそれぞれ２次分割溝よりも大きくしたことによって、
グリーンシートに分割溝を加工する際に、刃に張りつく
ことを防止できるとともに、導電ペーストが分割溝を流
れて短絡することを防止し、また１次分割溝の分割時に
２次分割溝が割れてしまうことを防止できる。Further, according to the present invention, there is provided a ceramic substrate used as a base material of various electronic components, wherein
By having a secondary division groove and a secondary division groove, by making the depth and angle of the primary division groove larger than the secondary division grooves,
When processing the dividing groove on the green sheet, it can prevent sticking to the blade, prevent the conductive paste from flowing through the dividing groove and short-circuit, and break the secondary dividing groove when dividing the primary dividing groove. Can be prevented.
【００８６】また、上記セラミック基板の材質として、
９３〜９７重量％のＡｌ2 Ｏ3 を主成分とし、添加成分
の重量比がＳｉＯ2 ５２〜６８％、ＣａＯ２〜１０．５
％、ＭｇＯ２５．５〜４２％であるアルミナセラミック
スを用いることにより、基板の強度を向上し、搬送時等
での破損を防止できる。Further, as the material of the ceramic substrate,
93 to 97% by weight of Al 2 O 3 as a main component, and the weight ratio of added components is 52 to 68% of SiO 2 and 2 to 10.5% of CaO.
%, And the use of alumina ceramics of 25.5 to 42% of MgO can improve the strength of the substrate and prevent damage during transportation and the like.
【図１】（ａ）は本発明のセラミック基板を示す斜視
図、（ｂ）は断面図である。FIG. 1A is a perspective view showing a ceramic substrate of the present invention, and FIG. 1B is a sectional view.
【図２】本発明のセラミック基板を用いたチップ抵抗器
を回路基板に搭載した状態の断面図である。FIG. 2 is a cross-sectional view showing a state where a chip resistor using the ceramic substrate of the present invention is mounted on a circuit board.
【図３】（ａ）は本発明の他の実施形態のセラミック基
板の１次分割溝に沿った断面図、（ｂ）は１次分割溝に
垂直な断面図、（ｃ）はグリーンシートの加工方法を示
す断面図である。3A is a cross-sectional view along a primary division groove of a ceramic substrate according to another embodiment of the present invention, FIG. 3B is a cross-sectional view perpendicular to the primary division groove, and FIG. It is sectional drawing which shows a processing method.
【図４】本発明のセラミック基板の分割溝を示す平面図
である。FIG. 4 is a plan view showing a dividing groove of the ceramic substrate of the present invention.
【図５】（ａ）は従来のセラミック基板を示す斜視図、
（ｂ）は短冊状に分割した状態の斜視図、（ｃ）はこの
基板を用いたチップ抵抗器を回路基板に搭載した状態の
断面図である。FIG. 5A is a perspective view showing a conventional ceramic substrate,
(B) is a perspective view in a state of being divided into strips, and (c) is a cross-sectional view in a state where a chip resistor using this substrate is mounted on a circuit board.
１０：セラミック基板 １１：１次分割溝 １２：２次分割溝 ２０：チップ抵抗器 ２１：導体 ２２：抵抗体 ２３：保護層 ３０：回路基板 ３１：導体 ３２：ハンダ Reference Signs List 10: ceramic substrate 11: primary division groove 12: secondary division groove 20: chip resistor 21: conductor 22: resistor 23: protective layer 30: circuit board 31: conductor 32: solder
Claims (7)
ミック基板であって、厚みが０．１〜０．３ｍｍであ
り、この厚みに対して３０〜７０％の深さの分割溝を有
することを特徴とする電子部品用セラミック基板。1. A ceramic substrate used as a base material of various electronic parts, having a thickness of 0.1 to 0.3 mm, and having a dividing groove having a depth of 30 to 70% of the thickness. A ceramic substrate for electronic components characterized by the above-mentioned.
ミック基板であって、縦横の分割溝を有し、この分割溝
に囲まれる最小領域の短辺に対する基板の厚みの比を
０．２５〜１．０の範囲にしたことを特徴とする電子部
品用セラミック基板。2. A ceramic substrate used as a base material of various electronic components, having a vertical and horizontal dividing groove, wherein a ratio of a thickness of the substrate to a short side of a minimum region surrounded by the dividing groove is 0.25 to 0.25. A ceramic substrate for electronic components, characterized in that the range is 1.0.
ミック基板であって、縦横の１次分割溝と２次分割溝を
有し、１次分割溝の深さと角度をそれぞれ２次分割溝よ
りも大きくしたことを特徴とする電子部品用セラミック
基板。3. A ceramic substrate used as a base material of various electronic components, having a vertical and horizontal primary division groove and a secondary division groove, wherein the depth and angle of the primary division groove are respectively set to be smaller than those of the secondary division groove. A ceramic substrate for electronic components, characterized by having a larger size.
次分割溝の角度を２５〜４０°の範囲としたことを特徴
とする請求項３記載の電子部品用セラミック基板。4. The angle of said primary dividing groove is 30-60 °, 2
4. The ceramic substrate for electronic parts according to claim 3, wherein the angle of the next division groove is in a range of 25 to 40 [deg.].
ミック基板であって、縦横の１次分割溝と２次分割溝を
有し、上記１次分割溝の幅が、２次分割溝との交点で狭
くなっていることを特徴とする電子部品用セラミック基
板。5. A ceramic substrate used as a base material of various electronic components, comprising a vertical and horizontal primary division groove and a secondary division groove, wherein the width of the primary division groove is different from that of the secondary division groove. A ceramic substrate for an electronic component, characterized in that it is narrowed at an intersection.
のＡｌ2 Ｏ3 を主成分とし、添加成分の重量比がＳｉＯ
2 ５２〜６８％、ＣａＯ２〜１０．５％、ＭｇＯ２５．
５〜４２％であることを特徴とする請求項１、２、３又
は５記載の電子部品用セラミック基板。6. The method according to claim 1, wherein said ceramic substrate is 93 to 97% by weight.
Of Al 2 O 3 as the main component, and the weight ratio of the added components is SiO 2
2 52-68%, CaO2-10.5%, MgO25.
The ceramic substrate for an electronic component according to claim 1, wherein the content is 5 to 42%.
以下のアルミナセラミックスからなることを特徴とする
請求項１、２、３又は５記載の電子部品用セラミック基
板。7. The ceramic substrate according to claim 1, wherein the average particle diameter is 12 μm.
6. The ceramic substrate for an electronic component according to claim 1, wherein the ceramic substrate is made of the following alumina ceramics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26758297A JP3574730B2 (en) | 1997-09-30 | 1997-09-30 | Ceramic substrates and chip resistors for electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26758297A JP3574730B2 (en) | 1997-09-30 | 1997-09-30 | Ceramic substrates and chip resistors for electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11111502A true JPH11111502A (en) | 1999-04-23 |
| JP3574730B2 JP3574730B2 (en) | 2004-10-06 |
Family
ID=17446781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26758297A Expired - Fee Related JP3574730B2 (en) | 1997-09-30 | 1997-09-30 | Ceramic substrates and chip resistors for electronic components |
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| Country | Link |
|---|---|
| JP (1) | JP3574730B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001176708A (en) * | 1999-12-15 | 2001-06-29 | Matsushita Electric Ind Co Ltd | Resistor |
| JP2002011718A (en) * | 2000-06-28 | 2002-01-15 | Ngk Spark Plug Co Ltd | Method for manufacturing ceramic connected substrate |
| JP2007173867A (en) * | 2007-03-20 | 2007-07-05 | Koa Corp | Substrate for electronic component, and method for manufacturing electronic component |
| KR100888130B1 (en) * | 2004-01-23 | 2009-03-11 | 허스키 인젝션 몰딩 시스템즈 리미티드 | Injection molding method and apparatus for continuous plastication |
-
1997
- 1997-09-30 JP JP26758297A patent/JP3574730B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001176708A (en) * | 1999-12-15 | 2001-06-29 | Matsushita Electric Ind Co Ltd | Resistor |
| JP2002011718A (en) * | 2000-06-28 | 2002-01-15 | Ngk Spark Plug Co Ltd | Method for manufacturing ceramic connected substrate |
| KR100888130B1 (en) * | 2004-01-23 | 2009-03-11 | 허스키 인젝션 몰딩 시스템즈 리미티드 | Injection molding method and apparatus for continuous plastication |
| JP2007173867A (en) * | 2007-03-20 | 2007-07-05 | Koa Corp | Substrate for electronic component, and method for manufacturing electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3574730B2 (en) | 2004-10-06 |
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