JPH10150140A - 半導体デバイスおよび表面実装パッケージ - Google Patents
半導体デバイスおよび表面実装パッケージInfo
- Publication number
- JPH10150140A JPH10150140A JP9291168A JP29116897A JPH10150140A JP H10150140 A JPH10150140 A JP H10150140A JP 9291168 A JP9291168 A JP 9291168A JP 29116897 A JP29116897 A JP 29116897A JP H10150140 A JPH10150140 A JP H10150140A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- die
- pins
- lead frame
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 241001080526 Vertica Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229920002994 synthetic fiber Polymers 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H01L23/495—Lead-frames or other flat leads
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Abstract
廉価にできる半導体デバイスを提供する。 【解決手段】 MOSFETダイ10およびショットキ
ーダイオードダイ12を共通のリードフレームパッド4
1上に装着し、それらドレインおよびカソードをそれぞ
れ一緒にそのパッド41に接続する。そのパッドはその
一方の側から伸び出た複数のピン5〜8を有する。リー
ドフレームは、その反対側にワイヤボンディングにより
FET10のソース、FET10のゲートおよびショッ
トキーダイオード12のアノードにそれぞれ接続され
る、分離して孤立の複数のピン1〜4を有する。リード
フレーム40およびダイは絶縁したハウジング30内に
成形され、リードフレーム40のピン1〜8は、表面実
装パッケージが構成されるように下向きに折り曲げられ
る。
Description
導体装置)に関し、特に種々の大きさおよび種々の接合
パターンの複数のダイ(チップともいう)が共通のリー
ドフレームと呼ばれる金属の枠に固定され共通のパッケ
ージ又はハウジング内に収容されている新規なデバイス
に関するものである。
ンバータ等のような多数の電気回路はMOSFETやシ
ョットキーダイオードのような多数の半導体素子(また
は半導体部品)を必要とする。これらの素子は携帯用の
電子装置にしばしば用いられ、通常分離して収容され支
持基板上に個別に装着する必要がある。
品は、基板のスペースをそれぞれ占めることになる。さ
らに、各部品は発熱するので、マイクロプロセッサのよ
うな別の素子が近くに存在する場合、これら別の素子の
動作に悪影響を及ぼすおそれがある。
スを減少させると共に、素子の総数を低減し、並びにパ
ワーコンバータおよび高密度の用途の他の電力サブ系の
組み立てコストを低減することが望ましい。
又はそれ以上の種々の半導体ダイを横方向に離間して共
通のリードフレーム上に装着し、各電力端子の第1の端
子をリードフレームに電気的に接続する。そして、主リ
ードフレーム本体は、各種々のダイの電力端子の第1の
端子に接続するために用いられ外部から使用できるピン
の第1の組を有する。これらのダイには、その上側に第
2の電力端子をも設け、これら第2の端子をリードフレ
ームの互いにおよび第1の外部ピンの組から分離された
各外部ピンにそれぞれ接続する。1個又はそれ以上のダ
イはMOSFETダイのゲート電極のような制御端子を
含むことができ、リードフレームの別の分離した孤立の
ピンをこのゲート端子に接続する。
な絶縁性の合成材料のハウジングを用いて覆うように成
形され、種々のピンをインラインでハウジングの縁部表
面を超えて延在させ外部接続できるようにする。
ト(foot print)」(床面などに置かれたデバイスが占め
る面積や形状のこと)を有する表面実装されたハウジン
グの形態をとることができる。一例として、MOSFE
Tダイおよびショットキーダイオードダイはハウジング
内に収容され、共通の導電性リードフレームパッドにそ
れぞれ半田付けされハウジング内で相互接続したドレイ
ン電極とカソード電極を有することができる。ダイの上
側のFETのソース端子およびゲート端子は絶縁された
リードフレームピンにワイヤボンディングされ、上側の
ショットキーダイオードのアノードも分離した孤立のピ
ンに接続され、パッケージに対して所望の外部接続する
ことができる。
ができるので、新規な本発明はSO−8型式の小さい出
力ラインパッケージを用いて実施した。
(電池)に対する電力の取り出しを低減することにより
DC−DCコンバータの効率を改善することができ、寿
命が一層長くなる。デスクトップ型の場合、このデバイ
スは電力浪費およびマイクロプロセッサのような温度感
受性部品付近での発熱が減少する。このデバイスは基板
(ボード)のスペースを大幅に節約すると共に、素子の
総数および組み立てコストを低減する。
22D2型のFET(−20V,90mΩのPチャネル
FET)およびショットキーダイオード(30V,1ア
ンペァ)をバックコンバータ(buck converter)回路に用
いた場合、基板スペースおよび組み立てコストが60%
節約された。
施の形態を詳細に説明する。
ダウン・コンバータ(step down converter:逓降変換
器)として知られている一般的なバックコンバータ回路
が示され、このバックコンバータ回路は携帯用電子デバ
イス等の回路基板上の集積回路およびプロセッサの電圧
を低下させるために通常用いられる。例えば、この回路
を用いて直流12Vの入力電圧を直流5V(又は、ある
場合には、直流3.3V)に低下させて集積回路や他の
負荷(図示せず)を駆動することができる。
ルMOSFET10を用いてこのFETのゲートGに接
続された適切な制御回路11の制御のもとでスイッチィ
ング機能を行う。FET10は、インターナショナル
レクチファイア コーポレイション社(International R
ectifier Corporation) から市販されている20V,9
0mΩのダイとすることができる。30V,1アンペア
のダイとすることができるショットキーダイオード12
は、FET10のドレインDに接続したカソードを有
し、インダクタ(誘導子)13およびキャパシタ(コン
デンサ)14へ出力電流を再循環するために用いる。後
述するように、本発明ではFET10およびショットキ
ーダイオード12はダイの形態として設け、かつ破線の
ブロック15により図示した単一パッケージの共通のリ
ードフレーム上に実装する。この新規な組合せにより、
デバイスの支持基板の60%の空間が節約され組み立て
コストも低減される。
ができること明らかである。例えば、図2は、スイッチ
ィングデバイスとしてのNチャネルMOSFET20
と、NチャネルMOSFET21、および同期整流を行
うため並列に接続したショットキーダイオード22とを
用いる同期バックコンバータ回路を示す。
ットキーダイオード22は、破線ブロック23で示すよ
うに、共通のハウジング内にパッケージされたダイとす
ることができる。この回路は、図1のショットキーダイ
オード12の「損失(lossy)」順方向電圧降下に
見られる損失を回避するのに有用である。ショットキー
ダイオード22はコントローラ24の「ウエイト(待
機)」状態の期間中、同期整流器により生ずる反転電流
を処理するので、この回路は垂直伝導(vertica
l condution)FET21の固有の本体ダイ
オード効果を回路から除去する。
レクチファイア コーポレイション社から市販されてい
る30V,35mΩのダイとすることができる。
図4に示すように、公知のハウジング型式SO−8の形
態をとることができる。すなわち、図3は、プラスチッ
クの絶縁性ハウジング30から伸び出た8個のイン−ラ
インピン1〜8(図4)を有するSO−8表面実装ハウ
ジングを示す。図4に示すように、FETダイ10およ
びショットキーダイオード12は、共通のリードフレー
ム上に内部装着される共に、後述するように、相互接続
して図1又は図2のように(適切なFETダイ10又は
21と共に、或いは他の回路形態中に)外部接続できる
ようにする。
びショットキーダイオード12のカソードは、後述する
ように、互いに接続すると共に共通のリードフレーム部
分(section) のピン5〜8に接続する。FET10のソ
ースおよびゲートは分離した孤立のピン3および4にワ
イヤボンディングによりそれぞれ接続し、ショットキー
ダイオード12のアノードは分離した孤立のピン1およ
び2にワイヤボンディングにより接続する。
ET10およびショットキーダイオード12を詳細に示
す。本例では、主パッド本体(body;ボディ)41を含
み、このパッド本体からピン5〜8が一体的に伸び出た
リードフレーム40を設ける。主パッド本体41は通常
のリードフレームのパッド本体よりも大きいので、FE
Tダイ10およびショットキーダイオード12は共にパ
ッド本体に装着することができる。本発明の新規な一形
態によれば、プラスチックの絶縁性ハウジング30の壁
部は通常のハウジングよりも薄くして、耐水性が顕著に
劣化することなく、より大きな主パッド本体を収納す
る。
されたハウジング30内ある各ボンドパッド延長部も含
む。これらは、初めはリードフレーム本体40と一体化
されているが(成形期間中)、ピン1〜4を互いにかつ
主パッド41から分離した切断された状態にしたのを示
す。典型的には、ピン1〜4は互いにおよび主ボンドパ
ッドに対して同一平面とする。
り、通常のリードフレーム半田仕上げを受けることがで
きる。ダイオード12の底部カソード面およびFET1
0の底部ドレイン面は導電性エポキシ・ダイ接合化合物
によりパッド41に接続され、従ってピン5〜8に接続
される。或いは、ダイオード12のカソード面およびF
ET10のドレイン面はパッド41にハンダ付けされ、
又は銀粒子(silver particle) を含有する導電性ガラス
を用いてパッドに接続する。
ド電極は金のボンディングワイヤ50および51により
それぞれピン1および2にワイヤボンディングし(ハウ
ジング成形前)、FETダイ10のソース電極およびゲ
ート電極も同様にハウジング30の成形前に金ワイヤ5
2および53によりピン3および4の内部ボンディング
延長部にそれぞれ接続する。或いは、アルミニウムのボ
ンディングワイヤも用いられる。これらピンの内部ボン
ディング延長部は、典型的には銀又は金のプレートとす
る。ボンディングワイヤは、他のプロセスを用いること
もできるが、一般的に当該技術分野において公知の超音
波併用熱圧着ボール・ボンディング(thermosonic ball
bonding)を用いてダイの表面および内部ボンディング延
長部にくっつける。
「ニットウ(NITTO) MP7400」のような成形合成物
(mold compound) であるとすることができる。ハウジン
グは通常の成形作業工程により形成する。一方、セラミ
ックハウジング、ハーメチックハウジング又は射出成形
の金属ハウジングのような他のタイプのハウジングを用
いることもできる。
きるが、表面実装パッケージでパッケージを共用するこ
とはかなりの基板スペースを占めることになることに注
意されたい。最終的なデバイスは通常の大量生産のハン
ダ付け技術を用いてプリント回路基板にハンダ付けする
ことができる。
形例を示し、本例ではFET10のソースは分離した孤
立のピン2および3にワイヤボンディング151および
152により接続し、FET10のゲートは分離した孤
立のピン4にワイヤボンディング153により接続し、
ショットキーダイオード12のアノードは分離した孤立
のピン1にワイヤボンディング150により接続する。
FET10のドレインおよびショットキーダイオード1
2のカソードは互いに接続すると共に上述した方法によ
り通常のリードフレーム部分のピン5〜8に接続する。
びにFET10およびショットキー12をさらに詳細に
示す。このリードフレーム140は上述したリードフレ
ーム40と同様なものであり、同様な主パッド本体14
1を含む。ショットキーダイオード12の底部カソード
面およびFET10の底部ドレイン面は上述した方法と
同様な方法でパッド141に接続し、ショットキーダイ
オード12の上側アノード電極およびFETダイ10の
ソース電極およびゲート電極も上述したようにピンの内
部ボンディング延長部に同様にボンディングする。同様
に、ハウジング130も上述した方法で形成する。
したが、当業者にとって多くの変形や変更並びに他の部
材の使用が可能である。従って、本発明は、本明細書の
開示内容だけに限定されず添付した請求の範囲により定
めることが望ましい。
コンバータ回路の回路図である。
ョットキーダイオードを用いるバックコンバータ回路の
回路図である。
MOSFETダイおよびショットキーダイの両方を収納
するために用いることができるSO−8型パッケージの
斜視図である。
た図1の回路のダイを有する図3のパッケージの擬略上
面図である。
ダイおよびショットキーダイオードダイを有する図3お
よび図4のパッケージのリードフレームの上面図であ
る。
れた図1の回路のダイを有する図3のパッケージの変形
例の擬略上面図である。
ダイおよびショットキーダイオードダイを有する図7の
パッケージのリードフレームの上面図である。
Claims (5)
- 【請求項1】 それぞれ電極を含む互いに対向する面を
有する第1の半導体ダイと、 それぞれ電極を含む互いに対向する面を有する第2の半
導体ダイと、 主パット部分を有していて、この主パット部分がその一
端から伸び出た第1の複数の平行ピンと、互いにかつそ
れぞれ前記主パット部分からも分離された第2の複数の
ピンを有する薄い導電性リードフレームと、 前記リードフレーム、前記第1および第2の半導体ダ
イ、およびボンディングワイヤを封入する成形ハウジン
グとを組合わせて具え、 前記第2の複数ピンは、前記主パット部分の第1の複数
のピンを含む側と反対側の縁部に沿って配置し、 前記第1および第2の半導体ダイの各々の一方の対向す
る面は前記主パット部分の上側にこの主パット部分と電
気的に接触するように配置すると共に横方向において互
いに離間し、 前記第1および第2の半導体ダイの反対側の対向する面
は前記第2の複数のピンの各ピンにワイヤボンディング
し、 前記第1および第2のピンが前記成形ハウジングの境界
を越えて延在して外部接続で利用可能となっていること
を特徴とする半導体デバイス。 - 【請求項2】 MOSFETダイおよびショットキーダ
イオードダイを含む表面実装パッケージであって、 ハウジングの一端を越えて延在する第1の複数のピンを
備えた主パット部分と前記一端の反対側のハウジングの
端部を越えて延在する第2の複数の同一平面上の孤立ピ
ンとを有するリードフレームを具え、 前記MOSFETダイは一の面にドレイン電極を反対側
の面にソース電極およびゲート電極を有し、 前記ショットキーダイは一の面にカソード電極を反対側
の面にアノード電極を有し、 前記ドレイン電極および前記カソード電極は横方向の変
位した位置で前記リードフレームの主パット部分と面対
面で接触して固定され、 前記アノード電極、前記ソース電極、および前記ゲート
電極は前記ハウジング内において前記第2の複数のピン
の各ピンにそれぞれワイヤボンディングされていること
を特徴とする表面実装パッケージ。 - 【請求項3】 複数のリードおよび1つのダイパッドを
有するリードフレームと、 前記ダイパッドに固定した底面を有すると共に、ソース
端子、ドレイン端子およびゲート端子を有するMOSF
ETを具える第1の半導体チップと、 前記ダイパッドに固定した底面を有すると共に、アノー
ド端子およびカソード端子を有するショットキーダイオ
ードを具える第2の半導体チップと、 前記第1および第2の半導体デバイス、前記ダイパッド
および複数のリードの各々の各部分を包囲するハウジン
グとを具え、 前記ソース端子、前記ドレイン端子、前記ゲート端子、
前記アノード端子および前記カソード端子を前記複数の
リードに電気的に結合したことを特徴とする半導体デバ
イス。 - 【請求項4】 複数のリードおよび1つのダイパッドを
有するリードフレームと、前記ダイパッドに固定した底
面を有すると共にソース端子、ドレイン端子およびゲー
ト端子を有するMOSFETを含む第1の半導体チップ
と、前記ダイパッドに固定した底面を有すると共にアノ
ード端子およびカソード端子を有するショットキーダイ
オードを含む第2の半導体チップと、前記第1および第
2の半導体チップ並びに前記複数のリードの各部分を収
容するハウジングとをを含み、前記ソース端子、前記ド
レイン端子、前記ゲート端子、前記アノード端子および
前記カソード端子の各々が前記複数のリードに電気的に
結合されている半導体デバイスと、 前記MOSFETの前記ソース端子に電気的に結合した
電源電圧端子と、 前記ショットキーダイオードの前記アノード端子に電気
的に結合した接地端子と、 前記MOSFETの前記ドレイン端子および前記ショッ
トキーダイオードの前記カソード端子に電気的に結合し
た負荷端子と、前記ショットキーダイオードの前記アノ
ード端子に電気的に結合した他の負荷端子とを有する一
対の負荷端子とを具えることを特徴とするコンバータ回
路。 - 【請求項5】 複数のリードおよび1つダイパッドを有
するリードフレームと、前記ダイパッドに固定した底面
を有すると共にソース端子、ドレイン端子およびゲート
端子を有する第1のMOSFETを含む第1の半導体チ
ップと、前記ダイパッドに固定した底面を有すると共に
アノード端子およびカソード端子を有するショットキー
ダイオードを含む第2の半導体チップと、前記第1およ
び第2の半導体チップ並びに前記ダイパット、前記複数
のリードの各部分を包囲するハウジングとを含み、前記
ソース端子、前記ドレイン端子、前記ゲート端子、前記
アノード端子および前記カソード端子の各々が前記複数
のリードに電気的に結合されている半導体デバイスと、 電源電圧端子と、 前記電源電圧端子に電気的に結合したドレイン端子、前
記第1のMOSFETの前記ドレイン端子および前記シ
ョットキーダイオードの前記カソード端子に電気的に結
合したソース端子とを有する第2のMOSFETと、 前記第1および第2のMOSFETのゲート端子に結合
したコントローラと、 前記第1のMOSFETの前記ソース端子および前記シ
ョットキーダイオードの前記アノード端子に電気的に結
合した接地端子とを具えることを特徴とする同期レギュ
レータ回路。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US2948396P | 1996-10-24 | 1996-10-24 | |
US08/816,829 | 1997-03-18 | ||
US08816829 US5814884C1 (en) | 1996-10-24 | 1997-03-18 | Commonly housed diverse semiconductor die |
US60/029,483 | 1997-03-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10150140A true JPH10150140A (ja) | 1998-06-02 |
JP2896126B2 JP2896126B2 (ja) | 1999-05-31 |
Family
ID=26704993
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9291168A Expired - Lifetime JP2896126B2 (ja) | 1996-10-24 | 1997-10-23 | 半導体デバイスおよび表面実装パッケージ |
Country Status (2)
Country | Link |
---|---|
US (4) | US5814884C1 (ja) |
JP (1) | JP2896126B2 (ja) |
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Also Published As
Publication number | Publication date |
---|---|
US5814884C1 (en) | 2002-01-29 |
US20020008319A1 (en) | 2002-01-24 |
US6404050B2 (en) | 2002-06-11 |
US6133632A (en) | 2000-10-17 |
US6297552B1 (en) | 2001-10-02 |
JP2896126B2 (ja) | 1999-05-31 |
US5814884A (en) | 1998-09-29 |
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