JPH10107204A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH10107204A JPH10107204A JP8256110A JP25611096A JPH10107204A JP H10107204 A JPH10107204 A JP H10107204A JP 8256110 A JP8256110 A JP 8256110A JP 25611096 A JP25611096 A JP 25611096A JP H10107204 A JPH10107204 A JP H10107204A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- circuit board
- semiconductor
- spacer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数個の半導体チ
ップが積層された半導体装置に関するものであり、特に
上記のように形成された半導体装置を回路基板に固着す
る場合の半導体装置及びその製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor chips are stacked, and more particularly to a semiconductor device in which the semiconductor device formed as described above is fixed to a circuit board and its manufacture. It is about the method.
【０００２】[0002]
【従来の技術】近年の電子機器はマルチメディア時代を
むかえ、より小型、軽量、薄型化が求められている。こ
のため、電子機器の半導体チップの実装形態はパッケー
ジング実装からベアチップ実装に移行しつつあり、具体
的には、実装密度の高密度化を達成すべく、半導体チッ
プのパッドと回路基板の電極との接続は、ワイヤボンデ
ィング方式からフリップチップ方式が用いられる傾向に
ある。2. Description of the Related Art In recent years, electronic devices have been required to be smaller, lighter, and thinner in the multimedia age. For this reason, the mounting form of semiconductor chips for electronic devices is shifting from packaging mounting to bare chip mounting.Specifically, in order to achieve a higher mounting density, the pads of the semiconductor chip and the electrodes of the circuit board have to be mounted. For the connection of, there is a tendency that the flip chip method is used instead of the wire bonding method.
【０００３】また、一方では電子機器および半導体チッ
プの低コスト化と電子機器の高機能化をはかるため、半
導体チップの内部回路を機能分割して機能の異なる複数
個の半導体チップとし、この複数個の異種の半導体チッ
プを積層して積層体を形成して実装する方法が用いられ
ている。On the other hand, in order to reduce the cost of electronic equipment and semiconductor chips and to increase the functionality of electronic equipment, the internal circuit of the semiconductor chip is divided into a plurality of semiconductor chips having different functions. A method of stacking different types of semiconductor chips to form a stacked body and mounting the same is used.
【０００４】図５は上記した異種の半導体チップを積層
して実装した後、それらを回路基板へ実装した際の半導
体装置の断面図を示したものである。図５において、２
０は回路基板、２１は第１の半導体チップ、２２は第１
の半導体チップ２１上に積層された第２の半導体チップ
（フリップチップ接続されている）、２３は第１の半導
体チップ２１及び第２の半導体チップ２２に形成された
パッド、２４は第１の半導体チップ２１のパッドと第２
の半導体チップのパッド間を接続する際に介されるバン
プである。FIG. 5 is a cross-sectional view of a semiconductor device when the above-mentioned different types of semiconductor chips are stacked and mounted, and then mounted on a circuit board. In FIG. 5, 2
0 is a circuit board, 21 is a first semiconductor chip, 22 is a first semiconductor chip.
A second semiconductor chip (flip-chip connected) laminated on the first semiconductor chip 21, a pad 23 formed on the first semiconductor chip 21 and the second semiconductor chip 22, and a first semiconductor chip 24. The pad of the chip 21 and the second
Bumps used to connect pads of the semiconductor chip.
【０００５】図５（ａ）において回路基板２０の材料に
は低コスト化の目的として一般的にガラス／エポキシが
用いられる。第１および第２の半導体チップ２１、２２
の素子形成面には第１および第２の半導体チップ２１、
２２の素子形成面を対向させた際、それぞれ対向する微
小なパッド２３が設けられており、第１および第２の半
導体チップ２１、２２の電気的な接続は、パッド２３に
形成したはんだあるいはＡｕ等の材料からなる微小なバ
ンプ２４を介して行われ、バンプ２４により接続された
第１および第２の半導体チップ２１、２２の間には素子
形成表面を外部環境からの保護のため樹脂２５が充填さ
れている。また、第１の半導体チップ２２の周囲には、
回路基板２０の電極２６と電気的に接続するボンディン
グパッド２７が設けられており、第１および第２の半導
体チップ２１、２２を積層した積層体をエポキシ樹脂等
からなる導電性接着樹脂２８により回路基板２０へ直接
ダイボンドし、回路基板の電極とボンディングワイヤ２
９により電気的な接続が行われている。In FIG. 5A, glass / epoxy is generally used for the material of the circuit board 20 for the purpose of cost reduction. First and second semiconductor chips 21 and 22
The first and second semiconductor chips 21,
When the element forming surfaces of the semiconductor chips 22 are opposed to each other, opposed minute pads 23 are provided. The electrical connection between the first and second semiconductor chips 21 and 22 is made by solder or Au formed on the pads 23. A resin 25 is provided between the first and second semiconductor chips 21 and 22 connected by the bumps 24 to protect the element formation surface from the external environment. Is filled. In addition, around the first semiconductor chip 22,
A bonding pad 27 that is electrically connected to the electrode 26 of the circuit board 20 is provided, and a laminate of the first and second semiconductor chips 21 and 22 is formed by a conductive adhesive resin 28 made of epoxy resin or the like. Die-bonding directly to the substrate 20, the electrode of the circuit board and the bonding wire 2
9, an electrical connection is made.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記し
た従来の半導体装置においては下記に示すような課題を
有していた。However, the above-mentioned conventional semiconductor device has the following problems.
【０００７】まず第１に、電子機器の小型、軽量、薄型
と低コスト化をはかるため、電子機器の回路基板２０に
は上記したようにガラス／エポキシからなるプリント基
板が用いられているわけであるが、図５（ｂ）に示すよ
うに回路基板２０に横方向からの外力Ｇ、Ｇ’が加わっ
た際（例えば積層体において、第１の半導体チップの裏
面にコネクタが形成されている場合において、そのコネ
クタを別の基板に接続する際等）、回路基板２０に曲げ
変形σが生じてしまう。この時、回路基板２０に第１の
半導体チップ２１をダイボンドする導電性接着樹脂２８
（例えばエポキシ樹脂）の弾性率が高いため、回路基板
２０の曲げ変形がそのまま第１の半導体チップ２１に加
わり、回路基板２０と同じように第１の半導体チップ２
１に曲げ変形が生じてしまう。上記のように第１の半導
体チップ２１に曲げ変形が生じると、その曲げ応力が微
小なバンプ２４に加わり、結果としてバンプ２４で接続
された第１および第２の半導体チップ２１、２２のパッ
ド２３の接続不良が発生し、電子機器の信頼性が著しく
低下する。First, in order to reduce the size, weight, thickness and cost of electronic equipment, a printed circuit board made of glass / epoxy is used for the circuit board 20 of the electronic equipment as described above. However, as shown in FIG. 5B, when external forces G and G ′ are applied to the circuit board 20 from the lateral direction (for example, when a connector is formed on the back surface of the first semiconductor chip in the laminate) In such a case, when the connector is connected to another board, for example), bending deformation σ occurs in the circuit board 20. At this time, the conductive adhesive resin 28 for die-bonding the first semiconductor chip 21 to the circuit board 20 is used.
Since the elastic modulus of the epoxy resin (eg, epoxy resin) is high, the bending deformation of the circuit board 20 is applied to the first semiconductor chip 21 as it is, and the first semiconductor chip 2
Bending deformation occurs in 1. When bending deformation occurs in the first semiconductor chip 21 as described above, the bending stress is applied to the minute bumps 24, and as a result, the pads 23 of the first and second semiconductor chips 21 and 22 connected by the bumps 24. Connection failure occurs, and the reliability of the electronic device is significantly reduced.
【０００８】第２に、外力Ｇ、Ｇ’による回路基板２０
の曲げ変形σが第１の半導体チップ２１に加わるため、
第１および第２の半導体チップ２１、２２の電気特性が
変動し、電子機器の性能が低下する。具体的には、半導
体チップに伸びが生じるため、半導体チップに形成され
た抵抗の値が変化し、トランジスタ等の場合にはしきい
値電圧が変化してしまう。[0008] Second, the circuit board 20 by external force G, G '
Is applied to the first semiconductor chip 21,
The electrical characteristics of the first and second semiconductor chips 21 and 22 fluctuate, and the performance of the electronic device decreases. Specifically, since the semiconductor chip expands, the value of the resistor formed on the semiconductor chip changes, and in the case of a transistor or the like, the threshold voltage changes.
【０００９】第３に、回路基板の外力による曲げ変形に
対処するための手段として基板剛性の高いセラミック基
板を適用する方法が考えられるわけであるが、セラミッ
ク基板はガラス／エポキシ基板と比較して高価であり、
工程数も増大してしまう。Third, as a means for coping with bending deformation of the circuit board due to external force, a method of applying a ceramic board having a high board rigidity can be considered. The ceramic board is compared with a glass / epoxy board. Expensive and
The number of steps also increases.
【００１０】本願発明は上記問題点に鑑み、複数個の半
導体チップがフリップチップ接続された半導体装置を曲
げ変形を生じやすいガラス／エポキシ樹脂などの材料で
形成された回路基板に対してベアチップ実装する構造に
おいて、特に曲げ変形が回路基板に対して与えられるこ
とに起因して半導体チップに対して曲げ変形が加わるこ
とによるパッド部の接続不良および、半導体チップの電
気特性変動を発生させることなく、電子機器に信頼性、
機能低下が生じない回路基板への半導体チップのダイボ
ンドを低コストに実現することの可能な半導体装置及び
その製造方法を提供することを目的とする。SUMMARY OF THE INVENTION In view of the above problems, the present invention mounts a semiconductor device in which a plurality of semiconductor chips are flip-chip connected to a circuit board made of a material such as glass / epoxy resin or the like which is easily bent and deformed. In the structure, in particular, it is possible to prevent the connection failure of the pad portion due to the bending deformation applied to the semiconductor chip due to the bending deformation being applied to the circuit board, and to prevent the electrical characteristics of the semiconductor chip from fluctuating. Equipment reliability,
It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can realize die bonding of a semiconductor chip to a circuit board which does not cause functional deterioration at low cost.
【００１１】[0011]
【課題を解決するための手段】上記の目的を達成するた
めに本発明の半導体装置は、回路基板と半導体チップと
の接着固定を樹脂を用いて行い、樹脂の接着面積と低弾
性樹脂層の厚みを弾性体のスペーサで制御し、半導体チ
ップを回路基板に搭載する。これにより樹脂および弾性
ゴムシートからなるスペーサで回路基板の外力による曲
げ変形によって生じる曲げ応力を吸収し、半導体チップ
への曲げ応力を皆無となり、バンプによるフリップチッ
プ接続で積層化実装された半導体チップ同士のパッド部
の接続不良を発生させることがない。In order to achieve the above object, a semiconductor device according to the present invention is characterized in that a circuit board and a semiconductor chip are bonded and fixed by using a resin, and the bonding area of the resin and the low elastic resin layer are reduced. The thickness is controlled by an elastic spacer, and the semiconductor chip is mounted on a circuit board. This allows the spacer made of resin and elastic rubber sheet to absorb the bending stress generated by the bending deformation due to the external force of the circuit board, eliminating the bending stress on the semiconductor chip, and connecting the semiconductor chips stacked and mounted by flip chip connection using bumps. The connection failure of the pad portion does not occur.
【００１２】[0012]
【発明の実施の形態】以下に、本発明の実施の形態にお
ける半導体装置及びその製造方法について図面を参照し
ながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings.
【００１３】図１は本発明の半導体装置の構成を分解し
て示した斜視図である。図１において１はガラス／エポ
キシ樹脂からなる回路基板、２は第１の半導体チップ、
３は第１の半導体チップ上に積層して形成された第２の
半導体チップ、４は第１の半導体チップ２に形成された
ボンディングパッド、５はシリコーンゴム等の低弾性導
電性樹脂、６は弾性ゴムシートからなる弾性体のスペー
サ、７は回路基板の電極を示している。FIG. 1 is an exploded perspective view showing the structure of a semiconductor device according to the present invention. In FIG. 1, 1 is a circuit board made of glass / epoxy resin, 2 is a first semiconductor chip,
Reference numeral 3 denotes a second semiconductor chip formed by stacking on the first semiconductor chip, 4 denotes a bonding pad formed on the first semiconductor chip 2, 5 denotes a low-elasticity conductive resin such as silicone rubber, and 6 denotes Elastic spacers 7 made of an elastic rubber sheet indicate electrodes on the circuit board.
【００１４】図１について更に詳細に説明すると、第１
の半導体チップの一主面に第２の半導体チップがフリッ
プチップ実装された積層体は低弾性導電性樹脂を介して
回路基板７に接着される（すなわち、第１の半導体チッ
プの裏面を低弾性導電性樹脂により回路基板に固着す
る）。その際、低弾性導電性樹脂の厚さおよび接着面積
を制御するため所定の開口部を有したスペーサ６の開口
部内に低弾性導電性樹脂を塗布し、第２の半導体チップ
がフリップチップ実装された第１の半導体チップ側から
積層体を接着する。これにより、スペーサ自身の厚みｔ
で低弾性導電性樹脂層の厚みを、スペーサの開口部の大
きさで接着面積が高精度に制御できるものである。従っ
て、積層体における第１の半導体チップの裏面から低弾
性導電性樹脂がはみ出すことがなく、この低弾性導電性
樹脂が電極７に付着することも完全に防止することがで
きる。FIG. 1 will be described in more detail.
The laminate in which the second semiconductor chip is flip-chip mounted on one main surface of the semiconductor chip is bonded to the circuit board 7 via a low-elasticity conductive resin (that is, the back surface of the first semiconductor chip has low elasticity). It is fixed to the circuit board by the conductive resin). At this time, in order to control the thickness and adhesion area of the low elasticity conductive resin, the low elasticity conductive resin is applied to the inside of the opening of the spacer 6 having a predetermined opening, and the second semiconductor chip is flip-chip mounted. The laminated body is bonded from the first semiconductor chip side. Thereby, the thickness t of the spacer itself is obtained.
Thus, the bonding area can be controlled with high precision by controlling the thickness of the low elasticity conductive resin layer by the size of the opening of the spacer. Therefore, the low-elasticity conductive resin does not protrude from the back surface of the first semiconductor chip in the laminate, and it is possible to completely prevent the low-elasticity conductive resin from adhering to the electrode 7.
【００１５】次に以下では、上記した図１に示す本発明
の実施の形態における半導体装置の製造方法について図
２を参照しながら説明する。Next, a method of manufacturing the semiconductor device according to the embodiment of the present invention shown in FIG. 1 will be described with reference to FIG.
【００１６】まず図２（ａ）に示すように、電極７が形
成された回路基板１の半導体チップ搭載領域にシリコン
ゴム等などの弾性率が低い材料からなるシート状のスペ
ーサ６を配置して図２（ｂ）に示す構成を得る。この
時、シート状のスペーサ６の厚みは５０〜１００μｍ
で、後に第１の半導体チップを回路基板１と接着するた
めの低弾性導電性樹脂層の厚みはシート状のスペーサの
厚みを変化させることにより任意の厚みに制御できるわ
けである。また、第１の半導体チップと回路基板１の接
着面積についても、シート状のスペーサ６に設けられた
開口部の大きさを変えることにより設定することが可能
である。First, as shown in FIG. 2A, a sheet-like spacer 6 made of a material having a low elastic modulus, such as silicon rubber, is disposed in a semiconductor chip mounting area of the circuit board 1 on which the electrodes 7 are formed. The configuration shown in FIG. 2B is obtained. At this time, the thickness of the sheet-like spacer 6 is 50 to 100 μm.
Thus, the thickness of the low-elasticity conductive resin layer for later bonding the first semiconductor chip to the circuit board 1 can be controlled to an arbitrary thickness by changing the thickness of the sheet-shaped spacer. Further, the bonding area between the first semiconductor chip and the circuit board 1 can also be set by changing the size of the opening provided in the sheet-like spacer 6.
【００１７】次に図２（ｃ）に示すように、シート状の
スペーサ６に設けられた開口部内に低弾性導電性樹脂５
を適量塗布する。その後、図２（ｄ）に示すように第１
の半導体チップ２の主面に第２の半導体チップ３がフリ
ップチップ実装された積層体を回路基板１に圧接し、シ
ート状のスペーサ６に設けられた開口部内の低弾性導電
性樹脂５を押し広げ、低弾性導電性樹脂層５の厚みをシ
ート状のスペーサの厚みと同じになるように第２の半導
体チップの主面に第１の半導体チップを圧着、接着す
る。その後、図２（ｅ）に示すように、低弾性導電性樹
脂５を硬化させ、さらに第１の半導体チップの電極４と
回路基板１上の電極７とをボンディングワイヤ２９によ
り電気的に接続する。Next, as shown in FIG. 2 (c), a low elastic conductive resin 5 is formed in an opening provided in the sheet-like spacer 6.
Is applied in an appropriate amount. Thereafter, as shown in FIG.
A laminate in which the second semiconductor chip 3 is flip-chip mounted on the main surface of the semiconductor chip 2 is pressed against the circuit board 1 to push the low elastic conductive resin 5 in the opening provided in the sheet-like spacer 6. The first semiconductor chip is crimped and bonded to the main surface of the second semiconductor chip so that the thickness of the low elastic conductive resin layer 5 is equal to the thickness of the sheet-shaped spacer. Thereafter, as shown in FIG. 2E, the low-elasticity conductive resin 5 is cured, and the electrodes 4 of the first semiconductor chip and the electrodes 7 on the circuit board 1 are electrically connected by bonding wires 29. .
【００１８】上記ようにして形成された本発明の実施の
形態における半導体装置に外部から力が加わった時の挙
動について図３を参照しながら説明する。The behavior when a force is applied from the outside to the semiconductor device according to the embodiment of the present invention formed as described above will be described with reference to FIG.
【００１９】回路基板１に横方向からの外力Ｇ、Ｇ’が
加わって、回路基板１に曲げ変形σが生じても低弾性導
電性樹脂層５およびシート状のスペーサ６が回路基板１
の曲げ変形σを吸収変形して第１の半導体チップ２に回
路基板１の曲げ変形σを伝えることがない。なお、スペ
ーサ６の弾性率が回路基板の弾性率より低い場合、確実
に回路基板に生じた変形をスペーサ６により吸収するこ
とができる。Even when external forces G and G 'are applied to the circuit board 1 from the lateral direction and the circuit board 1 undergoes a bending deformation σ, the low elastic conductive resin layer 5 and the sheet-like spacers 6 form the circuit board 1.
The bending deformation σ of the circuit board 1 is not transmitted to the first semiconductor chip 2 by absorbing the bending deformation σ. When the elastic modulus of the spacer 6 is lower than the elastic modulus of the circuit board, the deformation generated on the circuit board can be reliably absorbed by the spacer 6.
【００２０】また、スペーサ６と回路基板とが直接固着
されていない場合、積層体における第１の半導体チップ
２はスペーサ６に形成された開口部の領域内のみで完全
に固定されており、その他の部分は樹脂によって固定さ
れていないため、回路基板に変形が生じたところで、ス
ペーサ６と回路基板１との間に空間が生じ、生じた変形
を第１の半導体チップ２が直接全てを受けることはな
い。これにより、バンプによるフリップチップ接続で積
層化実装された半導体チップ同士のパッド部の接続不良
を発生させることがない。When the spacer 6 and the circuit board are not directly fixed, the first semiconductor chip 2 in the laminated body is completely fixed only in the region of the opening formed in the spacer 6. Is not fixed by the resin, a space is generated between the spacer 6 and the circuit board 1 when the circuit board is deformed, and the first semiconductor chip 2 receives all the generated deformation directly. There is no. As a result, there is no occurrence of connection failure of the pad portion between the semiconductor chips stacked and mounted by flip-chip connection using bumps.
【００２１】また、上記の図１に示したような構造のシ
ート状のスペーサを用いる代わりに、開口部を図４に示
すように複数の開口部を設けたものを用いることも可能
である。Instead of using the sheet-like spacer having the structure as shown in FIG. 1, it is also possible to use an opening having a plurality of openings as shown in FIG.
【００２２】[0022]
【発明の効果】以上説明のとおり本願発明の効果は回路
基板と半導体チップとの接着固定を弾性ゴムシートから
なるスペーサおよび樹脂を介して行うことにより回路基
板の外力による曲げ変形によって生じる曲げ応力を吸収
し、剛性の高いセラミック基板を用いることなく、半導
体チップへの曲げ応力の伝達を効果的に止めることがで
きる。As described above, the effect of the present invention is that the bending stress generated by the bending deformation due to the external force of the circuit board is achieved by bonding and fixing the circuit board and the semiconductor chip through the spacer and the resin made of the elastic rubber sheet. The transmission of bending stress to the semiconductor chip can be effectively stopped without using an absorbing and rigid ceramic substrate.
【００２３】これにより、半導体チップへの曲げ応力に
よるフリップチップ接続で積層化実装された半導体チッ
プ同士のバンプ接続部の接続不良や曲げ応力による半導
体チップの電気特性の劣化を低コストでかつ簡便な方法
で防止する事ができる。また、回路基板のコストの増大
とセラミック基板の作製納期の長期化による電子機器の
コストおよび開発期間が著しく長期化することがなく極
めて効果的である。[0023] This makes it possible to reduce the cost of the semiconductor device and to reduce the electrical characteristics of the semiconductor chip due to the poor connection of the bump connection portion between the semiconductor chips stacked and mounted by the flip chip connection due to the bending stress to the semiconductor chip and the bending stress. It can be prevented by the method. In addition, the cost and development period of the electronic device due to the increase in the cost of the circuit board and the prolonged production and delivery time of the ceramic substrate are extremely effective without significantly prolonging.
【図１】本発明の実施の形態における半導体装置の断面
図FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の実施の形態における半導体装置の製造
工程断面図FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;
【図３】本発明の実施の形態における半導体装置の断面
図FIG. 3 is a cross-sectional view of the semiconductor device according to the embodiment of the present invention;
【図４】本発明の実施の形態における半導体装置に用い
るシート状のスペーサの斜視図FIG. 4 is a perspective view of a sheet-like spacer used in the semiconductor device according to the embodiment of the present invention;
【図５】従来の半導体装置の断面図FIG. 5 is a sectional view of a conventional semiconductor device.
１ 回路基板 ２ 第１の半導体チップ ３ 第２の半導体チップ ４ ボンディングパッド ５ 低弾性導電性樹脂 ６ スペーサ ７ 電極 ８ 樹脂 ９ バンプ １０ パッド １１ ボンディングワイヤ １２ 開口部 DESCRIPTION OF SYMBOLS 1 Circuit board 2 1st semiconductor chip 3 2nd semiconductor chip 4 Bonding pad 5 Low elastic conductive resin 6 Spacer 7 Electrode 8 Resin 9 Bump 10 Pad 11 Bonding wire 12 Opening
Claims (3)
チップ上に積層されるとともに前記第１の半導体チップ
と電気的に接続された第２の半導体チップと、前記第１
の半導体チップと樹脂を介して固着された回路基板とを
有する半導体装置であって、前記第１の半導体チップと
前記回路基板との間に開口部を有する弾性体のスペーサ
を配置したことを特徴とする半導体装置。A first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip;
A semiconductor device having a semiconductor chip and a circuit board fixed via a resin, wherein an elastic spacer having an opening is disposed between the first semiconductor chip and the circuit board. Semiconductor device.
低いことを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the elastic modulus of the spacer is lower than the elastic modulus of the circuit board.
チップ上に積層されるとともに前記第１の半導体チップ
と電気的に接続された第２の半導体チップとを有する積
層体を樹脂を介して回路基板に固着する半導体装置の製
造方法であって、前記回路基板と前記積層体との間に開
口部を有する弾性体のスペーサを配置する工程と、前記
低弾性シートの開口部に樹脂を塗布する工程と、前記ス
ペーサ上部から前記積層体を加圧して前記積層体を前記
回路基板に固着する工程とを有する半導体装置の製造方
法。3. A laminated body having a first semiconductor chip and a second semiconductor chip laminated on the first semiconductor chip and electrically connected to the first semiconductor chip via a resin. A method of manufacturing a semiconductor device that is fixed to a circuit board by attaching a spacer of an elastic body having an opening between the circuit board and the laminate, and applying a resin to the opening of the low elasticity sheet. A method of manufacturing a semiconductor device, comprising: a step of applying the laminate; and a step of pressing the laminate from above the spacer to fix the laminate to the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8256110A JPH10107204A (en) | 1996-09-27 | 1996-09-27 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8256110A JPH10107204A (en) | 1996-09-27 | 1996-09-27 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10107204A true JPH10107204A (en) | 1998-04-24 |
Family
ID=17288042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8256110A Pending JPH10107204A (en) | 1996-09-27 | 1996-09-27 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10107204A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1296374A1 (en) * | 2001-09-14 | 2003-03-26 | STMicroelectronics S.r.l. | Process for bonding and electrically connecting microsystems integrated in several distinct substrates |
| JP2012216836A (en) * | 2011-03-31 | 2012-11-08 | Mitsubishi Chemicals Corp | Three-dimensional integrated circuit laminate |
| US9508648B2 (en) | 2011-03-31 | 2016-11-29 | Mitsubishi Chemical Corporation | Three-dimensional integrated circuit laminate, and interlayer filler for three-dimensional integrated circuit laminate |
| CN110006580A (en) * | 2014-06-12 | 2019-07-12 | 意法半导体(格勒诺布尔2)公司 | The stacking and electronic device of IC chip |
-
1996
- 1996-09-27 JP JP8256110A patent/JPH10107204A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1296374A1 (en) * | 2001-09-14 | 2003-03-26 | STMicroelectronics S.r.l. | Process for bonding and electrically connecting microsystems integrated in several distinct substrates |
| US7595223B2 (en) | 2001-09-14 | 2009-09-29 | Stmicroelectronics S.R.L. | Process for bonding and electrically connecting microsystems integrated in several distinct substrates |
| JP2012216836A (en) * | 2011-03-31 | 2012-11-08 | Mitsubishi Chemicals Corp | Three-dimensional integrated circuit laminate |
| US9508648B2 (en) | 2011-03-31 | 2016-11-29 | Mitsubishi Chemical Corporation | Three-dimensional integrated circuit laminate, and interlayer filler for three-dimensional integrated circuit laminate |
| US9847298B2 (en) | 2011-03-31 | 2017-12-19 | Mitsubishi Chemical Corporation | Three-dimensional integrated circuit laminate, and interlayer filler for three-dimensional integrated circuit laminate |
| CN110006580A (en) * | 2014-06-12 | 2019-07-12 | 意法半导体(格勒诺布尔2)公司 | The stacking and electronic device of IC chip |
| CN110006580B (en) * | 2014-06-12 | 2021-03-09 | 意法半导体(格勒诺布尔2)公司 | Stack of integrated circuit chips and electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6208525B1 (en) | Process for mounting electronic device and semiconductor device | |
| US7485490B2 (en) | Method of forming a stacked semiconductor package | |
| US6744122B1 (en) | Semiconductor device, method of manufacture thereof, circuit board, and electronic device | |
| US20030173679A1 (en) | Stacked dice standoffs | |
| JP2000269371A (en) | Semiconductor device and semiconductor mounting structure member | |
| JP2001156246A (en) | Mounting structure and mounting method for integrated circuit chip | |
| JP2001298115A (en) | Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment | |
| EP1579502A2 (en) | Electronic device and method of manufacturing same | |
| JP4175138B2 (en) | Semiconductor device | |
| JP2008192984A (en) | Semiconductor device and method of manufacturing the same | |
| JPH10107204A (en) | Semiconductor device and its manufacture | |
| JP3569585B2 (en) | Semiconductor device | |
| JP3549316B2 (en) | Wiring board | |
| KR20010017143A (en) | Stacked flip chip package using carrier tape | |
| JP2002289735A (en) | Semiconductor device | |
| JPH06140542A (en) | Semiconductor device | |
| JP2002289741A (en) | Semiconductor device | |
| JP2001053106A (en) | Flip-chip connection structure and manufacture for electronic component | |
| JP3841135B2 (en) | Semiconductor device, circuit board and electronic equipment | |
| JP2004200665A (en) | Semiconductor device and manufacturing method of the same | |
| JP2004200665A6 (en) | Semiconductor device and method of manufacturing the same | |
| JPH11150155A (en) | Manufacture of semiconductor device and circuit board holding jig there for | |
| JPH06275675A (en) | Tab package and its connection | |
| JP3248854B2 (en) | Structure of a semiconductor device having a plurality of IC chips | |
| JPH09275161A (en) | Semiconductor device |