JP2001298115A - Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment - Google Patents
Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipmentInfo
- Publication number
- JP2001298115A JP2001298115A JP2000112169A JP2000112169A JP2001298115A JP 2001298115 A JP2001298115 A JP 2001298115A JP 2000112169 A JP2000112169 A JP 2000112169A JP 2000112169 A JP2000112169 A JP 2000112169A JP 2001298115 A JP2001298115 A JP 2001298115A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- semiconductor device
- resin
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法、回路基板並びに電子機器に関する。The present invention relates to a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device.
【０００２】[0002]
【発明の背景】半導体装置の小型化・薄型化に伴い、集
積回路の形成された能動面とは反対側の面を研削するこ
とにより、薄い半導体チップを形成する方法が知られて
いる。BACKGROUND OF THE INVENTION Along with the miniaturization and thinning of a semiconductor device, a method of forming a thin semiconductor chip by grinding a surface opposite to an active surface on which an integrated circuit is formed is known.
【０００３】しかし、研削後の薄い半導体チップは割れ
やすいので、基板に搭載するまでの製造工程において、
その取り扱いが難しい場合があった。[0003] However, since the thin semiconductor chip after grinding is easily broken, in the manufacturing process up to mounting on a substrate,
The handling was sometimes difficult.
【０００４】本発明はこの問題点を解決するものであ
り、その目的は、製造工程での取り扱いに優れる半導体
装置及びその製造方法、回路基板並びに電子機器を提供
することにある。An object of the present invention is to solve this problem, and an object of the present invention is to provide a semiconductor device excellent in handling in a manufacturing process, a manufacturing method thereof, a circuit board, and an electronic device.
【０００５】[0005]
【課題を解決するための手段】（１）本発明に係る半導
体装置の製造方法は、配線パターンを少なくとも一方の
面に有する基板に、半導体チップにおける電極形成面を
対向させて搭載し、前記電極と前記配線パターンとを電
気的に接続して固定する工程と、前記工程後に、前記半
導体チップにおける前記基板とは反対側の面を研削する
工程と、を含む。(1) In a method of manufacturing a semiconductor device according to the present invention, an electrode forming surface of a semiconductor chip is mounted on a substrate having a wiring pattern on at least one surface thereof, and the electrodes are mounted on the substrate. And a step of electrically connecting and fixing the wiring pattern, and a step of grinding the surface of the semiconductor chip opposite to the substrate after the step.
【０００６】本発明によれば、半導体チップを基板に搭
載した後に、基板上において半導体チップを研削して薄
くする。すなわち、薄くて割れやすい半導体チップその
ものを取り扱うことがなく、半導体装置を製造すること
ができる。According to the present invention, after the semiconductor chip is mounted on the substrate, the semiconductor chip is ground and thinned on the substrate. That is, a semiconductor device can be manufactured without handling a thin and fragile semiconductor chip itself.
【０００７】（２）この半導体装置の製造方法におい
て、前記半導体チップを搭載する工程で、接着剤を介し
て前記半導体チップを前記基板に固定してもよい。(2) In this method of manufacturing a semiconductor device, in the step of mounting the semiconductor chip, the semiconductor chip may be fixed to the substrate via an adhesive.
【０００８】これによって、半導体チップが基板に固着
されるので確実に半導体チップを研削することができ
る。なお、接着剤は半導体チップに加わる応力を緩和す
るためのものであってもよい。Accordingly, the semiconductor chip can be reliably ground because the semiconductor chip is fixed to the substrate. Note that the adhesive may be used to alleviate the stress applied to the semiconductor chip.
【０００９】（３）この半導体装置の製造方法におい
て、前記半導体チップを搭載する工程で、前記接着剤は
導電粒子が分散されてなる異方性導電材料であり、前記
導電粒子を介して、前記電極と前記配線パターンとを電
気的に接続してもよい。(3) In the method of manufacturing a semiconductor device, in the step of mounting the semiconductor chip, the adhesive is an anisotropic conductive material in which conductive particles are dispersed, and the adhesive is formed through the conductive particles. The electrode and the wiring pattern may be electrically connected.
【００１０】これによって、半導体チップの電極と基板
の配線パターンとの電気的接続を図るとともに、半導体
チップを基板に固着させることができるので、工程を簡
単にすることができる。[0010] This makes it possible to electrically connect the electrodes of the semiconductor chip to the wiring pattern of the substrate and to fix the semiconductor chip to the substrate, thereby simplifying the process.
【００１１】（４）この半導体装置の製造方法におい
て、前記研削する工程前に、前記基板における一方の面
で前記半導体チップを樹脂封止する工程をさらに含み、
前記研削する工程は、前記樹脂を研削して、前記半導体
チップにおける前記電極形成面とは反対側の面を露出さ
せ、前記露出面及びその周囲の前記樹脂の面を研削する
工程であってもよい。(4) The method of manufacturing a semiconductor device further includes a step of resin-sealing the semiconductor chip on one surface of the substrate before the step of grinding,
The step of grinding may be a step of grinding the resin to expose a surface of the semiconductor chip opposite to the electrode forming surface, and grinding the exposed surface and the surface of the resin around the exposed surface. Good.
【００１２】これによれば、半導体チップを樹脂封止
し、樹脂とともに半導体チップを研削する。半導体チッ
プを研削するには、封止樹脂の外側の面を研削して半導
体チップを露出させ、半導体チップの露出面とその周囲
の樹脂の面とを研削してもよい。これによって、より確
実に半導体チップを研削することができる。According to this, the semiconductor chip is sealed with a resin, and the semiconductor chip is ground together with the resin. In order to grind the semiconductor chip, the outer surface of the sealing resin may be ground to expose the semiconductor chip, and the exposed surface of the semiconductor chip and the surface of the resin surrounding the semiconductor chip may be ground. Thereby, the semiconductor chip can be more reliably ground.
【００１３】（５）この半導体装置の製造方法におい
て、前記樹脂封止する工程前に、複数のバンプを、前記
基板における前記半導体チップの搭載側の前記半導体チ
ップの搭載領域外に形成する工程をさらに含み、前記樹
脂を、前記バンプを覆うように設け、前記研削する工程
は、前記露出面及びその周囲の前記樹脂の面を研削する
とともに、前記バンプの一部を露出させる工程であって
もよい。(5) In this method of manufacturing a semiconductor device, a step of forming a plurality of bumps outside the mounting area of the semiconductor chip on the mounting side of the semiconductor chip on the substrate before the resin sealing step. The method further includes the step of providing the resin so as to cover the bump, and the step of grinding is a step of grinding the exposed surface and the surface of the resin around the exposed surface and exposing a part of the bump. Good.
【００１４】これによって、封止樹脂の側に外部端子を
形成することができる。Thus, external terminals can be formed on the side of the sealing resin.
【００１５】（６）本発明に係る半導体装置は、上記半
導体装置の製造方法によって製造されてなる。(6) A semiconductor device according to the present invention is manufactured by the above-described method for manufacturing a semiconductor device.
【００１６】（７）本発明に係る半導体装置は、少なく
とも一方の面に配線パターンが形成された基板と、複数
の電極を有し、前記基板にフェースダウンボンディング
された半導体チップと、前記基板における前記半導体チ
ップの搭載領域外に設けられ、前記基板における前記半
導体チップの搭載側に形成された複数のバンプと、を含
む。(7) A semiconductor device according to the present invention includes a substrate having a wiring pattern formed on at least one surface thereof, a semiconductor chip having a plurality of electrodes, face-down bonded to the substrate, A plurality of bumps provided outside the mounting area of the semiconductor chip and formed on the mounting side of the semiconductor chip on the substrate.
【００１７】本発明によれば、基板における半導体チッ
プの搭載側にバンプが形成されている。これによって、
半導体装置における基板の側とは反対側に外部端子を設
けることが可能となり、設計自由度の高い半導体装置を
提供することができる。According to the present invention, the bump is formed on the side of the substrate on which the semiconductor chip is mounted. by this,
External terminals can be provided on the side opposite to the substrate side of the semiconductor device, and a semiconductor device with high design flexibility can be provided.
【００１８】（８）この半導体装置において、前記半導
体チップにおける前記基板とは反対側の面を除いて前記
半導体チップに密着して設けられ、かつ、前記半導体チ
ップにおける前記基板とは反対側の面と面一となって設
けられた樹脂をさらに含み、前記バンプは、その先端部
を除いて前記樹脂によって覆われていてもよい。(8) In this semiconductor device, a surface of the semiconductor chip is provided in close contact with the semiconductor chip except for a surface of the semiconductor chip opposite to the substrate, and a surface of the semiconductor chip opposite to the substrate. And the bump may be covered with the resin except for a tip portion thereof.
【００１９】これによって、半導体装置における基板の
側とは反対側に外部端子を設けることが可能となり、設
計自由度の高い半導体装置を提供することができる。This makes it possible to provide external terminals on the side opposite to the substrate side of the semiconductor device, thereby providing a semiconductor device with a high degree of design freedom.
【００２０】（９）この半導体装置において、前記基板
には複数の貫通穴が形成されており、前記配線パターン
は、前記基板における前記半導体チップの搭載面に形成
され、前記配線パターンの一部は、前記貫通穴を通って
形成されており、前記貫通穴を介して、前記基板におけ
る前記半導体チップの搭載側とは反対側に、複数の外部
端子が形成されてもよい。(9) In this semiconductor device, a plurality of through holes are formed in the substrate, and the wiring pattern is formed on a mounting surface of the semiconductor chip on the substrate, and a part of the wiring pattern is formed. A plurality of external terminals may be formed through the through-hole, and on the opposite side of the substrate from the mounting side of the semiconductor chip via the through-hole.
【００２１】これによって、半導体装置の両面に外部端
子を形成することができる。As a result, external terminals can be formed on both surfaces of the semiconductor device.
【００２２】（１０）本発明に係る回路基板は、上記半
導体装置が搭載されている。(10) A circuit board according to the present invention has the above-described semiconductor device mounted thereon.
【００２３】（１１）本発明に係る電子機器は、上記半
導体装置を有する。(11) An electronic apparatus according to the present invention includes the above semiconductor device.
【００２４】[0024]
【発明の実施の形態】以下に、本発明の好適な実施の形
態について図面を参照して説明する。ただし、本発明は
以下の実施の形態に限定されるものではない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments.
【００２５】図１〜図５は、本実施の形態に係る半導体
装置及びその製造方法を説明する図である。図１は本実
施の形態に係る半導体装置の製造方法から製造されてな
る半導体装置の一例を示す図である。図１に示すよう
に、本実施の形態に係る半導体装置１は、少なくとも、
半導体チップ１０と、基板２０とを含む。以下に本実施
の形態に係る半導体装置の構成について説明する。FIGS. 1 to 5 are views illustrating a semiconductor device and a method of manufacturing the same according to the present embodiment. FIG. 1 is a view showing an example of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment. As shown in FIG. 1, the semiconductor device 1 according to the present embodiment has at least
The semiconductor device includes a semiconductor chip and a substrate. Hereinafter, the configuration of the semiconductor device according to the present embodiment will be described.
【００２６】半導体チップ１０は、複数の電極（又はパ
ッド）１２を有する。各電極１２は、例えばアルミニウ
ムで形成されることが多い。電極１２の表面は、ほぼ平
坦になっているが、バンプの形状をなしていてもよい。
電極１２の表面の形状は特に限定されないが矩形である
ことが多い。電極１２は、半導体チップ１０の面と面一
になっていてもよい。電極１２の表面の少なくとも一部
を避けて、半導体チップ１０には絶縁膜（図示しない）
が形成されている。絶縁膜は、例えば、ＳｉＯ 2、Ｓｉ
Ｎ、ポリイミド樹脂などで形成することができる。複数
の電極１２は、半導体チップ１０の端部に並んでいて
も、半導体チップ１０の中央部に並んでいてもよい。ま
た、電極１２は、半導体チップの１０が矩形をなすとき
に平行な２辺の端部に沿って並んでいても、４辺の端部
に並んでいてもよい。なお、電極１２上に、ハンダボー
ル、金ワイヤーボール、金メッキなどからなるバンプ１
４が形成されていてもよい。この場合に、電極１２とバ
ンプ１４との間にバンプ金属の拡散防止層として、ニッ
ケル、クロム、チタン等を付加してもよい。The semiconductor chip 10 includes a plurality of electrodes (or
12). Each electrode 12 is made of, for example, aluminum.
It is often formed by a system. The surface of the electrode 12 is substantially flat
Although it is flat, it may have a bump shape.
The shape of the surface of the electrode 12 is not particularly limited, but is rectangular.
Often. The electrode 12 is flush with the surface of the semiconductor chip 10.
It may be. At least a part of the surface of the electrode 12
Insulation film (not shown) is formed on the semiconductor chip 10 to avoid
Are formed. The insulating film is made of, for example, SiO Two, Si
It can be formed of N, a polyimide resin, or the like. Multiple
Electrodes 12 are arranged at the end of the semiconductor chip 10.
May be arranged in the center of the semiconductor chip 10. Ma
The electrode 12 is used when the semiconductor chip 10 has a rectangular shape.
Even if they are lined up along the edges of two sides parallel to
May be lined up. Note that a solder board is placed on the electrode 12.
1 consisting of metal, gold wire ball, gold plating, etc.
4 may be formed. In this case, the electrode 12 and the battery
A bump metal diffusion preventing layer
Kel, chromium, titanium or the like may be added.
【００２７】基板２０は、有機系又は無機系のいずれの
材料から形成されたものであってもよく、これらの複合
構造からなるものであってもよい。有機系の材料から形
成された基板２０として、例えばポリイミド樹脂からな
るフレキシブル基板が挙げられる。フレキシブル基板と
して、ＴＡＢ技術で使用されるテープを使用してもよ
い。また、無機系の材料から形成された基板２０とし
て、例えばセラミック基板やガラス基板が挙げられる。
有機系及び無機系の材料の複合構造として、例えばガラ
スエポキシ基板が挙げられる。また、基板２０として、
多層基板やビルドアップ型基板を用いてもよい。The substrate 20 may be formed of either an organic or inorganic material, or may be formed of a composite structure thereof. As the substrate 20 formed of an organic material, for example, a flexible substrate made of a polyimide resin is exemplified. As the flexible substrate, a tape used in TAB technology may be used. Further, as the substrate 20 formed of an inorganic material, for example, a ceramic substrate or a glass substrate can be used.
As a composite structure of an organic material and an inorganic material, for example, a glass epoxy substrate can be given. Also, as the substrate 20,
A multilayer substrate or a build-up type substrate may be used.
【００２８】また、基板２０として、複数の半導体チッ
プ１０の搭載領域がマトリクス状に設けられた基板を用
いてもよい。この場合には、後の工程（例えば一括して
樹脂封止する工程の後の工程）で半導体チップ１０の搭
載領域に分けて切断される。Further, as the substrate 20, a substrate in which a plurality of mounting areas for the semiconductor chips 10 are provided in a matrix may be used. In this case, the semiconductor chip 10 is cut into the mounting region of the semiconductor chip 10 in a later step (for example, a step after the step of collectively sealing the resin).
【００２９】配線パターン２２は、基板２０の一方、又
は両方の面に形成される。配線パターン２２は、複数層
から構成されることが多い。例えば、銅（Ｃｕ）、クロ
ム（Ｃｒ）、チタン（Ｔｉ）、ニッケル（Ｎｉ）、チタ
ンタングステン（Ｔｉ−Ｗ）のうちのいずれかを積層し
て配線パターン２２を形成することができる。配線パタ
ーン２２は、フォトリソグラフィ、スパッタ、又はメッ
キ処理によって形成してもよい。また、配線パターンの
一部は、配線となる部分よりも面積の大きいランド部と
なっていてもよい。ランド部は電気的接続部を十分に確
保する機能を有し、半導体チップ１０の電極１２又は外
部端子３２などの電気的接続部として設けられることが
多い。The wiring pattern 22 is formed on one or both surfaces of the substrate 20. The wiring pattern 22 is often composed of a plurality of layers. For example, the wiring pattern 22 can be formed by stacking any one of copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), and titanium tungsten (Ti-W). The wiring pattern 22 may be formed by photolithography, sputtering, or plating. In addition, a part of the wiring pattern may be a land part having a larger area than a part to be a wiring. The land portion has a function of sufficiently securing an electrical connection portion, and is often provided as an electrical connection portion such as the electrode 12 or the external terminal 32 of the semiconductor chip 10.
【００３０】基板２０には、両方の面を電気的に導通す
るための貫通穴２６が形成されていてもよい。貫通穴２
６は、基板２０がテープ基板である場合には、パンチ、
エッチング等で形成してもよい。基板２０に貫通穴２６
が形成されている場合に、配線パターン２２の一部は、
貫通穴２６上を通る。貫通穴２６を形成することによっ
て、基板２０における配線パターン２２の形成面にかか
わらず、基板２０の両方の側から配線パターン２２との
電気的接続を図ることができる。配線パターン２２は、
配線となる部分よりも面積の大きいランド部を有し、ラ
ンド部は貫通穴２６を塞いで形成されていてもよい。The substrate 20 may be provided with a through hole 26 for electrically connecting both surfaces. Through hole 2
6 is a punch when the substrate 20 is a tape substrate;
It may be formed by etching or the like. Through hole 26 in substrate 20
Is formed, a part of the wiring pattern 22
It passes over the through hole 26. By forming the through holes 26, electrical connection with the wiring pattern 22 can be achieved from both sides of the substrate 20 irrespective of the surface on which the wiring pattern 22 is formed on the substrate 20. The wiring pattern 22
A land portion having an area larger than that of a portion serving as a wiring may be provided, and the land portion may be formed so as to cover the through hole 26.
【００３１】半導体チップ１０は基板２０にフェースダ
ウンボンディングされている。基板２０の配線パターン
２２の形成面に半導体チップ１０が搭載されていてもよ
い。半導体チップ１０は、異方性導電材料２４を介して
基板２０に搭載されていてもよく、形態はこれに限定さ
れない。The semiconductor chip 10 is face-down bonded to the substrate 20. The semiconductor chip 10 may be mounted on the surface of the substrate 20 on which the wiring pattern 22 is formed. The semiconductor chip 10 may be mounted on the substrate 20 via the anisotropic conductive material 24, and the form is not limited to this.
【００３２】半導体チップ１０における基板２０を向く
側とは反対側の面を除いて、半導体チップ１０に密着し
て、基板２０の一方の面に樹脂４０が設けられていても
よい。この場合に、半導体チップ１０における前記反対
側の面は、その周囲の樹脂４０の面と面一となっていて
もよい。また、図１に示すように、樹脂４０の面の一部
に、バンプ３０が露出していてもよい。バンプ３０は複
数であってもよく、この場合はそれぞれのバンプ３０の
一部が露出してもよい。バンプ３０は、基板２０におけ
る配線パターン２２の一部（例えばランド部）に設けら
れている。バンプ３０は、ハンダボールの一部や銅から
なるものであってもよく、導電性のものであればその構
成は問わない。バンプ３０の一部が露出している場合
に、その露出部を半導体装置の電気的接続部とすること
ができる。すなわち、バンプ３０の露出部に、ハンダボ
ール等の導電部材からなる外部端子をさらに設けてもよ
い。Resin 40 may be provided on one surface of substrate 20 in close contact with semiconductor chip 10 except for the surface of semiconductor chip 10 opposite to the side facing substrate 20. In this case, the surface on the opposite side of the semiconductor chip 10 may be flush with the surface of the resin 40 around it. Further, as shown in FIG. 1, the bump 30 may be exposed on a part of the surface of the resin 40. A plurality of bumps 30 may be provided, and in this case, a part of each bump 30 may be exposed. The bump 30 is provided on a part (for example, a land) of the wiring pattern 22 on the substrate 20. The bump 30 may be made of a part of a solder ball or copper, and its configuration is not limited as long as it is conductive. When a part of the bump 30 is exposed, the exposed part can be used as an electrical connection part of the semiconductor device. That is, an external terminal made of a conductive member such as a solder ball may be further provided on the exposed portion of the bump 30.
【００３３】上述のバンプ３０の他に、基板２０におけ
る半導体チップ１０とは反対側にハンダ等の導電部材か
らなる外部端子３２を設けてもよい。配線パターン２２
が基板２０の半導体チップ１０の面に形成される場合
に、外部端子３２は、貫通穴２６を介して、基板２０に
おける半導体チップ１０とは反対側に突出してもよい。
なお、外部端子３２は、この形態に限定されず、基板２
０における半導体チップ１０とは反対側に突出していれ
ばよい。In addition to the bumps 30 described above, external terminals 32 made of a conductive material such as solder may be provided on the substrate 20 on the side opposite to the semiconductor chip 10. Wiring pattern 22
Is formed on the surface of the semiconductor chip 10 of the substrate 20, the external terminals 32 may protrude through the through holes 26 to the opposite side of the substrate 20 from the semiconductor chip 10.
Note that the external terminals 32 are not limited to this form, and
0 may protrude to the opposite side of the semiconductor chip 10.
【００３４】図２は、本実施の形態に係る半導体装置１
が複数、積み重ねられてなる、いわゆるスタックド型の
半導体装置である。半導体装置１は、上述のように、そ
の両面の側に外部端子を形成することができるので、二
つ以上の半導体装置１を積み重ねることができる。例え
ば、半導体装置１の封止樹脂４０の側の面に形成された
バンプ３０の電気的接続部と、別の半導体装置１の基板
２０の側に設けられた外部端子３２と、を電気的に導通
させてもよい。この場合に、接着剤５０を介して、半導
体装置を積み重ねてもよい。これによって、実装面積を
無駄に広げることなく高集積の半導体装置を提供するこ
とができる。FIG. 2 shows a semiconductor device 1 according to this embodiment.
Are stacked, that is, a so-called stacked semiconductor device. As described above, since the external terminals can be formed on both sides of the semiconductor device 1, two or more semiconductor devices 1 can be stacked. For example, the electrical connection of the bump 30 formed on the surface of the semiconductor device 1 on the side of the sealing resin 40 and the external terminal 32 provided on the substrate 20 of another semiconductor device 1 are electrically connected. It may be conducted. In this case, the semiconductor devices may be stacked via the adhesive 50. Thus, a highly integrated semiconductor device can be provided without unnecessarily increasing the mounting area.
【００３５】以下に、本実施の形態に係る半導体装置の
製造方法について説明する。Hereinafter, a method of manufacturing a semiconductor device according to the present embodiment will be described.
【００３６】（研削工程前の工程）本工程は、半導体チ
ップ１０を搭載する工程を含む。また、本工程はさら
に、バンプ３０を形成する工程と、樹脂封止する工程と
を含んでもよい。(Step Before Grinding Step) This step includes a step of mounting the semiconductor chip 10. In addition, this step may further include a step of forming the bump 30 and a step of resin sealing.
【００３７】図３に示すように、半導体チップ１０にお
ける電極１２の形成された面を基板２０に対向させて搭
載し、電極１２と配線パターン２２とを電気的に接続す
る。すなわち、半導体チップ１０を基板２０にフェース
ダウンボンディングする。この場合に図３に示すよう
に、半導体チップ１０を基板２０における配線パターン
２２の形成面に搭載してもよい。As shown in FIG. 3, the surface of the semiconductor chip 10 on which the electrodes 12 are formed is mounted so as to face the substrate 20, and the electrodes 12 and the wiring patterns 22 are electrically connected. That is, the semiconductor chip 10 is face-down bonded to the substrate 20. In this case, as shown in FIG. 3, the semiconductor chip 10 may be mounted on the surface of the substrate 20 where the wiring pattern 22 is formed.
【００３８】フェースダウンボンディングでは、導電樹
脂ペーストによるもの、Ａｕ−Ａｕ、Ａｕ−Ｓｎ、ハン
ダなどによる金属接合によるもの、絶縁樹脂の収縮力に
よるものなどの形態があり、そのいずれの形態を用いて
もよい。図３に示すよに、異方性導電材料２４を介し
て、半導体チップ１０をフェースダウンボンディングし
てもよい。The face-down bonding includes a method using a conductive resin paste, a method using metal bonding with Au-Au, Au-Sn, solder, and the like, and a method using a contraction force of an insulating resin. Is also good. As shown in FIG. 3, the semiconductor chip 10 may be face-down bonded via the anisotropic conductive material 24.
【００３９】異方性導電材料２４は、接着剤（バイン
ダ）に導電粒子（導電フィラー）が分散されたもので、
分散剤が添加される場合もある。異方性導電材料２４の
接着剤として、熱硬化性の接着剤が使用されることが多
い。異方性導電材料２４は、少なくとも配線パターン２
２における半導体チップ１０とのボンディング部上に設
けられる。この場合に、異方性導電材料２４は異方性導
電膜であってもよく、予め半導体チップ１０又は基板２
０に貼り付けられてもよい。また、基板２０が短冊状の
基板である場合には、一括して基板２０の全面に異方性
導電材料２４を設けてもよい。異方性導電材料２４を設
けた基板２０に半導体チップ１０を搭載することで、導
電粒子が電極１２と配線パターン２２との間で押しつぶ
されて、両者間での電気的導通を図るようになってい
る。なお、熱硬化性の樹脂を接着剤として使用したとき
には、異方性導電材料２４を加熱しながら押圧すること
が好ましい。こうして、異方性導電材料２４の接着剤
は、半導体チップ１０と基板２０とを接着して固定す
る。The anisotropic conductive material 24 is obtained by dispersing conductive particles (conductive filler) in an adhesive (binder).
Dispersants may be added. As the adhesive for the anisotropic conductive material 24, a thermosetting adhesive is often used. The anisotropic conductive material 24 includes at least the wiring pattern 2
2 is provided on the bonding portion with the semiconductor chip 10 in FIG. In this case, the anisotropic conductive material 24 may be an anisotropic conductive film.
0 may be attached. When the substrate 20 is a strip-shaped substrate, the anisotropic conductive material 24 may be provided on the entire surface of the substrate 20 in a lump. By mounting the semiconductor chip 10 on the substrate 20 provided with the anisotropic conductive material 24, the conductive particles are crushed between the electrode 12 and the wiring pattern 22, and electrical conduction between the two is achieved. ing. When a thermosetting resin is used as the adhesive, it is preferable that the anisotropic conductive material 24 is pressed while being heated. Thus, the adhesive of the anisotropic conductive material 24 adheres and fixes the semiconductor chip 10 and the substrate 20.
【００４０】また、異方性導電材料２４を除くその他の
フェースダウンボンディングの形態であっても、半導体
チップ１０と基板２０との間に接着剤を介して両者を固
定してもよい。この接着剤は、熱などによって、半導体
チップ１０に加わえられる応力を緩和する目的で設けら
れる、いわゆるアンダーフィル樹脂であってもよい。こ
の場合には、半導体チップ１０を基板２０に搭載した後
に、接着剤を両者の間に注入してもよく、予め基板２０
又は半導体チップ１０に設けておいてもよい。なお、半
導体チップ１０を基板２０により強く固着するために、
接着剤を半導体チップ１０の側面に及ぶまで設けても構
わない。In another face-down bonding mode other than the anisotropic conductive material 24, both may be fixed between the semiconductor chip 10 and the substrate 20 via an adhesive. This adhesive may be a so-called underfill resin provided for the purpose of relaxing the stress applied to the semiconductor chip 10 by heat or the like. In this case, after the semiconductor chip 10 is mounted on the substrate 20, an adhesive may be injected between the two.
Alternatively, it may be provided on the semiconductor chip 10. In order to firmly fix the semiconductor chip 10 to the substrate 20,
The adhesive may be provided up to the side surface of the semiconductor chip 10.
【００４１】図３に示すように、配線パターン２２に複
数のバンプ３０を設けてもよい。詳しくは、後の工程で
基板２０における半導体チップ１０の搭載面を樹脂封止
する工程を行う場合に、基板２０における半導体チップ
１０の搭載側に突出するバンプ３０を設けておいてもよ
い。配線パターン２２が基板２０の半導体チップ１０の
搭載面に形成されている場合は、配線パターン２２の一
部（ランド部）に、バンプ３０を設ければよい。例え
ば、ハンダペーストを用いたハンダ印刷や、ハンダボー
ルを配線パターン２２上に載せることによって、バンプ
３０を形成してもよい。なお、後の工程で樹脂封止する
工程を行う場合は、バンプ３０を形成する工程を、前記
樹脂封止工程の前に行っておくことが好ましい。As shown in FIG. 3, a plurality of bumps 30 may be provided on the wiring pattern 22. More specifically, when performing the step of resin-sealing the mounting surface of the semiconductor chip 10 on the substrate 20 in a later step, a bump 30 protruding from the mounting side of the semiconductor chip 10 on the substrate 20 may be provided. When the wiring pattern 22 is formed on the mounting surface of the substrate 20 on which the semiconductor chip 10 is mounted, a bump 30 may be provided on a part (land portion) of the wiring pattern 22. For example, the bump 30 may be formed by solder printing using a solder paste or by placing a solder ball on the wiring pattern 22. When a resin sealing step is performed in a later step, the step of forming the bumps 30 is preferably performed before the resin sealing step.
【００４２】図４に示すように、基板２０における半導
体チップ１０の搭載された面を樹脂４０で封止してもよ
い。封止には、金型を使用すればよい。金型を使用した
場合には、樹脂４０をモールド樹脂と称してもよい。基
板２０が複数の半導体チップ１０の搭載領域を有する場
合には、基板２０に搭載された複数の半導体チップ１０
を一括して樹脂封止してもよい。基板２０における半導
体チップ１０が搭載された面に配線パターン２２が形成
されていれば、樹脂４０によって配線パターン２２が覆
われて保護される。また、バンプ３０が形成されている
場合は、半導体チップ１０とともに、バンプ３０を樹脂
４０によって封止する。As shown in FIG. 4, the surface of the substrate 20 on which the semiconductor chip 10 is mounted may be sealed with a resin 40. A mold may be used for sealing. When a mold is used, the resin 40 may be referred to as a mold resin. When the substrate 20 has a mounting area for a plurality of semiconductor chips 10, the plurality of semiconductor chips 10 mounted on the substrate 20
May be collectively resin-sealed. If the wiring pattern 22 is formed on the surface of the substrate 20 on which the semiconductor chip 10 is mounted, the wiring pattern 22 is covered and protected by the resin 40. When the bumps 30 are formed, the bumps 30 are sealed with the resin 40 together with the semiconductor chip 10.
【００４３】なお変形例として、図５に示すように基板
２０の半導体チップ１０の搭載された面に樹脂４０を、
半導体チップ１０の高さを超えない程度に設けてもよ
い。バンプ３０を設けた場合には、バンプ３０の先端部
を露出させて樹脂４０を設けてもよい。これによって、
後の研削工程における樹脂４０の研削する量を少なくす
ることができるので、容易に研削工程を行うことができ
る。As a modification, as shown in FIG. 5, a resin 40 is provided on the surface of the substrate 20 on which the semiconductor chip 10 is mounted.
It may be provided not to exceed the height of the semiconductor chip 10. When the bump 30 is provided, the resin 40 may be provided by exposing the tip of the bump 30. by this,
Since the amount of grinding the resin 40 in the subsequent grinding process can be reduced, the grinding process can be easily performed.
【００４４】（研削する工程）基板２０上に搭載した半
導体チップ１０を研削して薄くする。図１は、本工程を
行うことによって形成した半導体装置の一例を示す図で
ある。(Step of Grinding) The semiconductor chip 10 mounted on the substrate 20 is ground and thinned. FIG. 1 is a diagram illustrating an example of a semiconductor device formed by performing this step.
【００４５】基板２０における半導体チップ１０の搭載
面を樹脂４０で封止した場合は、まず、樹脂４０の上面
を研削する。例えば、基板２０をＵＶテープ等の保持部
材に貼り付けて固定し、研削用冶具に設けた砥石などに
よって樹脂４０の上面を研削してもよい。樹脂４０を研
削していくと、半導体チップ１０における電極１２の形
成された面とは反対側の面が露出する。本工程では、そ
の露出面をさらに研削する。この場合に、半導体チップ
１０の露出した面と同時に、その周囲の樹脂４０の面も
同時に研削してもよい。言い換えると、封止樹脂４０の
上面の全体を面一に保ちつつ、半導体チップ１０を研削
してもよい。When the mounting surface of the semiconductor chip 10 on the substrate 20 is sealed with the resin 40, first, the upper surface of the resin 40 is ground. For example, the substrate 20 may be affixed to a holding member such as a UV tape and fixed, and the upper surface of the resin 40 may be ground with a grindstone provided on a grinding jig. As the resin 40 is ground, the surface of the semiconductor chip 10 opposite to the surface on which the electrodes 12 are formed is exposed. In this step, the exposed surface is further ground. In this case, the surface of the resin 40 surrounding the exposed surface of the semiconductor chip 10 may be ground simultaneously. In other words, the semiconductor chip 10 may be ground while keeping the entire upper surface of the sealing resin 40 flush.
【００４６】研削していくと、研削くずが生じる。この
場合に、半導体チップ１０の電極１２、又は配線パター
ン２２は、封止樹脂４０によって覆われているので、研
削くずによって、半導体装置の信頼性を損なうことな
く、薄い半導体装置を製造することができる。また、半
導体チップ１０は封止樹脂４０によって基板２０に固定
されているので、研削する際に基板２０を保持部材等で
固定すれば、確実に研削することができる。As the grinding is performed, grinding waste is generated. In this case, since the electrodes 12 or the wiring patterns 22 of the semiconductor chip 10 are covered with the sealing resin 40, a thin semiconductor device can be manufactured by grinding chips without impairing the reliability of the semiconductor device. it can. Further, since the semiconductor chip 10 is fixed to the substrate 20 by the sealing resin 40, if the substrate 20 is fixed by a holding member or the like at the time of grinding, the grinding can be surely performed.
【００４７】また、基板２０が複数の半導体チップ１０
の搭載領域を有する場合に、一括して樹脂封止した封止
樹脂４０の上面を一面に研削してもよい。すなわち、複
数の半導体チップ１０を一括して研削してもよい。これ
によって、効率良く薄い半導体装置を製造することがで
きる。The substrate 20 is composed of a plurality of semiconductor chips 10
In the case where the mounting region is provided, the upper surface of the sealing resin 40 which is collectively sealed with resin may be ground to one surface. That is, the plurality of semiconductor chips 10 may be ground at once. Thus, a thin semiconductor device can be manufactured efficiently.
【００４８】半導体チップ１０を樹脂封止する工程の前
に、基板２０の半導体チップ１０の搭載側に突出したバ
ンプ３０を形成した場合には、封止樹脂４０を研削して
いくと、バンプ３０の先端部が露出する。研削によって
バンプ３０の先端部が樹脂４０から露出した後に、さら
に封止樹脂４０の上面を研削してもよく、この場合に樹
脂４０から露出したバンプ３０の先端部を研削しても構
わない。いずれにしても、半導体チップ１０を研削した
後の半導体装置において、研削した面にバンプ３０の一
部を露出できればその形態は問わない。また、この場合
に、バンプ３０の露出部にさらに外部端子を設けてもよ
い。詳しくは、バンプ３０の露出部を電気的接続部とし
て、外部端子を前記露出部に設けてもよい。また、前記
外部端子は、バンプ３０と同一部材であってもよい。If the bump 30 protruding from the substrate 20 on the side on which the semiconductor chip 10 is mounted is formed before the step of sealing the semiconductor chip 10 with the resin, the bump 30 The tip of is exposed. After the tip of the bump 30 is exposed from the resin 40 by grinding, the upper surface of the sealing resin 40 may be further ground. In this case, the tip of the bump 30 exposed from the resin 40 may be ground. In any case, in the semiconductor device after the semiconductor chip 10 is ground, the form is not limited as long as a part of the bump 30 can be exposed on the ground surface. In this case, an external terminal may be further provided on the exposed portion of the bump 30. Specifically, the exposed portion of the bump 30 may be used as an electrical connection portion, and external terminals may be provided on the exposed portion. Further, the external terminal may be the same member as the bump 30.
【００４９】研削後において、バンプ３０とは別に、基
板２０における半導体チップ１０とは反対側に外部端子
３２を、貫通穴２６を介して設けてもよい（図１参
照）。これによって、配線パターン２２が基板２０の一
方の面にのみ形成されている場合であっても、配線パタ
ーン２２とは反対側の面に外部端子３２を形成すること
ができる。例えば、外部端子３２と配線パターン２２と
の電気的な接続を、貫通穴２６の内面にメッキされた金
や銅などの導電部材によって図ってもよい。あるいは、
ハンダボールを外部端子３２とする場合には、ハンダボ
ールの材料となるハンダを貫通穴２６に充填して、ハン
ダボールと一体化した導電部材を貫通穴２６内に形成し
てもよい。あるいは、外部端子３２が突出する側の面
に、配線パターン２２とビアホールやスルーホールで接
続された外部電極用のランド部を形成し、その上に外部
端子３２を形成してもよい。After the grinding, an external terminal 32 may be provided on the side of the substrate 20 opposite to the semiconductor chip 10 via the through-hole 26 in addition to the bump 30 (see FIG. 1). Thus, even when the wiring pattern 22 is formed only on one surface of the substrate 20, the external terminals 32 can be formed on the surface opposite to the wiring pattern 22. For example, the electrical connection between the external terminal 32 and the wiring pattern 22 may be achieved by a conductive member such as gold or copper plated on the inner surface of the through hole 26. Or,
When a solder ball is used as the external terminal 32, solder as a material of the solder ball may be filled in the through hole 26, and a conductive member integrated with the solder ball may be formed in the through hole 26. Alternatively, a land portion for an external electrode connected to the wiring pattern 22 by a via hole or a through hole may be formed on the surface on which the external terminal 32 protrudes, and the external terminal 32 may be formed thereon.
【００５０】本実施の形態によれば、半導体チップ１０
を基板２０に搭載した後に、基板２０上において半導体
チップ１０を研削して薄くする。すなわち、薄くて割れ
やすい半導体チップ１０そのものを取り扱うことがな
く、半導体装置を製造することができる。According to the present embodiment, the semiconductor chip 10
After the semiconductor chip 10 is mounted on the substrate 20, the semiconductor chip 10 is ground and thinned on the substrate 20. In other words, the semiconductor device can be manufactured without handling the thin and fragile semiconductor chip 10 itself.
【００５１】上述の外部端子の形態として、積極的に外
部端子を形成せずマザーボード実装時にマザーボード側
に塗布されるハンダクリームを利用し、その溶融時の表
面張力で結果的に外部端子を形成してもよい。その半導
体装置は、いわゆるランドグリッドアレイ型の半導体装
置である。As a form of the above-mentioned external terminal, a solder cream applied to the motherboard side at the time of mounting the motherboard without utilizing the external terminal is used, and the external terminal is eventually formed by the surface tension at the time of melting. You may. The semiconductor device is a so-called land grid array type semiconductor device.
【００５２】また、基板２０の一部を延出し、そこから
外部接続を図るようにしてもよい。基板２０の一部をコ
ネクタのリードとしたり、コネクタを基板２０上に実装
したり、基板２０の配線パターン２２そのものを他の電
子機器に接続してもよい。Further, a part of the substrate 20 may be extended and an external connection may be made therefrom. A part of the board 20 may be used as a lead of the connector, the connector may be mounted on the board 20, or the wiring pattern 22 of the board 20 may be connected to another electronic device.
【００５３】図５には、本実施の形態に係る半導体装置
を実装した回路基板１００が示されている。回路基板１
００には例えばガラスエポキシ基板等の有機系基板を用
いることが一般的である。回路基板１００には例えば銅
などからなる配線パターンが所望の回路となるように形
成されていて、それらの配線パターンと半導体装置の外
部端子とを機械的に接続することでそれらの電気的導通
を図る。FIG. 5 shows a circuit board 100 on which the semiconductor device according to the present embodiment is mounted. Circuit board 1
For 00, an organic substrate such as a glass epoxy substrate is generally used. Wiring patterns made of, for example, copper or the like are formed on the circuit board 100 so as to form a desired circuit, and the electrical continuity of the wiring patterns and the external terminals of the semiconductor device is established by mechanically connecting the wiring patterns and external terminals of the semiconductor device. Aim.
【００５４】そして、本発明を適用した半導体装置を有
する電子機器として、図６にはノート型パーソナルコン
ピュータ２００、図７には携帯電話３００が示されてい
る。FIG. 6 shows a notebook personal computer 200 and FIG. 7 shows a mobile phone 300 as an electronic apparatus having a semiconductor device to which the present invention is applied.
【００５５】なお、上記発明の構成要件で「半導体チッ
プ」を「電子素子」に置き換えて、半導体チップと同様
に電子素子（能動素子か受動素子かを問わない）を、基
板に実装して電子部品を製造することもできる。このよ
うな電子素子を使用して製造される電子部品として、例
えば、光素子、抵抗器、コンデンサ、コイル、発振器、
フィルタ、温度センサ、サーミスタ、バリスタ、ボリュ
ーム又はヒューズなどがある。The "semiconductor chip" is replaced by the "electronic element" in the constitutional requirements of the present invention, and an electronic element (whether an active element or a passive element) is mounted on a substrate in the same manner as the semiconductor chip. Parts can also be manufactured. As electronic components manufactured using such electronic elements, for example, optical elements, resistors, capacitors, coils, oscillators,
Examples include a filter, a temperature sensor, a thermistor, a varistor, a volume or a fuse.
【００５６】さらに、前述した全ての実装の形態は、半
導体チップ１０とその他の上記のような電子素子とが基
板上で混載実装される半導体装置（実装モジュール）で
あってもよい。Further, all of the above-described mounting forms may be a semiconductor device (mounting module) in which the semiconductor chip 10 and other electronic elements as described above are mounted together on a substrate.
【図１】図１は、本実施の形態に係る半導体装置及びそ
の製造方法を説明するための図である。FIG. 1 is a diagram for explaining a semiconductor device and a method of manufacturing the same according to an embodiment;
【図２】図２は、本実施の形態に係る半導体装置を示す
図である。FIG. 2 is a diagram illustrating a semiconductor device according to the present embodiment;
【図３】図３は、本実施の形態に係る半導体装置の製造
方法を説明するための図である。FIG. 3 is a diagram for explaining the method for manufacturing the semiconductor device according to the present embodiment.
【図４】図４は、本実施の形態に係る半導体装置の製造
方法を説明するための図である。FIG. 4 is a diagram for explaining the method for manufacturing the semiconductor device according to the present embodiment.
【図５】図５は、本実施の形態に係る半導体装置の製造
方法の変形例を説明するための図である。FIG. 5 is a view for explaining a modification of the method for manufacturing a semiconductor device according to the present embodiment;
【図６】図６は、本実施の形態に係る半導体装置の製造
方法から製造されてなる半導体装置を搭載した回路基板
を示す図である。FIG. 6 is a diagram showing a circuit board on which a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment is mounted.
【図７】図７は、本実施の形態に係る半導体装置の製造
方法から製造されてなる半導体装置を有する電子機器を
示す図である。FIG. 7 is a diagram showing an electronic apparatus having a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment;
【図８】図８は、本実施の形態に係る半導体装置の製造
方法から製造されてなる半導体装置を有する電子機器を
示す図である。FIG. 8 is a diagram illustrating an electronic apparatus having a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present embodiment;
１０ 半導体チップ １２ 電極 １４ バンプ ２０ 基板 ２２ 配線パターン ２４ 異方性導電材料 ２６ 貫通穴 ３０ バンプ ３２ 外部端子 ４０ 樹脂 ５０ 接着剤 DESCRIPTION OF SYMBOLS 10 Semiconductor chip 12 Electrode 14 Bump 20 Substrate 22 Wiring pattern 24 Anisotropic conductive material 26 Through hole 30 Bump 32 External terminal 40 Resin 50 Adhesive
Claims (11)
する基板に、半導体チップにおける電極形成面を対向さ
せて搭載し、前記電極と前記配線パターンとを電気的に
接続して固定する工程と、 前記工程後に、前記半導体チップにおける前記基板とは
反対側の面を研削する工程と、 を含む半導体装置の製造方法。1. A step of mounting an electrode forming surface of a semiconductor chip on a substrate having a wiring pattern on at least one surface thereof, and electrically connecting and fixing the electrode and the wiring pattern; After the step, grinding the surface of the semiconductor chip opposite to the substrate.
おいて、 前記半導体チップを搭載する工程で、接着剤を介して前
記半導体チップを前記基板に固定する半導体装置の製造
方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of mounting the semiconductor chip, the semiconductor chip is fixed to the substrate via an adhesive.
おいて、 前記半導体チップを搭載する工程で、 前記接着剤は導電粒子が分散されてなる異方性導電材料
であり、前記導電粒子を介して、前記電極と前記配線パ
ターンとを電気的に接続する半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein in the step of mounting the semiconductor chip, the adhesive is an anisotropic conductive material in which conductive particles are dispersed, and And a method of manufacturing a semiconductor device for electrically connecting the electrode and the wiring pattern.
の半導体装置の製造方法において、 前記研削する工程前に、前記基板における一方の面で前
記半導体チップを樹脂封止する工程をさらに含み、 前記研削する工程は、前記樹脂を研削して、前記半導体
チップにおける前記電極形成面とは反対側の面を露出さ
せ、前記露出面及びその周囲の前記樹脂の面を研削する
工程である半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of resin-sealing the semiconductor chip on one surface of the substrate before the grinding step. The grinding step is a step of grinding the resin to expose a surface of the semiconductor chip opposite to the electrode forming surface, and grinding the exposed surface and the surface of the resin around the exposed surface. A method for manufacturing a semiconductor device.
おいて、 前記樹脂封止する工程前に、複数のバンプを、前記基板
における前記半導体チップの搭載側の前記半導体チップ
の搭載領域外に形成する工程をさらに含み、 前記樹脂を、前記バンプを覆うように設け、 前記研削する工程は、前記露出面及びその周囲の前記樹
脂の面を研削するとともに、前記バンプの一部を露出さ
せる工程である半導体装置の製造方法。5. The method for manufacturing a semiconductor device according to claim 4, wherein a plurality of bumps are formed outside the mounting area of the semiconductor chip on the mounting side of the semiconductor chip on the substrate before the step of resin sealing. The resin is provided so as to cover the bump, and the grinding is a step of grinding the exposed surface and the surface of the resin around the exposed surface and exposing a part of the bump. A method for manufacturing a semiconductor device.
の半導体装置の製造方法から製造されてなる半導体装
置。6. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.
成された基板と、 複数の電極を有し、前記基板にフェースダウンボンディ
ングされた半導体チップと、 前記基板における前記半導体チップの搭載領域外に設け
られ、前記基板における前記半導体チップの搭載側に形
成された複数のバンプと、 を含む半導体装置。7. A substrate having a wiring pattern formed on at least one surface, a semiconductor chip having a plurality of electrodes, face-down bonded to the substrate, and a semiconductor chip provided outside the substrate mounting area on the substrate. And a plurality of bumps formed on the substrate on the mounting side of the semiconductor chip.
いて前記半導体チップに密着して設けられ、かつ、前記
半導体チップにおける前記基板とは反対側の面と面一と
なって設けられた樹脂をさらに含み、 前記バンプは、その先端部を除いて前記樹脂によって覆
われている半導体装置。8. The semiconductor device according to claim 7, wherein the semiconductor chip is provided in close contact with the semiconductor chip except for a surface of the semiconductor chip opposite to the substrate, and is opposite to the substrate in the semiconductor chip. A semiconductor device further comprising a resin provided flush with a side surface, wherein the bumps are covered with the resin except for a tip thereof.
置において、 前記基板には複数の貫通穴が形成されており、 前記配線パターンは、前記基板における前記半導体チッ
プの搭載面に形成され、前記配線パターンの一部は、前
記貫通穴を通って形成されており、 前記貫通穴を介して、前記基板における前記半導体チッ
プの搭載側とは反対側に、複数の外部端子が形成された
半導体装置。9. The semiconductor device according to claim 7, wherein a plurality of through holes are formed in the substrate, and the wiring pattern is formed on a mounting surface of the semiconductor chip on the substrate. A part of the wiring pattern is formed through the through hole, and a plurality of external terminals are formed on the substrate on the side opposite to the mounting side of the semiconductor chip through the through hole. Semiconductor device.
載の半導体装置が搭載された回路基板。10. A circuit board on which the semiconductor device according to claim 6 is mounted.
載の半導体装置を有する電子機器。11. An electronic apparatus comprising the semiconductor device according to claim 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000112169A JP2001298115A (en) | 2000-04-13 | 2000-04-13 | Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000112169A JP2001298115A (en) | 2000-04-13 | 2000-04-13 | Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment |
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|---|---|
| JP2001298115A true JP2001298115A (en) | 2001-10-26 |
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ID=18624385
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000112169A Pending JP2001298115A (en) | 2000-04-13 | 2000-04-13 | Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment |
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| US9171792B2 (en) | 2011-02-28 | 2015-10-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages having a side-by-side device arrangement and stacking functionality |
| JP2013012522A (en) * | 2011-06-28 | 2013-01-17 | Shinko Electric Ind Co Ltd | Package and method for manufacturing package |
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