JPH09223755A - Package for storing semiconductor element - Google Patents
Package for storing semiconductor elementInfo
- Publication number
- JPH09223755A JPH09223755A JP8026970A JP2697096A JPH09223755A JP H09223755 A JPH09223755 A JP H09223755A JP 8026970 A JP8026970 A JP 8026970A JP 2697096 A JP2697096 A JP 2697096A JP H09223755 A JPH09223755 A JP H09223755A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- identification mark
- insulating substrate
- package
- insulating base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＬＳＩ（大規模集積
回路素子）等の半導体素子を収容するための半導体素子
収納用パッケージに関し、詳しくはパッケージ外表面に
おける識別標識の形成に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device such as an LSI (Large Scale Integrated Circuit Device), and more particularly to the formation of an identification mark on the outer surface of the package.
【０００２】[0002]
【従来の技術】半導体素子を収容するための半導体素子
収納用パッケージには、外部リード端子の取着位置によ
り、サイドブレーズパッケージやトップブレーズパッケ
ージ・ボトムブレーズパッケージなどの種類がある。こ
のうち従来のトップブレーズパッケージの一般的な構成
を図２に断面図で示す。2. Description of the Related Art There are various types of semiconductor element housing packages for housing semiconductor elements, such as a side blazed package, a top blazed package and a bottom blazed package, depending on the mounting position of external lead terminals. Among them, a general structure of a conventional top blazed package is shown in a sectional view in FIG.
【０００３】図２に断面図で示す従来の半導体素子収納
用パッケージ21は、例えば酸化アルミニウム質焼結体や
ムライト質焼結体・窒化アルミニウム焼結体・炭化珪素
質焼結体等の電気絶縁材料から成り、上面に半導体素子
26を載置収容するための載置部22ａおよび載置部22ａ周
辺から外周縁にかけて導出されたタングステンあるいは
モリブデン・マンガン等の高融点金属粉末の焼結体から
成る複数個のメタライズ配線層23・23を有する絶縁基体
22と、半導体素子26を外部電気回路に電気的に接続する
ためにメタライズ配線層23・23に銀ロウや金−シリコン
ロウ等のロウ材を介して取着された外部リード端子24・
24と、蓋体25とから構成されており、絶縁基体22の載置
部22ａに半導体素子26を金−シリコンロウ等のロウ材か
ら成る接着剤27を介して載置固定するとともに、半導体
素子26の各電極をボンディングワイヤ28・28を介してメ
タライズ配線層23・23に電気的に接続し、しかる後、絶
縁基体22上面に蓋体25をロウ材・ガラス・樹脂等の封止
材29・29を介して、あるいは溶接により接合して、絶縁
基体22と蓋体25とから成る容器内部に半導体素子26を気
密に封止している。これにより、製品としての半導体装
置となる。A conventional semiconductor element housing package 21 shown in a sectional view in FIG. 2 is an electrical insulation of, for example, an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, or a silicon carbide sintered body. Made of material, semiconductor element on top
A mounting portion 22a for mounting and accommodating 26 and a plurality of metallized wiring layers 23 made of a sintered body of refractory metal powder such as tungsten or molybdenum / manganese which is led out from the periphery of the mounting portion 22a to the outer peripheral edge. Insulating substrate with 23
22 and external lead terminals 24 attached to the metallized wiring layers 23, 23 via a brazing material such as silver brazing or gold-silicon brazing in order to electrically connect the semiconductor element 26 to an external electric circuit.
24 and a lid 25, the semiconductor element 26 is mounted and fixed on the mounting portion 22a of the insulating base 22 via an adhesive 27 made of a brazing material such as gold-silicon braze, and the semiconductor element Each electrode of 26 is electrically connected to the metallized wiring layers 23, 23 through the bonding wires 28, 28, and then the lid 25 is attached to the upper surface of the insulating substrate 22 with a sealing material 29 such as a brazing material, glass, or resin. The semiconductor element 26 is hermetically sealed inside the container composed of the insulating base body 22 and the lid body 25 via 29 or by welding. As a result, a semiconductor device as a product is obtained.
【０００４】また、絶縁基体22の下面には、半導体装置
の品番や製造者名、あるいは半導体装置の方向性を示す
識別標識30が被着形成されており、この識別標識30を目
視やカメラ等により認識することによって、半導体装置
の品番や製造者名、あるいは半導体装置の方向性が確認
できるようになっている。このような識別標識30は、一
般にタングステンやモリブデン等の高融点金属から成る
メタライズ層や絶縁基体22と色調が異なる絶縁層によっ
て形成されており、通常、20〜50μｍ程度の厚みを有し
ている。Further, on the lower surface of the insulating substrate 22, an identification mark 30 showing the product number of the semiconductor device, the manufacturer's name, or the directionality of the semiconductor device is adhered and formed. The identification mark 30 can be visually observed, a camera or the like. It is possible to confirm the product number of the semiconductor device, the manufacturer's name, or the directionality of the semiconductor device by recognizing. Such an identification mark 30 is generally formed of a metallized layer made of a refractory metal such as tungsten or molybdenum or an insulating layer having a color tone different from that of the insulating substrate 22, and usually has a thickness of about 20 to 50 μm. .
【０００５】このような半導体素子収納用パッケージ21
において絶縁基体22の載置部22ａに半導体素子26を接着
固定する方法としては、接着剤27が溶融する温度以上に
絶縁基体22を加熱し、加熱された絶縁基体22の載置部22
ａに上記接着剤27を介して半導体素子26を載置して、半
導体素子26を複数回スクライブすることにより載置部22
ａと半導体素子26下面との間に接着剤27を濡れ広がら
せ、しかる後に接着剤27を冷却固化させる方法が採用さ
れている。Such a semiconductor element housing package 21
In order to bond and fix the semiconductor element 26 to the mounting portion 22a of the insulating base 22, the insulating base 22 is heated to a temperature above the temperature at which the adhesive 27 melts, and the mounting portion 22 of the heated insulating base 22 is heated.
The semiconductor element 26 is mounted on the a via the adhesive 27, and the semiconductor element 26 is scribed a plurality of times to mount the semiconductor element 26 on the mounting portion 22.
A method is adopted in which the adhesive 27 is wetted and spread between a and the lower surface of the semiconductor element 26, and then the adhesive 27 is cooled and solidified.
【０００６】そして絶縁基体22を加熱するにはヒーター
ブロックが用いられ、ヒーターブロックの上面に設けら
れた平坦な載置面に絶縁基体22をその下面が密着するよ
うに載置して、所定の温度に加熱することが行なわれて
いる。A heater block is used to heat the insulating base 22, and the insulating base 22 is mounted on a flat mounting surface provided on the upper surface of the heater block so that the lower surface of the insulating base 22 is in close contact with the insulating base 22. Heating to temperature is being performed.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、従来の
半導体素子収納用パッケージ21では、絶縁基体22の下面
に被着形成された識別標識30の厚みが20〜50μｍ程度あ
るため、ヒーターブロックの平坦な載置面に絶縁基体22
の下面を載置すると、載置部22ａに対向する絶縁基体22
の下面とヒーターブロックの載置面との間に識別標識30
の厚みに起因する隙間が形成されていた。そのため、ヒ
ーターブロックから絶縁基体22への熱の伝達が阻害され
てしまい、絶縁基体22を所定の温度に加熱するのに長時
間を要するという問題点があった。However, in the conventional package 21 for accommodating semiconductor elements, since the identification mark 30 formed on the lower surface of the insulating substrate 22 has a thickness of about 20 to 50 μm, the heater block is flat. Insulating substrate 22 on the mounting surface
When the lower surface of the base is placed, the insulating base 22 facing the placement portion 22a
Identification mark 30 between the underside of the heater and the mounting surface of the heater block
A gap was formed due to the thickness of the. Therefore, the heat transfer from the heater block to the insulating substrate 22 is hindered, and it takes a long time to heat the insulating substrate 22 to a predetermined temperature.
【０００８】また、絶縁基体22の下面とヒーターブロッ
クの載置面との接触に偏りが生じて両者の接触面積が極
めて小さくなってしまい、絶縁基体22が局部的に加熱さ
れてその内部に急峻な温度勾配が形成されるために、大
きな熱応力が発生して絶縁基体22に割れやクラックを発
生させてしまうという問題点もあった。Further, the contact between the lower surface of the insulating base 22 and the mounting surface of the heater block becomes uneven, and the contact area between the two becomes extremely small, so that the insulating base 22 is locally heated and steeped inside. There is also a problem that a large thermal stress is generated due to the formation of such a temperature gradient to cause cracks or cracks in the insulating substrate 22.
【０００９】これに対して、絶縁基体の下面に凹部を形
成して、この凹部を識別標識とすることによって絶縁基
体の下面とヒーターブロックの載置面とがほぼ一様に接
触するようにした半導体素子収納用パッケージが提案さ
れている。しかし、これによれば、絶縁基体の加熱のた
めの接触状態は改善されるものの、識別標識と絶縁基体
との色調が同一となるので目視やカメラ等による識別標
識の認識が困難であるという問題点があった。On the other hand, a concave portion is formed on the lower surface of the insulating substrate, and the concave portion is used as an identification mark so that the lower surface of the insulating substrate and the mounting surface of the heater block are substantially uniformly in contact with each other. A package for housing a semiconductor device has been proposed. However, according to this, although the contact state for heating the insulating base is improved, since the color tone of the identification mark and the insulating base are the same, it is difficult to visually recognize the identification mark with a camera or the like. There was a point.
【００１０】本発明はこのような従来技術の問題点に鑑
みて案出されたものであり、その目的は、目視やカメラ
による識別標識の認識が容易であるとともに、絶縁基体
の下面とヒーターブロックの載置面とを一様に接触させ
ることができて、半導体素子を接着固定するための加熱
を短時間でかつ均一に行なうことができる半導体素子収
納用パッケージを提供することにある。The present invention has been devised in view of the problems of the prior art as described above, and an object thereof is to facilitate visual recognition and identification of an identification mark by a camera, and also to provide a lower surface of an insulating substrate and a heater block. It is an object of the present invention to provide a package for accommodating a semiconductor element, which can make uniform contact with the mounting surface of the semiconductor element and can uniformly heat the semiconductor element in a short time.
【００１１】[0011]
【課題を解決するための手段】本発明は、上面に半導体
素子が載置される載置部を有し、下面に識別標識が被着
されている絶縁基体と、蓋体とから成り、内部に半導体
素子を収容するための空所を有する半導体素子収納用パ
ッケージであって、前記絶縁基体の下面の少なくとも前
記載置部に対向する領域に、前記識別標識の高さと同じ
もしくはそれ以上の高さを有する平坦な被着層が、前記
識別標識を露出させるようにして形成されていることを
特徴とするものである。SUMMARY OF THE INVENTION The present invention comprises an insulating base body having a mounting portion on which a semiconductor element is mounted on the upper surface, and an identification mark adhered on the lower surface, and a lid body. A semiconductor element housing package having a space for housing a semiconductor element therein, wherein the height of the identification mark is equal to or higher than the height of the identification mark in at least a region of the lower surface of the insulating base facing the mounting portion. A flat adherend layer having a thickness is formed so as to expose the identification mark.
【００１２】[0012]
【発明の実施の形態】本発明の半導体素子収納用パッケ
ージによれば、半導体素子が載置される載置部に対向す
る絶縁基体の下面の領域に、識別標識の高さと同じもし
くはそれ以上の高さを有する平坦な被着層を、識別標識
が露出するように形成したことから、載置部への半導体
素子の接着固定の際に絶縁基体をヒーターブロックに載
置した場合、絶縁基体の下面の少なくとも載置部に対向
する領域に形成された平坦な被着層とヒーターブロック
の載置面とが識別標識に影響されることなく一様に接触
して、ヒーターブロックの熱を良好かつ一様に絶縁基体
に伝達することができる。そのため、絶縁基体の載置部
の温度が短時間で所定の温度となり、半導体素子を効率
良く接着固定することができる。According to the semiconductor element housing package of the present invention, the height of the identification mark is equal to or higher than the height of the identification mark in the region of the lower surface of the insulating substrate facing the mounting portion on which the semiconductor element is mounted. Since the flat adherend layer having a height is formed so that the identification mark is exposed, when the insulating substrate is mounted on the heater block when the semiconductor element is bonded and fixed to the mounting portion, the insulating substrate The flat adherend layer formed in at least the area facing the mounting portion of the lower surface and the mounting surface of the heater block are in uniform contact without being affected by the identification mark, and heat of the heater block is good and It can be uniformly transferred to the insulating substrate. Therefore, the temperature of the mounting portion of the insulating base reaches a predetermined temperature in a short time, and the semiconductor element can be efficiently adhered and fixed.
【００１３】また、被着層を絶縁基体の下面のほぼ全面
にわたるように形成した場合には、その被着層の平坦な
広い面積でもって絶縁基体がヒーターブロックの載置面
に接触することから、絶縁基体とヒーターブロックとの
接触に従来の識別標識のみが形成された場合のような偏
りがなくなるので、絶縁基体が局部的に加熱されること
を防止することができる。そのため、絶縁基体中に急峻
な温度勾配が形成されることがなくなり、大きな熱応力
が発生して絶縁基体に割れやクラックが発生するのを防
止することができる。Further, when the adhered layer is formed so as to cover almost the entire lower surface of the insulating substrate, the insulating substrate comes into contact with the mounting surface of the heater block due to the flat and large area of the adhered layer. Since there is no bias in the contact between the insulating base and the heater block as in the case where only the conventional identification mark is formed, it is possible to prevent the insulating base from being locally heated. Therefore, a steep temperature gradient is not formed in the insulating substrate, and it is possible to prevent a large thermal stress from being generated and cracks or cracks in the insulating substrate.
【００１４】さらに、被着層は識別標識が露出するよう
に形成されているので、被着層を絶縁基体の下面のほぼ
全面にわたって形成した場合であっても、目視やカメラ
等により識別標識を容易に認識することができる。Further, since the adhered layer is formed so that the identification mark is exposed, even when the adhered layer is formed over almost the entire lower surface of the insulating substrate, the identification mark can be visually or by a camera or the like. Can be easily recognized.
【００１５】次に、本発明を添付図面に基づき詳細に説
明する。Next, the present invention will be described in detail with reference to the accompanying drawings.
【００１６】図１は本発明の半導体素子収納用パッケー
ジの一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of a package for housing a semiconductor device of the present invention.
【００１７】図１の半導体素子収納用パッケージ１にお
いて、２は絶縁基体であり、その上面に半導体素子６を
ロウ材から成る接着剤７を介して接着固定して載置収容
するための凹状の載置部２ａを有している。なお、接着
剤７には必要に応じてガラスや樹脂等を用いてもよい。
また、５は蓋体であり、絶縁基体２上面にロウ材・ガラ
ス・樹脂等の封止材９・９を介して、あるいは溶接によ
り接合されることによって、この蓋体５と絶縁基体２と
で半導体素子６を気密に収容するための空所が形成され
る。In the package 1 for accommodating semiconductor elements of FIG. 1, reference numeral 2 is an insulating base, and a concave shape for accommodating and accommodating the semiconductor element 6 on the upper surface thereof by adhering and fixing it with an adhesive 7 made of a brazing material. It has a mounting portion 2a. The adhesive 7 may be made of glass, resin or the like, if necessary.
Reference numeral 5 denotes a lid, which is joined to the upper surface of the insulating base 2 via a sealing material 9 or 9 made of a brazing material, glass, resin, or the like, or by welding so that the lid 5 and the insulating base 2 are joined together. Thus, a space for hermetically housing the semiconductor element 6 is formed.
【００１８】絶縁基体２は、酸化アルミニウム質焼結体
やムライト質焼結体・窒化アルミニウム焼結体・炭化珪
素質焼結体等の電気絶縁材料から成り、従来周知のセラ
ミックグリーンシート積層法によって作製されている。
例えば、酸化アルミニウム質焼結体から成る場合には、
酸化アルミニウム・酸化珪素・酸化マグネシウム・酸化
カルシウム等の原料粉末に適当な有機バインダ・溶剤等
を添加混合して泥漿物を作るとともに、その泥漿物をド
クターブレード法やカレンダーロール法を採用すること
によってセラミックグリーンシート（セラミック生シー
ト）と成し、しかる後、前記セラミックグリーンシート
に適当な打ち抜き加工を施すとともにこれを複数枚積層
し、約1600℃の温度で焼成することによって作製され
る。The insulating substrate 2 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, and a silicon carbide sintered body. Has been made.
For example, in the case of an aluminum oxide sintered body,
By adding and mixing a suitable organic binder, solvent, etc. to the raw material powder of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. to make a sludge, and by adopting the doctor blade method or calender roll method. A ceramic green sheet (ceramic green sheet) is formed, and thereafter, the ceramic green sheet is appropriately punched, and a plurality of the ceramic green sheets are laminated and fired at a temperature of about 1600 ° C.
【００１９】絶縁基体２の載置部２ａ周辺から外周縁に
かけては複数個のメタライズ配線層３・３が形成されて
おり、このメタライズ配線層３・３の載置部２ａ周辺部
には半導体素子６の各電極がボンディングワイヤ８・８
を介して電気的に接続され、一方、絶縁基体２の上面外
周縁に導出された部位には外部電気回路と接続される外
部リード端子４・４が銀ロウや金−シリコンロウ等のロ
ウ材を介してロウ付け取着されている。A plurality of metallized wiring layers 3 and 3 are formed from the periphery of the mounting portion 2a of the insulating base 2 to the outer peripheral edge thereof, and semiconductor elements are provided around the mounting portion 2a of the metallized wiring layers 3 and 3. Each electrode of 6 is a bonding wire 8/8
On the other hand, external lead terminals 4 and 4 connected to an external electric circuit are electrically connected to each other through a brazing material such as silver solder or gold-silicon solder. It is attached by brazing through.
【００２０】メタライズ配線層３・３は半導体素子６の
各電極を外部電気回路に接続する際の導電路として作用
し、タングステン・モリブデン・マンガン等の高融点金
属粉末の焼結体により形成されている。The metallized wiring layers 3 and 3 act as conductive paths when connecting the electrodes of the semiconductor element 6 to an external electric circuit, and are formed of a sintered body of a refractory metal powder such as tungsten, molybdenum or manganese. There is.
【００２１】このメタライズ配線層３・３は、タングス
テン・モリブデン・マンガン等の高融点金属粉末に適当
な有機バインダ・溶剤等を添加混合して得た金属ペース
トを絶縁基体２となるセラミックグリーンシートに予め
従来周知のスクリーン印刷法により所定パターンに印刷
塗布しておき、それらをビアホールによって接続してお
くことによって、絶縁基体２の載置部２ａ周辺から外周
縁にかけて形成される。For the metallized wiring layers 3 and 3, a metal paste obtained by adding and mixing an appropriate organic binder, a solvent and the like to a high melting point metal powder such as tungsten, molybdenum and manganese is used as a ceramic green sheet which becomes the insulating substrate 2. It is formed from the periphery of the mounting portion 2a of the insulating substrate 2 to the outer peripheral edge by printing and applying a predetermined pattern in advance by a conventionally known screen printing method and connecting them by via holes.
【００２２】また、メタライズ配線層３・３の露出表面
には、ニッケル・金等の耐蝕性に優れかつロウ材との濡
れ性に優れる金属を1.0 〜20μｍの厚みにメッキ法によ
り層着させておくと、メタライズ配線層３・３の酸化腐
食を有効に防止することができるとともに、メタライズ
配線層３・３への外部リード端子４・４のロウ付けを強
固となすことができて好ましい。On the exposed surface of the metallized wiring layers 3 and 3, a metal such as nickel and gold, which has excellent corrosion resistance and wettability with the brazing material, is applied by plating to a thickness of 1.0 to 20 μm. This is preferable because it is possible to effectively prevent oxidative corrosion of the metallized wiring layers 3 and 3 and to firmly braze the external lead terminals 4 and 4 to the metallized wiring layers 3 and 3.
【００２３】さらに、メタライズ配線層３・３には外部
リード端子４・４が銀ロウや金−シリコンロウ等のロウ
材を介してロウ付け取着されており、外部リード端子４
・４はパッケージ１内部の空所に収容する半導体素子６
の各電極を外部電気回路に電気的に接続する作用をなす
ので、外部リード端子４・４を外部電気回路に接続する
ことによって、半導体素子６はメタライズ配線層３・３
および外部リード端子４・４を介して外部電気回路に接
続されることとなる。Further, external lead terminals 4 and 4 are brazed and attached to the metallized wiring layers 3 and 3 via a brazing material such as silver brazing or gold-silicon brazing.
4 is a semiconductor element 6 housed in a void inside the package 1.
Since each of the electrodes has the function of electrically connecting to the external electric circuit, the semiconductor element 6 is connected to the metallized wiring layer 3.3 by connecting the external lead terminals 4 to the external electric circuit.
And it will be connected to an external electric circuit via the external lead terminals 4 and 4.
【００２４】外部リード端子４・４は鉄−ニッケル−コ
バルト合金や鉄−ニッケル合金等の金属材料から成り、
例えば、鉄−ニッケル−コバルト合金等の金属から成る
インゴット（塊）に圧延加工法や打ち抜き加工法等、従
来周知の金属加工法を採用することによって所定の形状
に形成される。The external lead terminals 4 and 4 are made of a metal material such as iron-nickel-cobalt alloy or iron-nickel alloy.
For example, an ingot (lump) made of a metal such as an iron-nickel-cobalt alloy is formed into a predetermined shape by adopting a conventionally known metal processing method such as a rolling processing method or a punching processing method.
【００２５】絶縁基体２の下面には、タングステンやモ
リブデン等の高融点金属から成るメタライズ層や絶縁基
体２と色調が異なる絶縁層によって、半導体装置の品番
や製造者名、あるいは半導体装置の方向性を示す識別標
識10が被着形成されており、この識別標識10は絶縁基体
２の色調とは異なる色調のものであるので目視やカメラ
等により容易に認識することができ、それによって半導
体装置の品番や製造者名、あるいは半導体装置の方向性
が容易に確認できるようになっている。On the lower surface of the insulating base 2, a metallized layer made of a refractory metal such as tungsten or molybdenum or an insulating layer having a color tone different from that of the insulating base 2 is used. The identification mark 10 that indicates is attached and formed. Since the identification mark 10 has a color tone different from that of the insulating substrate 2, the identification mark 10 can be easily recognized by visual inspection, a camera, or the like. The product number, the manufacturer's name, and the orientation of the semiconductor device can be easily confirmed.
【００２６】このような識別標識10は、例えば、タング
ステン等の高融点金属ペーストを絶縁基体２となるセラ
ミックグリーンシートに所定のパターン形状に印刷塗布
して焼成することよって、絶縁基体２の下面にその下面
から20〜50μｍ程度の高さとなる厚みで被着形成され
る。Such an identification mark 10 is formed on the lower surface of the insulating substrate 2 by, for example, printing and applying a high melting point metal paste such as tungsten on a ceramic green sheet to be the insulating substrate 2 in a predetermined pattern and firing. It is formed to have a thickness of about 20 to 50 μm from the lower surface thereof.
【００２７】本発明の半導体素子収納用パッケージ１
は、その絶縁基体２の下面の少なくとも載置部２ａに対
向する領域に、識別標識10の高さと同じもしくはそれ以
上の高さの平坦な被着層11が、識別標識10を露出させる
ようにして形成されていることが特徴であり、この被着
層11は、図１に示すように絶縁基体２の下面のほぼ全面
にわたって形成してもよい。また、載置部２ａへの熱伝
導効率を高めるために、載置部２ａに対向する領域なら
びにその周辺のみに形成してもよい。この被着層11は、
絶縁基体２の下面から表面までの高さが識別標識10の高
さと同じもしくはそれ以上で、かつその表面を実質的に
平坦に形成することが重要であり、それにより、上述し
た本発明に特有の作用効果を奏するものである。被着層
11の厚みは20〜100 μｍ程度とすることが、識別標識10
の高さの影響をなくすとともに、絶縁基体２への熱伝導
を効率良く行なえるという点で好ましい。Package 1 for storing semiconductor elements of the present invention
The flat coating layer 11 having a height equal to or higher than the height of the identification mark 10 exposes the identification mark 10 in at least a region of the lower surface of the insulating substrate 2 facing the mounting portion 2a. The coating layer 11 may be formed over substantially the entire lower surface of the insulating substrate 2 as shown in FIG. Further, in order to increase the heat conduction efficiency to the mounting portion 2a, it may be formed only in the region facing the mounting portion 2a and its periphery. This coating layer 11 is
It is important that the height from the lower surface to the surface of the insulating substrate 2 is equal to or higher than the height of the identification mark 10 and that the surface is formed substantially flat, which is characteristic of the present invention described above. It has the effect of. Deposition layer
The thickness of 11 should be about 20-100 μm.
This is preferable in that the influence of the height of the substrate can be eliminated and the heat conduction to the insulating substrate 2 can be efficiently performed.
【００２８】この被着層11は、例えば、絶縁基体２と実
質的に同一の材料から成る絶縁層やガラス・樹脂等で形
成すればよい。被着層を絶縁膜基体２と実質的に同一の
材料で形成した場合には、絶縁基体２との間に熱膨張係
数の相違に起因する割れや剥がれが発生することがなく
なるので、被着層11は絶縁基体２と実質的に同一の材料
で形成されることが好ましい。The adhered layer 11 may be formed of, for example, an insulating layer made of substantially the same material as the insulating substrate 2 or glass / resin. When the adherend layer is formed of the substantially same material as the insulating film base 2, cracking or peeling due to the difference in thermal expansion coefficient from the insulating base 2 does not occur, so that the adherend is adhered. Layer 11 is preferably formed of substantially the same material as insulating substrate 2.
【００２９】被着層11を形成するには、例えば、絶縁基
体２と実質的に同一の原料粉末に適当な有機バインダ・
溶剤等を添加混合して得た絶縁ペーストを絶縁基体２の
下面あるいは絶縁基体２の下面となるセラミックグリー
ンシートに印刷塗布して焼成することによって被着形成
される。この際、被着層11を識別標識10の近傍にも形成
する場合には、適当な印刷スクリーン等を用いて識別標
識を露出させるように形成する。なお、この被着層11と
識別標識10の形成順序は、パッケージ１の製造工程に応
じてどちらが先となってもよい。In order to form the adhered layer 11, for example, an organic binder, which is substantially the same as the insulating substrate 2 and is made of a suitable organic binder, is used.
The insulating paste obtained by adding and mixing a solvent or the like is applied to the lower surface of the insulating substrate 2 or a ceramic green sheet to be the lower surface of the insulating substrate 2 by printing and firing, and then adhered. At this time, when the adhesion layer 11 is also formed in the vicinity of the identification mark 10, it is formed so that the identification mark is exposed by using a suitable printing screen or the like. It should be noted that the order of forming the adhered layer 11 and the identification mark 10 may be either first depending on the manufacturing process of the package 1.
【００３０】被着層11は、絶縁基体２の下面の少なくと
も載置部２ａに対向する領域に形成されていれば本発明
に特有の作用効果を奏し得るが、絶縁基体２の下面の識
別標識10を除くほぼ全面に形成されていれば、絶縁基体
２とヒーターブロックの載置面との接触面積を十分に大
として極めて短時間に絶縁基体２を所定の温度にするこ
とができる。従って、被着層11は絶縁基体２の下面のほ
ぼ全面に形成されていることが好ましい。The adhered layer 11 can exhibit the function and effect peculiar to the present invention as long as it is formed on at least a region of the lower surface of the insulating base 2 facing the mounting portion 2a. If it is formed on almost the entire surface except for 10, the contact area between the insulating base 2 and the mounting surface of the heater block can be made sufficiently large to bring the insulating base 2 to a predetermined temperature in an extremely short time. Therefore, it is preferable that the deposition layer 11 is formed on almost the entire lower surface of the insulating substrate 2.
【００３１】かくして上述の半導体素子収納用パッケー
ジ１によれば、絶縁基体２の載置部２ａの底面に半導体
素子６を接着剤７を介して載置固定するとともに半導体
素子６の各電極をポンディングワイヤ８・８を介して所
定のメタライズ配線層３・３に接続させ、しかる後、絶
縁基体２の上面に蓋体５を封止材９を介してあるいは溶
接により接合させ、絶縁基体２と蓋体５とで形成される
空所に半導体素子６を気密に収容することによって、製
品としての半導体素子となる。Thus, according to the above-mentioned package 1 for accommodating semiconductor elements, the semiconductor element 6 is mounted and fixed on the bottom surface of the mounting portion 2a of the insulating substrate 2 with the adhesive 7, and each electrode of the semiconductor element 6 is pumped. The metallized wiring layers 3 and 3 are connected to each other via the bonding wires 8 and 8 and then the lid 5 is joined to the upper surface of the insulating substrate 2 through the sealing material 9 or by welding to form the insulating substrate 2. The semiconductor element 6 is hermetically housed in the space formed by the lid 5 to form a semiconductor element as a product.
【００３２】なお、本発明は上述の実施例に何ら限定さ
れるものではなく、本発明の要旨を逸脱しない範囲で種
々の変更・改良などを加えることは何ら差し支えない。The present invention is not limited to the above-described embodiments, and various modifications and improvements may be added without departing from the gist of the present invention.
【００３３】[0033]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、絶縁基体の下面の少なくとも半導体素子が載置
される載置部に対向する領域に、その下面に被着形成さ
れた識別標識の高さと同じもしくはそれ以上の高さを有
する平坦な被着層を、その識別標識が露出するように形
成したことから、載置部への半導体素子の接着固定の際
に絶縁基体の下面とヒーターブロックの載置面とを一様
に接触させることができて絶縁基体の加熱を良好かつ一
様に行なうことができる。そのため、絶縁基体の載置部
の温度が短時間で所定の温度となり、半導体素子を効率
良く接着固定することができる。According to the semiconductor element accommodating package of the present invention, the identification mark formed on the lower surface of the insulating substrate is formed at least in the area facing the mounting portion on which the semiconductor element is mounted. Since a flat adherend layer having a height equal to or higher than the height is formed so that its identification mark is exposed, the lower surface of the insulating substrate and the heater are fixed when the semiconductor element is bonded and fixed to the mounting portion. It is possible to make uniform contact with the mounting surface of the block, and to heat the insulating substrate satisfactorily and uniformly. Therefore, the temperature of the mounting portion of the insulating base reaches a predetermined temperature in a short time, and the semiconductor element can be efficiently bonded and fixed.
【００３４】特に、被着層を絶縁基体の下面のほぼ全面
にわたるように形成した場合には、絶縁基体とヒーター
ブロックとの接触に偏りがなくなって、絶縁基体が局部
的に加熱されることを防止することができ、それによ
り、絶縁基体中の急峻な温度勾配の形成による大きな熱
応力が発生して絶縁基体に割れやクラックが発生するこ
とを防止することができる。Particularly, when the adhered layer is formed so as to cover almost the entire lower surface of the insulating substrate, the contact between the insulating substrate and the heater block is not biased, and the insulating substrate is locally heated. It is possible to prevent the generation of a large thermal stress due to the formation of a steep temperature gradient in the insulating substrate, thereby preventing the insulating substrate from cracking or cracking.
【００３５】さらに、被着層は識別標識が露出するよう
に形成されているので、被着層を絶縁基体の下面のほぼ
全面にわたって形成した場合であっても、目視やカメラ
等により識別標識を容易に認識することができる。Further, since the adhered layer is formed so that the identification mark is exposed, even when the adhered layer is formed over almost the entire lower surface of the insulating substrate, the identification mark can be visually or by a camera or the like. Can be easily recognized.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.
【図２】従来の半導体素子収納用パッケージを示す断面
図である。FIG. 2 is a cross-sectional view illustrating a conventional semiconductor element storage package.
１・・・・・半導体素子収納用パッケージ ２・・・・・絶縁基体 ２ａ・・・・載置部 ３・・・・・メタライズ配線層 ４・・・・・外部リード端子 ５・・・・・蓋体 ６・・・・・半導体素子 10・・・・・識別標識 11・・・・・被着層 1 ... Package for housing semiconductor element 2 ... Insulating substrate 2a ... Mounting part 3 ... Metallized wiring layer 4 ... External lead terminal 5 ...・ Lid 6 ・ ・ ・ Semiconductor element 10 ・ ・ ・ Identification mark 11 ・ ・ ・ Adhesive layer
Claims (1)
有し、下面に識別標識が被着されている絶縁基体と、蓋
体とから成り、内部に半導体素子を収容するための空所
を有する半導体素子収納用パッケージであって、前記絶
縁基体の下面の少なくとも前記載置部に対向する領域
に、前記識別標識の高さと同じもしくはそれ以上の高さ
の平坦な被着層が、前記識別標識を露出させるようにし
て形成されていることを特徴とする半導体素子収納用パ
ッケージ。1. A housing, which has a mounting portion on which a semiconductor element is mounted and whose lower surface is provided with an identification mark, and a lid, for accommodating the semiconductor element therein. A package for storing a semiconductor element having a void, wherein a flat adherend layer having a height equal to or higher than the height of the identification mark is provided on at least a region of the lower surface of the insulating substrate facing the mounting portion. A package for accommodating a semiconductor device, wherein the identification mark is formed so as to be exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02697096A JP3297577B2 (en) | 1996-02-14 | 1996-02-14 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02697096A JP3297577B2 (en) | 1996-02-14 | 1996-02-14 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09223755A true JPH09223755A (en) | 1997-08-26 |
| JP3297577B2 JP3297577B2 (en) | 2002-07-02 |
Family
ID=12208023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02697096A Expired - Lifetime JP3297577B2 (en) | 1996-02-14 | 1996-02-14 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3297577B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7114239B2 (en) * | 2002-10-04 | 2006-10-03 | Neomax Co., Ltd. | Method for manufacturing a thin-film magnetic head wafer |
| JP2008187193A (en) * | 2008-03-21 | 2008-08-14 | Kyocera Corp | Wiring board |
-
1996
- 1996-02-14 JP JP02697096A patent/JP3297577B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7114239B2 (en) * | 2002-10-04 | 2006-10-03 | Neomax Co., Ltd. | Method for manufacturing a thin-film magnetic head wafer |
| US7474503B2 (en) | 2002-10-04 | 2009-01-06 | Hitachi Metals, Ltd. | Thin film magnetic head wafer with identification information |
| JP2008187193A (en) * | 2008-03-21 | 2008-08-14 | Kyocera Corp | Wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3297577B2 (en) | 2002-07-02 |
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