JP2746813B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP2746813B2 JP2746813B2 JP6372093A JP6372093A JP2746813B2 JP 2746813 B2 JP2746813 B2 JP 2746813B2 JP 6372093 A JP6372093 A JP 6372093A JP 6372093 A JP6372093 A JP 6372093A JP 2746813 B2 JP2746813 B2 JP 2746813B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- silicon
- package
- semiconductor element
- thermal expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
【０００１】[0001]
【産業上の利用分野】本発明は複数個の半導体素子を収
容する半導体素子収納用パッケージに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for accommodating a plurality of semiconductor elements.
【０００２】[0002]
【従来技術】近時、コンピュータ等の情報処理装置は高
性能化が急激に進み、該情報処理装置に実装される半導
体素子も高密度化、高集積化が進むとともにその使用個
数が多くなってきた。2. Description of the Related Art In recent years, the performance of information processing apparatuses such as computers has rapidly increased, and the number of semiconductor devices mounted on the information processing apparatuses has increased as the density and integration have increased. Was.
【０００３】そのため従来は1 個の半導体素子を1 つの
半導体素子収納用パッケージに収容するとともにこれを
回路配線基板に実装していたが近年では複数個の半導体
素子を1 つの半導体素子収納用パッケージに収容し、こ
れを回路配線基板に実装するようになってきた。Conventionally, one semiconductor element is housed in one semiconductor element housing package and mounted on a circuit wiring board. In recent years, however, a plurality of semiconductor elements are housed in one semiconductor element housing package. It is housed and mounted on a circuit wiring board.
【０００４】かかる複数個の半導体素子を収容する半導
体素子収納用パッケージは通常、酸化アルミニウム質焼
結体から成り、その上面略中央部に複数個の半導体素子
を収容するための空所を形成する凹部及び該凹部周辺か
ら外周縁にかけて導出されたタングステン、モリブデ
ン、マンガン等の高融点金属粉末から成る複数個のメタ
ライズ配線層を有する絶縁基体と、各半導体素子を外部
電気回路に電気的に接続するために前記メタライズ配線
層に銀ロウ等のロウ材を介し取着された外部リード端子
と、蓋体とから構成されており、絶縁基体の凹部底面に
複数個の半導体素子が搭載されたシリコン配線基板をガ
ラス、樹脂、ロウ材等の接着剤を介して接着固定すると
ともに各半導体素子の電極をボンディングワイヤを介し
てメタライズ配線層に接続し、しかる後、絶縁基体と蓋
体とをガラス、樹脂、ロウ材等から成る封止材で接合さ
せ、絶縁基体と蓋体とから成る容器内部に複数個の半導
体素子を気密に収容することによって製品としての半導
体装置となる。A package for accommodating a plurality of semiconductor elements is usually made of an aluminum oxide sintered body, and a space for accommodating the plurality of semiconductor elements is formed substantially at the center of the upper surface thereof. An insulating base having a plurality of metallized wiring layers made of a high melting point metal powder such as tungsten, molybdenum, and manganese, which is led out from the periphery of the recess to the outer peripheral edge; and electrically connecting each semiconductor element to an external electric circuit. An external lead terminal attached to the metallized wiring layer via a brazing material such as silver brazing, and a lid, and a silicon wiring in which a plurality of semiconductor elements are mounted on the bottom surface of the concave portion of the insulating base. The substrate is bonded and fixed via an adhesive such as glass, resin, brazing material and the like, and the electrodes of each semiconductor element are metallized wiring layers via bonding wires. After connection, the insulating base and the lid are joined with a sealing material made of glass, resin, brazing material or the like, and a plurality of semiconductor elements are hermetically accommodated in a container formed of the insulating base and the lid. Thus, a semiconductor device as a product is obtained.
【０００５】尚、上述の半導体装置は半導体素子収納用
パッケージの内部に複数個の半導体素子を収容する際、
その収容の作業性を向上させるために、また内部に収容
する半導体素子同志を電気的に接続するために予め半導
体素子と熱膨張係数が同じシリコンから成る基板の表面
に銅から成る配線導体とポリイミド樹脂から成る絶縁膜
を多層に積層したシリコン配線基板を準備し、このシリ
コン配線基板に複数個の半導体素子を搭載するとともに
該半導体素子の各電極と配線導体とを電気的に接続し、
しかる後、前記複数個の半導体素子が搭載されたシリコ
ン配線基板をパッケージの絶縁基体と蓋体から成る容器
内部に収容するようになっている。In the above-described semiconductor device, when a plurality of semiconductor elements are housed in a semiconductor element housing package,
In order to improve the workability of the housing and to electrically connect the semiconductor elements housed therein, a wiring conductor made of copper and a polyimide are formed on the surface of a substrate made of silicon having the same thermal expansion coefficient as that of the semiconductor element in advance. Preparing a silicon wiring board in which an insulating film made of resin is laminated in multiple layers, mounting a plurality of semiconductor elements on the silicon wiring board, and electrically connecting each electrode of the semiconductor element and a wiring conductor,
Thereafter, the silicon wiring board on which the plurality of semiconductor elements are mounted is housed in a container including an insulating base and a lid of a package.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージは絶縁基体が酸化アル
ミニウム質焼結体から成り、その上面略中央部に形成し
た凹部内に複数個の半導体素子を搭載した広面積のシリ
コン配線基板を接着固定した場合、以下に述べる欠点を
有したものとなる。However, in this conventional package for housing a semiconductor element, the insulating base is made of an aluminum oxide sintered body, and a plurality of semiconductor elements are mounted in a recess formed substantially at the center of the upper surface thereof. When a large-area silicon wiring substrate is bonded and fixed, it has the following disadvantages.
【０００７】即ち、パッケージの絶縁基体を構成する酸
化アルミニウム質焼結体とシリコン配線基板のシリコン
の熱膨張係数がそれぞれ6.5 〜7.5 ×10-6/ ℃、3.0 〜
3.5×10-6/ ℃であり、大きく相違することから両者に
半導体素子を作動させた際等に発生する熱が印加される
と両者間に大きな熱応力が発生し、該熱応力によってシ
リコン配線基板に破損を生じたり、シリコン配線基板が
絶縁基体より剥離して半導体装置としての機能が喪失し
てしまうという欠点を有していた。That is, the thermal expansion coefficients of the aluminum oxide sintered body constituting the insulating base of the package and the silicon of the silicon wiring board are 6.5 to 7.5 × 10 -6 / ° C.
3.5 × 10 −6 / ° C., which is so different that when heat generated when the semiconductor element is operated is applied to both, a large thermal stress is generated between the two, and the thermal stress causes a silicon wiring. There has been a drawback that the substrate is damaged or the silicon wiring substrate is peeled off from the insulating base and the function as a semiconductor device is lost.
【０００８】[0008]
【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は複数個の半導体素子が搭載されたシリコ
ン配線基板を破損の発生を皆無として絶縁基体に強固に
接着固定し、半導体素子を長期間にわたり正常、且つ安
定に作動させることができる半導体素子収納用パッケー
ジを提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to firmly adhere and fix a silicon wiring board on which a plurality of semiconductor elements are mounted to an insulating substrate without any breakage. An object of the present invention is to provide a package for housing a semiconductor element, which allows a semiconductor element to operate normally and stably for a long period of time.
【０００９】[0009]
【課題を解決するための手段】本発明は複数個の半導体
素子を搭載させたシリコン配線基板が接着固定される絶
縁基体と蓋体とから成り、内部に複数個の半導体素子が
搭載されたシリコン配線基板を気密に収容するようにな
した半導体素子収納用パッケージであって、前記絶縁基
体表面のシリコン配線基板が接着固定される領域に、熱
膨張係数を絶縁基体の熱膨張係数とシリコン配線基板の
熱膨張係数の間とした中間部材を配したことを特徴とす
るものである。SUMMARY OF THE INVENTION The present invention comprises a silicon substrate having a plurality of semiconductor elements mounted thereon, and an insulating substrate to which the silicon wiring board is adhered and fixed, and a lid, wherein a plurality of semiconductor elements are mounted inside. A semiconductor element housing package adapted to hermetically house a wiring substrate, wherein a thermal expansion coefficient is set in a region of the surface of the insulating substrate to which the silicon wiring substrate is adhered and fixed. Wherein an intermediate member having a coefficient of thermal expansion between the intermediate members is disposed.
【００１０】[0010]
【作用】本発明の半導体素子収納用パッケージによれ
ば、絶縁基体表面のシリコン配線基板が接着固定される
領域に、熱膨張係数が絶縁基体の熱膨張係数とシリコン
配線基板の熱膨張係数の間にある中間部材を配したこと
から絶縁基体と中間部材との間及び中間部材とシリコン
配線基板との間に大きな熱応力が発生することはなく、
その結果、絶縁基体とシリコン配線基板との間に発生す
る熱応力は中間部材で実質的に緩和され、シリコン配線
基板に破損が発生するのを有効に防止することができる
とともにシリコン配線基板を絶縁基体に強固に接着固定
することが可能となり、これによって半導体素子を長期
間にわたり正常、且つ安定に作動させることができる。According to the package for housing a semiconductor element of the present invention, the thermal expansion coefficient between the thermal expansion coefficient of the insulating substrate and the thermal expansion coefficient of the silicon wiring substrate is set in the area of the insulating substrate surface where the silicon wiring substrate is bonded and fixed. No large thermal stress is generated between the insulating base and the intermediate member and between the intermediate member and the silicon wiring board because the intermediate member is disposed in
As a result, the thermal stress generated between the insulating base and the silicon wiring board is substantially alleviated by the intermediate member, so that it is possible to effectively prevent the silicon wiring board from being damaged and to insulate the silicon wiring board. The semiconductor element can be firmly bonded and fixed to the base, so that the semiconductor element can be operated normally and stably for a long period of time.
【００１１】[0011]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1 は本発明の半導体素子収納用パッケージの一実
施例を示し、1 は絶縁基体、2 は蓋体である。この絶縁
基体1 と蓋体2 とで複数個の半導体素子3 が搭載されて
いるシリコン配線基板5 を収容する容器4 が構成され
る。BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of a package for housing a semiconductor element according to the present invention, wherein 1 is an insulating base, and 2 is a lid. The insulating base 1 and the lid 2 constitute a container 4 for accommodating a silicon wiring substrate 5 on which a plurality of semiconductor elements 3 are mounted.
【００１２】前記絶縁基体1 はその上面中央部に複数個
の半導体素子3 が搭載されたシリコン配線基板5 を収容
するための空所を形成する凹部1aが設けてあり、該凹部
1a底面にはシリコン配線基板5 がガラス、樹脂等の接着
剤を介して接着固定される。The insulating substrate 1 has a recess 1a in the center of the upper surface thereof for forming a space for accommodating a silicon wiring board 5 on which a plurality of semiconductor elements 3 are mounted.
A silicon wiring substrate 5 is adhered and fixed to the bottom surface of the substrate 1a via an adhesive such as glass or resin.
【００１３】前記絶縁基体1 の凹部1a内に収容されるシ
リコン配線基板5 は、シリコン基板5a上に銅(Cu)から成
る配線導体5bとポリイミド樹脂から成る絶縁膜5cを薄膜
形成技術を採用し多層に積層させた構造を有しており、
配線導体5bには各半導体素子3 の電極が電気的に接続さ
れ、該配線導体5bによって各半導体素子3 の所定電極が
電気的に接続されるようになっている。The silicon wiring board 5 housed in the concave portion 1a of the insulating base 1 employs a thin film forming technique in which a wiring conductor 5b made of copper (Cu) and an insulating film 5c made of a polyimide resin are formed on the silicon substrate 5a. Has a multilayered structure,
The electrode of each semiconductor element 3 is electrically connected to the wiring conductor 5b, and the predetermined electrode of each semiconductor element 3 is electrically connected by the wiring conductor 5b.
【００１４】また前記シリコン配線基板5 はシリコン基
板5aが半導体素子3 と同質の材料で形成されていること
からシリコン配線基板5 に半導体素子3 を搭載させた
後、両者に熱が印加されても両者間には熱膨張係数の相
違に起因する大きな熱応力が発生することはなく、半導
体素子3 をシリコン配線基板5 に強固に搭載させておく
ことが可能となっている。Since the silicon substrate 5a is formed of the same material as that of the semiconductor element 3, the silicon wiring substrate 5 is not affected by heat applied to both after the semiconductor element 3 is mounted on the silicon wiring substrate 5. A large thermal stress due to the difference in thermal expansion coefficient does not occur between the two, and the semiconductor element 3 can be firmly mounted on the silicon wiring board 5.
【００１５】前記複数個の半導体素子3 が搭載されたシ
リコン配線基板5 を収容する空所を有する絶縁基体1 は
例えば、酸化アルミニウム質焼結体から成り、酸化アル
ミニウム(Al 2 O 3 ) 、酸化珪素(SiO2 ) 、酸化カルシ
ウム(CaO) 、酸化マグネシウム(MgO) 等の原料粉末に適
当な有機溶剤、溶媒を添加混合して泥漿状となすととも
にこれを従来周知のドクターブレード法やカレンダーロ
ール法を採用することによってセラミックグリーンシー
ト( セラミック生シート) に成形し、しかる後、前記セ
ラミックグリーンシートに適当な打ち抜き加工を施すと
ともに複数枚積層し、高温( 約1600℃) で焼成すること
によって製作される。The insulating base 1 having a space for accommodating the silicon wiring board 5 on which the plurality of semiconductor elements 3 are mounted is made of, for example, a sintered body of aluminum oxide, aluminum oxide (Al 2 O 3 ), A raw material powder such as silicon (SiO 2 ), calcium oxide (CaO), and magnesium oxide (MgO) is mixed with an appropriate organic solvent and a solvent to form a slurry, and the mixture is formed into a slurry by a well-known doctor blade method or calender roll method. It is manufactured by forming into a ceramic green sheet (ceramic green sheet) by applying a suitable punching process to the ceramic green sheet, laminating a plurality of sheets, and firing at a high temperature (about 1600 ° C.). You.
【００１６】前記絶縁基体1 はまたシリコン配線基板5
が接着固定される領域に、熱膨張係数を絶縁基体1 の熱
膨張係数とシリコン配線基板5 の熱膨張係数の間とした
中間部材6 が配されている。The insulating substrate 1 also comprises a silicon wiring substrate 5
An intermediate member 6 having a coefficient of thermal expansion between the coefficient of thermal expansion of the insulating base 1 and the coefficient of thermal expansion of the silicon wiring board 5 is disposed in a region where the substrate is bonded and fixed.
【００１７】前記中間部材6 は絶縁基体1 にシリコン配
線基板5 を接着固定した後、絶縁基体1 とシリコン配線
基板5 の両者に熱が印加された場合に発生する絶縁基体
1 とシリコン配線基板5 の熱膨張係数の相違に起因する
大きな熱応力を緩和する作用を為し、これによってシリ
コン配線基板5 は破損を発生することなく絶縁基体1に
強固に接着固定され、半導体素子3 を長期間にわたり正
常、且つ安定に作動させることができる。The intermediate member 6 is an insulating substrate that is generated when heat is applied to both the insulating substrate 1 and the silicon wiring substrate 5 after the silicon wiring substrate 5 is bonded and fixed to the insulating substrate 1.
1 and the silicon wiring board 5 to relieve a large thermal stress caused by a difference in thermal expansion coefficient between the silicon wiring board 5 and the silicon wiring board 5. The element 3 can be operated normally and stably for a long period of time.
【００１８】尚、前記中間部材6 による熱応力の緩和
は、中間部材6 の熱膨張係数が絶縁基体1 の熱膨張係数
とシリコン配線基板5 の熱膨張係数の間にあるため絶縁
基体1にシリコン配線基板5 を間に中間部材6 を挟んで
接着固定すれば絶縁基体1 と中間部材6 との間及び中間
部材6 とシリコン配線基板5 との間に大きな熱応力が発
生しないことによる。The thermal stress is reduced by the intermediate member 6 because the thermal expansion coefficient of the intermediate member 6 is between the thermal expansion coefficient of the insulating base 1 and the silicon substrate 5. If the wiring substrate 5 is bonded and fixed with the intermediate member 6 interposed therebetween, no large thermal stress is generated between the insulating base 1 and the intermediate member 6 and between the intermediate member 6 and the silicon wiring substrate 5.
【００１９】また前記中間部材6 は絶縁基体1 が酸化ア
ルミニウム質焼結体から成る場合、絶縁基体1 の熱膨張
係数(6.5〜7.5 ×10-6/ ℃) とシリコン配線基板5 の熱
膨張係数(3.0〜3.5 ×10-6/ ℃) との間の熱膨張係数を
有する窒化アルミニウム質焼結体( 熱膨張係数:5.0×10
-6/ ℃) 、炭化珪素質焼結体( 熱膨張係数:3.0〜4.0×1
0-6/ ℃) 、ムライト質焼結体( 熱膨張係数:4.0〜5.0
×10-6/ ℃) 等から成り、例えば窒化アルミニウム質焼
結体から成る場合は主原料としての窒化アルミニウム(A
lN) に焼結助剤としてのイットリア(Y2 O 3 ) 、カルシ
ア(CaO) 、マグネシア(MgO) と適当な有機溶剤、溶媒を
添加混合して泥漿状となし、次に前記泥漿物を従来周知
のドクターブレード法やカレンダーロール法を採用する
ことによってセラミックグリーンシート( セラミック生
シート) に成形し、しかる後、前記セラミックグリーン
シートに適当な打ち抜き加工を施すとともに複数枚積層
し、高温( 約1800℃) で焼成することによって製作され
る。When the insulating substrate 1 is made of an aluminum oxide sintered body, the thermal expansion coefficient of the insulating substrate 1 (6.5 to 7.5 × 10 −6 / ° C.) and the thermal expansion coefficient of the silicon wiring substrate 5 (3.0-3.5 × 10 −6 / ° C.) and an aluminum nitride-based sintered body having a coefficient of thermal expansion between (thermal expansion coefficient: 5.0 × 10
-6 / ° C), silicon carbide sintered body (coefficient of thermal expansion: 3.0-4.0 × 1
0 -6 / ° C), mullite sintered body (coefficient of thermal expansion: 4.0 to 5.0
× 10 -6 /°C).For example, when the sintered body is made of aluminum nitride, aluminum nitride (A
lN) and yttria (Y 2 O 3 ), calcia (CaO), and magnesia (MgO) as sintering aids, and an appropriate organic solvent and solvent, and mix to form a slurry. It is formed into a ceramic green sheet (ceramic green sheet) by employing a well-known doctor blade method or a calendar roll method, and thereafter, the ceramic green sheet is subjected to an appropriate punching process, and a plurality of sheets are laminated, and a high temperature (about 1800 (° C).
【００２０】更に前記絶縁基体1 には凹部1a周辺から外
周縁にかけて複数個のメタライズ配線層7 が被着形成さ
れており、該メタライズ配線層7 の凹部1a周辺部には半
導体素子3 の電極が接続されているシリコン配線基板5
の配線導体5bがボンディングワイヤ8 を介して電気的に
接続され、また絶縁基体1 の外周縁に導出する部位には
外部リード端子9 が銀ロウ等のロウ材を介してロウ付け
されている。Further, a plurality of metallized wiring layers 7 are formed on the insulating substrate 1 from the periphery of the concave portion 1a to the outer peripheral edge, and the electrodes of the semiconductor element 3 are formed around the concave portion 1a of the metallized wiring layer 7. Silicon wiring board 5 connected
The wiring lead 5b is electrically connected via a bonding wire 8, and an external lead terminal 9 is brazed to a portion extending to the outer peripheral edge of the insulating base 1 via a brazing material such as silver brazing.
【００２１】前記絶縁基体1 に設けたメタライズ配線層
7 は外部電気回路に接続される外部リード端子9 に各半
導体素子3 の電極を電気的に導通させる作用を為し、タ
ングステン、モリブデン、マンガン等の金属粉末で形成
されている。Metallized wiring layer provided on the insulating substrate 1
Numeral 7 serves to electrically connect the electrodes of the respective semiconductor elements 3 to the external lead terminals 9 connected to the external electric circuit, and is formed of a metal powder such as tungsten, molybdenum, manganese or the like.
【００２２】尚、前記メタライズ配線層7 は例えば、タ
ングステン等の金属粉末に有機溶剤、溶媒を添加混合し
て得た金属ペーストを絶縁基体1 となるセラミックグリ
ーンシートに予め従来周知のスクリーン印刷法により所
定パターンに印刷塗布しておくことによって絶縁基体1
の凹部1a周辺から外周縁にかけて被着形成される。The metallized wiring layer 7 is formed, for example, by applying a metal paste obtained by adding an organic solvent and a solvent to a metal powder such as tungsten on a ceramic green sheet serving as the insulating substrate 1 in advance by a conventionally known screen printing method. Insulating substrate 1 by printing and applying in a predetermined pattern
From the periphery of the concave portion 1a to the outer peripheral edge.
【００２３】また前記メタライズ配線層7 はその露出す
る外表面にニッケル、金等の耐蝕性に優れ、且つロウ材
と濡れ性の良い金属をメッキ法により1.0 乃至20.0μm
の厚みに層着させておくとメタライズ配線層7 の酸化腐
食を有効に防止することができるとともにメタライズ配
線層7 と外部リード端子9 とのロウ付けを強固なものと
なすことができる。従って、前記メタライズ配線層7 の
表面にはニッケル、金等の耐蝕性に優れ、且つロウ材と
濡れ性の良い金属をメッキ法により1.0 乃至20.0μm の
厚みに層着させておくことが好ましい。The metallized wiring layer 7 is coated on its exposed outer surface with a metal having excellent corrosion resistance such as nickel and gold and a good wettability with a brazing material by 1.0 to 20.0 μm by plating.
When the metallized wiring layer 7 is layered to a thickness of not less than 1, the oxidation corrosion of the metallized wiring layer 7 can be effectively prevented, and the brazing between the metallized wiring layer 7 and the external lead terminals 9 can be made firm. Therefore, it is preferable that a metal having excellent corrosion resistance, such as nickel or gold, and a good wettability with a brazing material is applied to the surface of the metallized wiring layer 7 by plating to a thickness of 1.0 to 20.0 μm.
【００２４】更に前記メタライズ配線層7 にロウ付けさ
れる外部リード端子9 はコバール金属( 鉄ーニッケルー
コバルト合金) や42アロイ( 鉄ーニッケル合金) 等の金
属材料から成り、各半導体素子3 の電極を外部電気回路
に電気的に接続する作用を為す。The external lead terminals 9 brazed to the metallized wiring layer 7 are made of a metal material such as Kovar metal (iron-nickel-cobalt alloy) or 42 alloy (iron-nickel alloy). To an external electric circuit.
【００２５】前記外部リード端子9 はコバール金属等の
インゴット( 塊) を圧延加工法や打ち抜き加工法等、従
来周知の金属加工法を採用し、所定の板状に形成するこ
とによって製作される。The external lead terminal 9 is manufactured by forming an ingot (lumps) of Kovar metal or the like into a predetermined plate shape by employing a conventionally known metal working method such as a rolling method or a punching method.
【００２６】かくして上述の半導体素子収納用パッケー
ジによれば、絶縁基体1 の凹部1a底面に、複数個の半導
体素子3 が搭載されたシリコン配線基板5 を間に中間部
材6を挟んでガラス、樹脂、ロウ材等の接着材により接
着固定するとともに該半導体素子3 の各電極が接続され
ているシリコン配線基板5 の配線導体5bをボンディング
ワイヤ8 を介してメタライズ配線層7 に電気的に接続
し、しかる後、絶縁基体1 の上面に蓋体2 をガラス、樹
脂、ロウ材等から成る封止材を介して接合させ、絶縁基
体1 と蓋体2 とからなる容器4 内部に複数個の半導体素
子3 が搭載されたシリコン配線基板5 を気密に封止する
ことによって製品としての半導体装置が完成する。Thus, according to the package for housing a semiconductor element described above, glass or resin is interposed between the silicon wiring board 5 on which the plurality of semiconductor elements 3 are mounted and the intermediate member 6 interposed therebetween on the bottom surface of the concave portion 1a of the insulating base 1. The wiring conductor 5b of the silicon wiring board 5 to which each electrode of the semiconductor element 3 is connected is electrically connected to the metallized wiring layer 7 through the bonding wire 8 while being fixed by an adhesive such as a brazing material. Thereafter, the lid 2 is bonded to the upper surface of the insulating base 1 via a sealing material made of glass, resin, brazing material, or the like, and a plurality of semiconductor elements are placed inside the container 4 including the insulating base 1 and the lid 2. The semiconductor device as a product is completed by hermetically sealing the silicon wiring substrate 5 on which the semiconductor device 3 is mounted.
【００２７】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.
【００２８】[0028]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、絶縁基体表面のシリコン配線基板が接着固定さ
れる領域に、熱膨張係数が絶縁基体の熱膨張係数とシリ
コン配線基板の熱膨張係数の間にある中間部材を配した
ことから絶縁基体と中間部材との間及び中間部材とシリ
コン配線基板との間に大きな熱応力が発生することはな
く、その結果、絶縁基体とシリコン配線基板との間に発
生する熱応力は中間部材で実質的に緩和され、シリコン
配線基板に破損が発生するのを有効に防止することがで
きるとともにシリコン配線基板を絶縁基体に強固に接着
固定することが可能となり、これによって半導体素子を
長期間にわたり正常、且つ安定に作動させることができ
る。According to the package for housing a semiconductor element of the present invention, the thermal expansion coefficients of the insulating substrate and the silicon wiring substrate are in the area where the silicon wiring substrate is adhered and fixed on the surface of the insulating substrate. Since the intermediate member between them is arranged, no large thermal stress is generated between the insulating base and the intermediate member and between the intermediate member and the silicon wiring substrate. The thermal stress generated during the process is substantially reduced by the intermediate member, which can effectively prevent the silicon wiring substrate from being damaged and can firmly adhere and fix the silicon wiring substrate to the insulating base. Thus, the semiconductor element can be normally and stably operated for a long period of time.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.
１・・・・・・絶縁基体 １ａ・・・・・凹部 ２・・・・・・蓋体 ３・・・・・・半導体素子 ４・・・・・・容器 ５・・・・・・シリコン配線基板 ６・・・・・・中間部材 DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Depression 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... Silicon Wiring board 6 Intermediate member
Claims (2)
に、上面に複数個の半導体素子が搭載されているシリコ
ン配線基板の下面を接着固定することによって内部に複
数個の半導体素子が搭載されたシリコン配線基板を気密
に収容するようになした半導体素子収納用パッケージで
あって、前記絶縁基体上面とシリコン配線基板下面との
間に、熱膨張係数が絶縁基体の熱膨張係数とシリコン配
線基板の熱膨張係数の間の値を示す中間部材を配したこ
とを特徴とする半導体素子収納用パッケージ。An upper surface of an insulating substrate, comprising an insulating substrate and a lid.
Has a plurality of semiconductor elements mounted on the top
A semiconductor device package for housing without to accommodate hermetically the silicon wiring substrate in which a plurality of semiconductor elements are mounted inside by bonding and fixing the lower surface of the emissions wiring board, the insulating base upper surface and the silicon wiring With the bottom surface of the substrate
A package for housing a semiconductor element, wherein an intermediate member having a thermal expansion coefficient between the thermal expansion coefficient of the insulating substrate and the thermal expansion coefficient of the silicon wiring board is disposed therebetween.
から成り、且つ中間部材が窒化アルミニウム質焼結体、
炭化珪素質焼結体、ムライト質焼結体の少なくとも１種
から成ることを特徴とする請求項１に記載の半導体素子
収納用パッケージ。2. The method according to claim 1, wherein the insulating base is made of an aluminum oxide sintered body, and the intermediate member is an aluminum nitride sintered body.
2. The package for accommodating a semiconductor element according to claim 1, comprising at least one of a silicon carbide-based sintered body and a mullite-based sintered body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6372093A JP2746813B2 (en) | 1993-03-23 | 1993-03-23 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6372093A JP2746813B2 (en) | 1993-03-23 | 1993-03-23 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06275737A JPH06275737A (en) | 1994-09-30 |
| JP2746813B2 true JP2746813B2 (en) | 1998-05-06 |
Family
ID=13237517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6372093A Expired - Fee Related JP2746813B2 (en) | 1993-03-23 | 1993-03-23 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2746813B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5904556B2 (en) * | 2010-03-03 | 2016-04-13 | ジョージア テック リサーチ コーポレイション | Through-package via (TPV) structure on inorganic interposer and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6323342A (en) * | 1985-05-24 | 1988-01-30 | Matsushita Electric Works Ltd | High heat conductive substrate |
| JPH0364060A (en) * | 1989-08-02 | 1991-03-19 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
-
1993
- 1993-03-23 JP JP6372093A patent/JP2746813B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06275737A (en) | 1994-09-30 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |