JPH0855804A - Method of manufacturing semiconductor film - Google Patents
Method of manufacturing semiconductor filmInfo
- Publication number
- JPH0855804A JPH0855804A JP18804394A JP18804394A JPH0855804A JP H0855804 A JPH0855804 A JP H0855804A JP 18804394 A JP18804394 A JP 18804394A JP 18804394 A JP18804394 A JP 18804394A JP H0855804 A JPH0855804 A JP H0855804A
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- JP
- Japan
- Prior art keywords
- film
- thin film
- semiconductor thin
- semiconductor
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体薄膜の製造方
法に係り、特に薄膜トランジスタ（以下、ＴＦＴと称す
る。）等の活性層に有用な半導体薄膜の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor thin film, and more particularly to a method for manufacturing a semiconductor thin film useful for an active layer such as a thin film transistor (hereinafter referred to as TFT).
【０００２】[0002]
【従来の技術】従来、半導体薄膜をはじめ、各種薄膜の
堆積にＣＶＤ（Chemical Vapor Diposition ）装置が用
いられている。ＣＶＤ装置には、原料ガスの活性化に、
熱を用いるもの、光を用いるもの、プラズマ反応を用い
るもの、更にはサイクロトロン共鳴を用いるもの等が知
られている。中でも、プラズマＣＶＤ装置は、均質で、
比較的生産性良く薄膜の堆積が可能であることから、各
種分野で利用されている。2. Description of the Related Art Conventionally, a CVD (Chemical Vapor Diposition) apparatus has been used for depositing various thin films including a semiconductor thin film. In the CVD device, to activate the source gas,
Those using heat, those using light, those using plasma reaction, and those using cyclotron resonance are known. Above all, the plasma CVD device is homogeneous and
Since it is possible to deposit a thin film with relatively high productivity, it is used in various fields.
【０００３】このようなプラズマＣＶＤ装置には、プラ
ズマ反応により活性化された原料ガスを反応炉内に導き
基板上に堆積させるもの、あるいは原料ガスを反応炉内
で活性化して基板上に堆積させるもの等、種々の構成が
あるが、いずれにしても基板上のみならず、反応炉内壁
等にも同様の薄膜が堆積される。この反応炉内壁や電極
板に付着した膜が厚くなると、膜が剥離することにより
パーティクルが発生し、製品の歩留まりを低下させる要
因となっている。In such a plasma CVD apparatus, a raw material gas activated by a plasma reaction is introduced into a reaction furnace to be deposited on a substrate, or a raw material gas is activated in the reaction furnace to be deposited on a substrate. Although there are various configurations such as those described above, in any case, similar thin films are deposited not only on the substrate but also on the inner wall of the reaction furnace and the like. When the film attached to the inner wall of the reaction furnace or the electrode plate becomes thick, the film is peeled off to generate particles, which is a factor of reducing the yield of products.
【０００４】[0004]
【発明が解決しようとする課題】このようなことから、
反応炉内壁等に堆積される不要被膜の膜厚の程度に応じ
て、反応炉内の防着板や電極板等を交換・清浄する、あ
るいは四沸化炭素（ＣＦ4 ），三沸化窒素（ＮＦ3 ）等
のフッ素系クリーニングガスとアルゴン（Ａｒ）等のキ
ャリアガスとを反応炉内に導入し、プラズマを発生させ
て反応炉内壁に堆積される不要膜を除去することが知ら
れている。また、更に、反応炉内を清浄にした後、実際
の成膜前に、基板を配置することなく、反応炉内壁に窒
化被膜あるいは実際に成膜すると同一の半導体被膜を堆
積させる、いわゆるプリコート工程を経ることにより、
反応炉内の不純物を排気除去すると共に、反応炉内壁か
らの不純物が実際の成膜に悪影響を及ぼすことを防止す
る技術が、例えば特開昭６３−２１５０３７号、特開昭
６３−２６７４３０号等で知られている。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Depending on the thickness of the unnecessary film deposited on the inner wall of the reaction furnace, the deposition prevention plate and electrode plate in the reaction furnace are replaced and cleaned, or carbon tetrafluoride (CF 4 ) and nitrogen trifluoride are cleaned. It is known that a fluorine-based cleaning gas such as (NF 3 ) and a carrier gas such as argon (Ar) are introduced into a reaction furnace to generate plasma to remove an unnecessary film deposited on the inner wall of the reaction furnace. There is. Further, a so-called pre-coating step of depositing a nitride film or the same semiconductor film when actually formed on the inner wall of the reaction furnace without arranging a substrate after cleaning the inside of the reaction furnace and before actual film formation By going through
A technique for exhausting and removing impurities in the reaction furnace and preventing the impurities from the inner wall of the reaction furnace from adversely affecting the actual film formation is disclosed in, for example, JP-A-63-215037 and JP-A-63-267430. Is known for.
【０００５】しかしながら、窒化被膜によるプリコート
工程を経ても、初期に成膜される半導体薄膜の移動度
が、それ以降に成膜される半導体薄膜に比べて低く、成
膜された半導体薄膜を活性層として用いたＴＦＴにあっ
ては、しきい値電圧が所望の範囲内に制御されないとい
った問題点があった。また、半導体皮膜では、このプリ
コートによりパーティクルが増大するという問題点があ
った。However, even after the precoating step with the nitride film, the mobility of the semiconductor thin film initially formed is lower than that of the semiconductor thin films formed thereafter, and the formed semiconductor thin film is used as the active layer. The TFT used as the above has a problem that the threshold voltage is not controlled within a desired range. Further, in the semiconductor film, there is a problem that particles increase due to this precoat.
【０００６】この発明は、上記した技術課題に鑑み成さ
れたものであって、製造ばらつきが抑えられ、製造歩留
り良く製造することが可能な半導体薄膜の製造方法を提
供することを目的としている。The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a method for manufacturing a semiconductor thin film, which can suppress manufacturing variations and can be manufactured with a high manufacturing yield.
【０００７】[0007]
【課題を解決するための手段】請求項１に記載される発
明は、シリコン（Ｓｉ）を含む活性化された原料ガスに
基づいて反応炉内で基板上に半導体薄膜を堆積させる半
導体薄膜の製造方法において、前記半導体薄膜を堆積さ
せる前に、前記反応炉内をフッ素（Ｆ）を含むクリーニ
ング・ガスで清浄する清浄工程と、前記反応炉内に少な
くとも前記シリコン（Ｓｉ）を含む半導体被膜と，前記
半導体被膜上に窒化被膜もしくは窒素含有酸化被膜を積
層して堆積させる堆積工程とを具備したことを特徴とし
たものである。According to a first aspect of the present invention, a semiconductor thin film is produced by depositing a semiconductor thin film on a substrate in a reaction furnace based on an activated source gas containing silicon (Si). In the method, a cleaning step of cleaning the inside of the reaction furnace with a cleaning gas containing fluorine (F) before depositing the semiconductor thin film, and a semiconductor film containing at least the silicon (Si) in the reaction furnace, A deposition step of stacking and depositing a nitride coating or a nitrogen-containing oxide coating on the semiconductor coating.
【０００８】請求項２に記載される発明は、請求項１記
載の半導体薄膜の製造方法において、前記半導体被膜が
２００〜１０００オングストロームの膜厚を有すること
を特徴としている。The invention described in claim 2 is the method for manufacturing a semiconductor thin film according to claim 1, wherein the semiconductor film has a film thickness of 200 to 1000 angstroms.
【０００９】請求項３に記載される発明は、請求項１記
載の半導体薄膜の製造方法において、前記窒化被膜もし
くは窒素含有酸化被膜が５０〜１０００オングストロー
ムの膜厚を有することを特徴としている。請求項４に記
載される発明は、請求項１記載の半導体薄膜の製造方法
において、前記原料ガスはプラズマにより活性化される
ことを特徴としている。According to a third aspect of the present invention, in the method of manufacturing a semiconductor thin film according to the first aspect, the nitride film or the nitrogen-containing oxide film has a film thickness of 50 to 1000 angstroms. According to a fourth aspect of the invention, in the method of manufacturing a semiconductor thin film according to the first aspect, the source gas is activated by plasma.
【００１０】[0010]
【作用】フッ素（Ｆ）を含むクリーニング・ガスで清浄
する清浄工程によれば、反応炉内の反応炉内壁、電極あ
るいはサセプタ等に付着するフッ素（Ｆ）が、特に半導
体薄膜の特性に影響を及ぼしてしまう。そこで、反応炉
内に残存するフッ素（Ｆ）の影響を効率よく吸収除去
し、しかもクリーニング・ガスで清浄が容易な被膜、即
ちシリコン（Ｓｉ）を含む半導体被膜と半導体被膜上に
窒化被膜もしくは窒素含有酸化被膜を反応炉内に堆積さ
せた後、実際の成膜を行うことにより、洗浄直後であっ
ても、特性に優れた半導体薄膜の製造が可能になること
を見い出し、本発明に至った。According to the cleaning step of cleaning with the cleaning gas containing fluorine (F), the fluorine (F) adhering to the inner wall of the reaction furnace, the electrode, the susceptor, etc. in the reaction furnace affects the characteristics of the semiconductor thin film in particular. Will affect. Therefore, a film that efficiently absorbs and removes the influence of fluorine (F) remaining in the reaction furnace and that is easily cleaned by a cleaning gas, that is, a semiconductor film containing silicon (Si) and a nitride film or nitrogen on the semiconductor film is used. The present invention was found by discovering that it is possible to manufacture a semiconductor thin film having excellent characteristics even immediately after cleaning by actually forming a film after depositing the contained oxide film in the reaction furnace. .
【００１１】シリコン（Ｓｉ）を含む半導体被膜を堆積
させるのは、この半導体被膜が反応炉内に残存するフッ
素（Ｆ）を主とした不純物を膜中に旨くトラップし、こ
れにより反応炉内に残存する不純物を激減させることが
できるためである。この半導体被膜としては、実際に成
膜する半導体薄膜と同一組成とすれば、配管等を増加さ
せる必要がない。また、半導体被膜は、反応炉内に残存
する不純物を十分にトラップさせるためには、２００オ
ングストローム以上の膜厚とすることが好ましく、特に
３００オングストローム以上であれば十分である。しか
しながら、膜厚が厚くなり過ぎると洗浄工程を頻繁に行
う必要があることから、１０００オングストローム以下
であることが好ましい。A semiconductor film containing silicon (Si) is deposited by the semiconductor film, which effectively traps impurities (mainly fluorine (F)) remaining in the reaction furnace in the film, whereby the semiconductor film is deposited in the reaction furnace. This is because residual impurities can be drastically reduced. If this semiconductor film has the same composition as the semiconductor thin film to be actually formed, it is not necessary to increase piping and the like. Further, the semiconductor film preferably has a film thickness of 200 angstroms or more, particularly 300 angstroms or more, in order to sufficiently trap impurities remaining in the reaction furnace. However, if the film thickness becomes too thick, it is necessary to frequently perform the cleaning step, and therefore it is preferably 1000 angstroms or less.
【００１２】また、この発明にあっては、上記した半導
体被膜上に窒化被膜もしくは窒素含有酸化被膜が積層さ
れることを必須の要件としている。半導体被膜上に窒化
被膜もしくは窒素含有酸化被膜を積層配置するのは、シ
リコン（Ｓｉ）を含む半導体被膜が露出していると、真
空中ではあっても半導体被膜表面が不所望な状態に酸化
され、膜剥離し易くなるといった問題点を招くためであ
り、半導体被膜表面の酸化を防止する理由から窒化被膜
もしくは窒素含有酸化被膜を積層する必要がある。Further, in the present invention, it is an essential requirement that a nitride film or a nitrogen-containing oxide film is laminated on the above-mentioned semiconductor film. The nitride film or the nitrogen-containing oxide film is laminated on the semiconductor film. When the semiconductor film containing silicon (Si) is exposed, the surface of the semiconductor film is oxidized into an undesired state even in vacuum. This is because it causes a problem that the film is easily peeled off, and it is necessary to stack a nitride film or a nitrogen-containing oxide film for the reason of preventing oxidation of the surface of the semiconductor film.
【００１３】このように、クリーニング・ガスで清浄し
た後、少なくとも半導体被膜、および窒化被膜もしくは
窒素含有酸化被膜を積層することにより、初めて上記し
た問題点が解決される。Thus, the above-mentioned problems can be solved for the first time by laminating at least the semiconductor film and the nitride film or the nitrogen-containing oxide film after cleaning with the cleaning gas.
【００１４】この窒化被膜もしくは窒素含有酸化被膜
は、半導体被膜が露出することがないように覆っていれ
ば良く、厚膜とする必要ない。半導体被膜表面の酸化防
止を考慮すると５０オングストローム以上とすることが
好ましく、やはり膜厚が厚くなり過ぎると洗浄工程を頻
繁に行う必要があることから、１０００オングストロー
ム以下であることが好ましい。The nitride film or the nitrogen-containing oxide film need only be covered so that the semiconductor film is not exposed, and it is not necessary to form a thick film. The thickness is preferably 50 angstroms or more in consideration of preventing the oxidation of the surface of the semiconductor film, and the thickness is preferably 1000 angstroms or less because the cleaning step must be frequently performed when the film thickness becomes too thick.
【００１５】この発明において、クリーニング・ガスに
よる清浄には、熱、光、プラズマ反応あるいはサイクロ
トロン共鳴等、適宜用いることができ、また、シリコン
（Ｓｉ）を含む原料ガスの活性化にも、同様に熱、光、
プラズマ反応あるいはサイクロトロン共鳴等、適宜用い
ることができるが、中でもプラズマ反応を用いる手法
は、均質で、比較的生産性良く薄膜の堆積が可能である
ことから、シリコン（Ｓｉ）を含む半導体薄膜の堆積に
有用である。In the present invention, for cleaning with a cleaning gas, heat, light, plasma reaction, cyclotron resonance, or the like can be used as appropriate, and similarly, activation of a source gas containing silicon (Si) is also performed. Heat, light,
A plasma reaction, a cyclotron resonance, or the like can be appropriately used. Among them, the method of using a plasma reaction is homogeneous and can relatively easily deposit a thin film. Therefore, a semiconductor thin film containing silicon (Si) can be deposited. Useful for.
【００１６】また、特開昭６３−２１５０３７号あるい
は特開昭６３−２６７４３０号等に記載されているよう
に、クリーニング・ガスで清浄した後、更に水素プラズ
マ等より反応炉内を清浄してもかまわない。Further, as described in JP-A-63-215037 or JP-A-63-267430, after cleaning with a cleaning gas, the inside of the reaction furnace is further cleaned with hydrogen plasma or the like. I don't care.
【００１７】[0017]
【実施例】以下、本発明の一実施例の半導体薄膜の製造
方法について図面を参照して説明する。図１は、この実
施例に用いられる半導体薄膜製造装置(101) の概略構成
図であって、この半導体薄膜製造装置(101) は、アルミ
ナ（Ａｌ2 Ｏ3 ）が表面に被着されて成るアルミニウム
（Ａｌ）によって構成される反応炉を備えたＣＶＤ成膜
系(111) 、ＣＶＤ成膜系(111) にシラン（ＳｉＨ4 ）、
水素（Ｈ2 ）、窒素（Ｎ2 ）およびアンモニア（ＮＨ
3 ）の各原料ガスをそれぞれバルブ(151a)〜(151d)を介
して供給する原料ガス供給系(151) 、ＣＶＤ成膜系(11
1) に三沸化窒素（ＮＦ3 ）とアルゴン（Ａｒ）とをそ
れぞれバルブ(161a),(161b) を介して供給するクリーニ
ングガス供給系(161) 、ＣＶＤ成膜系(111) 内をバルブ
(171a)を介して排気するドライポンプ(173) から構成さ
れる排気系(171) 、ＣＶＤ成膜系(111)に高周波電圧を
供給する電源系(181) とを備えている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor thin film according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a semiconductor thin film manufacturing apparatus (101) used in this embodiment. The semiconductor thin film manufacturing apparatus (101) has alumina (Al 2 O 3 ) deposited on its surface. A CVD film forming system (111) equipped with a reaction furnace composed of aluminum (Al), silane (SiH 4 ) in the CVD film forming system (111),
Hydrogen (H 2 ), nitrogen (N 2 ) and ammonia (NH
3 ) The source gas supply system (151) for supplying each source gas of ( 3 ) via the valves (151a) to (151d), the CVD film forming system (11)
1) A cleaning gas supply system (161) for supplying nitrogen trifluoride (NF 3 ) and argon (Ar) through valves (161a) and (161b) respectively, and a valve for CVD film formation system (111)
An exhaust system (171) including a dry pump (173) for exhausting air through the (171a) and a power supply system (181) for supplying a high frequency voltage to the CVD film forming system (111) are provided.
【００１８】このＣＶＤ成膜系(111) について、図２の
概略断面図を参照して、更に詳細に説明する。ＣＶＤ成
膜系(111) は、図中上下方向に移動可能に支持された凹
状の上収納体(121) と、上収納体(121) と合致する凹状
の下収納体(131) とから成り、それぞれアルミニウム
（Ａｌ）から成る反応炉(113) を備えている。上収納体
(121) の上壁中央部には原料ガスを導入する導入孔(12
3) 、下収納体(131) の側壁には排気系(171) に接続さ
れる排気孔(133) が形成されている。The CVD film forming system (111) will be described in more detail with reference to the schematic sectional view of FIG. The CVD film forming system (111) is composed of a concave upper container (121) movably supported in the vertical direction and a concave lower container (131) that matches the upper container (121). And a reaction furnace (113) made of aluminum (Al), respectively. Upper storage
(121) Introducing holes (12
3) An exhaust hole (133) connected to the exhaust system (171) is formed on the side wall of the lower storage body (131).
【００１９】そして、上収納体(121) には、導入孔(12
3) から導入される原料ガスを反応炉(113) 内に均一に
拡散させる吹き出し孔(143) を備えると共に、電気的に
電源系(181) に接続されて一方の電極としても機能する
アルミナ（Ａｌ2 Ｏ3 ）が表面に被着されて成るアルミ
ニウム（Ａｌ）から成るガス導入電極(141) が支持され
ている。Then, the introduction hole (12
3) A discharge hole (143) for uniformly diffusing the source gas introduced from (3) into the reaction furnace (113) is provided, and alumina (electrically connected to the power supply system (181) and functioning as one electrode ( A gas introduction electrode (141) made of aluminum (Al) having Al 2 O 3 ) deposited on the surface thereof is supported.
【００２０】また、下収納体(131) 上に支持され、一主
表面上に基板を配置することが可能なアルミナ（Ａｌ2
Ｏ3 ）が表面に被着されて成るアルミニウム（Ａｌ）か
ら成るサセプタ(145) を備えている。このサセプタ(14
5) は、基板温度の制御が可能なヒーター(147) を内部
に備えており、ガス導入電極(141) に対向する他方の電
極と成すグランド電位に接続されている。そして、この
サセプタ(145) 一主表面上とマスク(149) とによって基
板(11)が固定される。Alumina (Al 2 ) which is supported on the lower housing (131) and on which a substrate can be arranged on one main surface is provided.
It is provided with a susceptor (145) made of aluminum (Al) having O 3 ) deposited on the surface thereof. This susceptor (14
5) internally includes a heater (147) capable of controlling the substrate temperature, and is connected to the ground potential formed by the other electrode facing the gas introduction electrode (141). The substrate (11) is fixed on the main surface of the susceptor (145) and the mask (149).
【００２１】以下に、このような半導体薄膜製造装置(1
01) を用いたアクティブマトリクス型液晶表示装置の製
造方法について説明する。これは、例えば９．５インチ
の表示領域を備えたアクティブマトリクス型液晶表示装
置を構成するアレイ基板が、１枚のガラス基板から４個
採取されるように３６０mm×４６５mmのガラス基板を使
用するものである。Hereinafter, such a semiconductor thin film manufacturing apparatus (1
A method of manufacturing an active matrix type liquid crystal display device using (01) will be described. For example, a glass substrate of 360 mm × 465 mm is used so that four array substrates constituting an active matrix type liquid crystal display device having a 9.5 inch display area can be collected from one glass substrate. Is.
【００２２】まず、図３（ａ）に示すように、３６０mm
×４６５mmのガラス基板(11)の一主面上にモリブデン・
タンタル（ＭｏＴａ）の被膜を形成し、これを複数本の
ストライプ状にパターンニングしてゲート電極(13a) お
よびゲート電極(13a) と一体の走査線（図示せず）並び
に補助容量線(13b) を形成し、更にゲート電極（１３
ａ）および補助容量線（１３ｂ） 上にゲート絶縁膜と
して酸化シリコン（ＳｉＯ2 ）膜(15a) を堆積する。First, as shown in FIG. 3 (a), 360 mm
Molybdenum on one main surface of the glass substrate (11) of × 465 mm
A tantalum (MoTa) film is formed and patterned into a plurality of stripes to form a gate electrode (13a), a scanning line (not shown) integrated with the gate electrode (13a), and an auxiliary capacitance line (13b). And a gate electrode (13
A silicon oxide (SiO 2 ) film (15a) is deposited as a gate insulating film on a) and the auxiliary capacitance line (13b).
【００２３】このゲート電極(13a) 、補助容量線(13b)
および酸化シリコン膜(15a) が配設されたガラス基板(1
1)を、図示しないが、導入炉から搬送炉、搬送炉から反
応炉(113) に導く。This gate electrode (13a), auxiliary capacitance line (13b)
And the glass substrate (1a on which the silicon oxide film (15a) is arranged.
Although not shown, 1) is introduced from the introduction furnace to the transfer furnace and from the transfer furnace to the reaction furnace (113).
【００２４】ガラス基板(11)は、ゲート電極(13a) 、補
助容量線(13b) および酸化シリコン膜(15a) が配置され
た主表面が、図２に示すようにガス導入電極(141) と対
向するようにサセプタ(145) 上に配置し、その上にマス
ク(149) を配置する。そして、反応ガスとして２００sc
cmの流量のシラン（ＳｉＨ4 ）、１０００sccmの流量の
アンモニア（ＮＨ3 ）、７０００sccmの流量の窒素（Ｎ
2 ）を反応炉(113) 内に導入すると共に、反応炉(113)
内を１Torrに維持する。また、同時に、ヒーター(147)
により加熱されたサセプタ(145) 上の基板(11)温度を３
３０℃まで上昇させる。そして、電源系(181) からガス
導入電極(141) に１３００Ｗの高周波電圧を供給し、こ
れによりシラン（ＳｉＨ4 ）およびアンモニア（ＮＨ
3 ）をプラズマ励起させて基板(11)上に２層目のゲート
絶縁膜としてシリコンナイトライド（ＳｉＮX ）を５０
０オングストロームの膜厚で堆積させる。The glass substrate (11) has a main surface on which the gate electrode (13a), the auxiliary capacitance line (13b) and the silicon oxide film (15a) are arranged as a gas introduction electrode (141) as shown in FIG. The mask (149) is placed on the susceptor (145) so as to face each other. And 200sc as reaction gas
Silane (SiH 4 ) with a flow rate of cm, ammonia (NH 3 ) with a flow rate of 1000 sccm, nitrogen (N with a flow rate of 7000 sccm)
2 ) is introduced into the reactor (113) and the reactor (113)
Keep the inside at 1 Torr. Also, at the same time, heater (147)
The temperature of the substrate (11) on the susceptor (145) heated by
Raise to 30 ° C. Then, a high frequency voltage of 1300 W is supplied from the power supply system (181) to the gas introduction electrode (141), whereby silane (SiH 4 ) and ammonia (NH 3 ) are supplied.
3 ) is plasma-excited to form silicon nitride (SiN x ) 50 as a second gate insulating film on the substrate (11).
Deposit to a thickness of 0 Å.
【００２５】この後、反応ガスとして４００sccmの流量
のシラン（ＳｉＨ4 ）、１４００sccmの流量の水素（Ｈ
2 ）にガスを切り換えて反応炉(113) 内に導入すると共
に、基板(11)温度を３３０℃に制御し、更に１５０Ｗの
高周波電力を供給して、シリコンナイトライド（ＳｉＮ
x ）上に半導体薄膜として非晶質シリコン（ａ−Ｓｉ：
Ｈ）を５００オングストロームの膜厚で堆積させる。
尚、非晶質シリコン（ａ−Ｓｉ：Ｈ）の堆積に際しても
反応炉(11)内を１Torrに維持する。After that, silane (SiH 4 ) having a flow rate of 400 sccm and hydrogen (H) having a flow rate of 1400 sccm are used as reaction gases.
The gas is switched to 2 ) and introduced into the reaction furnace (113), the temperature of the substrate (11) is controlled at 330 ° C., and high-frequency power of 150 W is supplied to supply silicon nitride (SiN).
x ) as a semiconductor thin film on amorphous silicon (a-Si:
H) is deposited to a film thickness of 500 Å.
The inside of the reaction furnace (11) is maintained at 1 Torr during the deposition of amorphous silicon (a-Si: H).
【００２６】再び、反応ガスとして２００sccmの流量の
シラン（ＳｉＨ4 ）、１０００sccmの流量のアンモニア
（ＮＨ3 ）、キャリアガスとして７０００sccmの流量の
窒素（Ｎ2 ）を反応炉(113) 内に導入すると共に、基板
(11)温度を３３０℃に制御し、更に１３００Ｗの高周波
電圧を供給して、チャネル保護膜としてシリコンナイト
ライド（ＳｉＮX ）を３０００オングストロームの膜厚
で堆積させる。尚、シリコンナイトライド（ＳｉＮX ）
の堆積に際してはも反応炉(113) 内は同様の１Torrに維
持する。Again, silane (SiH 4 ) having a flow rate of 200 sccm, ammonia (NH 3 ) having a flow rate of 1000 sccm, and nitrogen (N 2 ) having a flow rate of 7000 sccm are introduced into the reaction furnace (113) as a reaction gas. With the substrate
(11) The temperature is controlled at 330 ° C., and a high frequency voltage of 1300 W is further supplied to deposit silicon nitride (SiN x ) as a channel protective film with a film thickness of 3000 angstrom. Silicon nitride (SiN x )
When depositing, the inside of the reactor (113) is maintained at the same 1 Torr.
【００２７】以上のようにして、図３（ｂ）に示すよう
に、１層目のゲート絶縁膜としてシリコン酸化膜(15a)
を含む基板(11)上にシリコンナイトライド膜(15b) ／半
導体薄膜(17)／チャネル保護膜(19)の３層を連続して堆
積させた後、図２に示す反応炉(113) 内を５０mTorr に
減圧し、図示しないが、この減圧状態と同様の減圧状態
にある搬送炉を介して排出炉に導く。As described above, as shown in FIG. 3B, the silicon oxide film (15a) is formed as the first-layer gate insulating film.
After three layers of silicon nitride film (15b) / semiconductor thin film (17) / channel protective film (19) are continuously deposited on the substrate (11) containing the metal, the reaction furnace (113) shown in FIG. Is depressurized to 50 mTorr, and although not shown, it is led to the discharge furnace via a carrier furnace in a depressurized state similar to this depressurized state.
【００２８】この後、図３（ｃ）に示すように、半導体
薄膜(17)を島状にパターニングして活性層(18)とすると
共に、またゲート電極(13a) をマスクとした裏面露光に
よりゲート電極(13a) に自己整合されたチャネル保護膜
(20)を形成する。Thereafter, as shown in FIG. 3C, the semiconductor thin film (17) is patterned into an island shape to form an active layer (18), and by backside exposure using the gate electrode (13a) as a mask. Channel protective film self-aligned with the gate electrode (13a)
Form (20).
【００２９】この後、図３（ｄ）に示すように、ＩＴＯ
（Indium Tin Oxide）を成膜し、パターニングして画素
電極(21)を形成する。また、ｎ+ 型の非晶質シリコン
（ａ−Ｓｉ：Ｈ）を堆積し、島状にパターニングして低
抵抗半導体膜(25)を形成した後、モリブデン（Ｍｏ）、
アルミニウム（Ａｌ）およびモリブデン（Ｍｏ）の３層
構造の導電体層(29)を堆積する。After this, as shown in FIG.
A film of (Indium Tin Oxide) is formed and patterned to form a pixel electrode (21). Further, n + type amorphous silicon (a-Si: H) is deposited and patterned in an island shape to form a low resistance semiconductor film (25), and then molybdenum (Mo),
A conductor layer (29) having a three-layer structure of aluminum (Al) and molybdenum (Mo) is deposited.
【００３０】この後、チャネル保護膜(20)上の低抵抗半
導体膜(25)をおよび導電体層(29)を切断すると共に、導
電体層(29)をパターンニングして画素電極(21)に接続さ
れるソース電極(31)、信号線(33)と一体のドレイン電極
(35)とをそれぞれ構成する。Thereafter, the low resistance semiconductor film (25) and the conductor layer (29) on the channel protection film (20) are cut, and the conductor layer (29) is patterned to form the pixel electrode (21). Drain electrode integrated with the source electrode (31) and signal line (33) connected to
(35) and are respectively configured.
【００３１】以上のようにして構成されたアレイ基板を
用い、図示しないが、常法にしたがって対向基板と所定
の間隔を隔てて貼り合わせ、基板間に液晶組成物を注入
し、封止して液晶パネルを構成する。更に、液晶パネル
と駆動回路基板とを電気的に接続すると共に、必要であ
れば液晶パネル外表面に偏光板を貼り付けて液晶表示装
置を完成させた。Although not shown in the figure, the array substrate constructed as described above is adhered to a counter substrate at a predetermined interval according to a conventional method, and a liquid crystal composition is injected between the substrates and sealed. Configure a liquid crystal panel. Further, the liquid crystal panel and the drive circuit board were electrically connected, and if necessary, a polarizing plate was attached to the outer surface of the liquid crystal panel to complete the liquid crystal display device.
【００３２】ところで、この実施例では、上記したシリ
コンナイトライド膜(15b) ／半導体薄膜(17)／チャネル
保護膜(19)の３層の連続成膜に先立ち、次のような操作
を行っている。By the way, in this embodiment, the following operations were performed prior to the continuous film formation of three layers of the silicon nitride film (15b) / semiconductor thin film (17) / channel protective film (19). There is.
【００３３】即ち、図２に示す反応炉(113) の内壁、ガ
ス導入電極(141) 、サセプタ(145)およびマスク(149)
の表面には、先の成膜工程での非晶質シリコン（ａ−Ｓ
ｉ：Ｈ）やシリコンナイトライド（ＳｉＮX ）が複数層
にわたり堆積されている。That is, the inner wall of the reaction furnace (113) shown in FIG. 2, the gas introduction electrode (141), the susceptor (145) and the mask (149).
On the surface of the amorphous silicon (a-S
i: H) and silicon nitride (SiN x ) are deposited over a plurality of layers.
【００３４】このような反応炉(113) の内壁、ガス導入
電極(141) 、サセプタ(145) およびマスク(149) の表面
に堆積する非晶質シリコン（ａ−Ｓｉ：Ｈ）やシリコン
ナイトライド（ＳｉＮX ）の膜厚が増大すると、成膜途
中に膜中に小片として混入すること等が生じ、製造歩留
りの低下を招いてしまう。特に、ガス導入電極(141)と
サセプタ(145) との間に挟まれる反応空間に接する領
域、例えばガス導入電極(145) の主表面やマスク(149)
の表面等に堆積される不要被膜が問題となる。Amorphous silicon (a-Si: H) and silicon nitride deposited on the inner wall of the reactor (113), the gas introduction electrode (141), the susceptor (145) and the surface of the mask (149). When the film thickness of (SiN x ) increases, it may be mixed into the film as a small piece during film formation, resulting in a decrease in manufacturing yield. In particular, a region in contact with the reaction space sandwiched between the gas introduction electrode (141) and the susceptor (145), for example, the main surface of the gas introduction electrode (145) or the mask (149).
Unnecessary coatings deposited on the surface and the like of the are problems.
【００３５】このため、反応空間に接する領域での不要
被膜の膜厚が増大した際、反応炉(113) 内壁を、クリー
ニングガス供給系(161) から７００sccmの流量の三沸化
窒素（ＮＦ3 ）と１００sccmの流量のアルゴン（Ａｒ）
とをそれぞれバルブ(161a),(161b) を介して供給すると
共に、１５００Ｗの高周波電圧を供給し、１０分間清浄
して、反応炉(113) の内壁、ガス導入電極(141) 、サセ
プタ(145) およびマスク(149) の表面の不要被膜をプラ
ズマ・クリーニングにより除去する。Therefore, when the film thickness of the unnecessary coating in the region in contact with the reaction space increases, the inner wall of the reaction furnace (113) is moved from the cleaning gas supply system (161) to a nitrogen trifluoride (NF 3 ) flow rate of 700 sccm. ) And argon (Ar) at a flow rate of 100 sccm
Are supplied via valves (161a) and (161b), respectively, and a high frequency voltage of 1500 W is supplied to clean them for 10 minutes, and then the inner wall of the reaction furnace (113), the gas introduction electrode (141) and the susceptor (145 ) And the unwanted coating on the surface of the mask (149) is removed by plasma cleaning.
【００３６】そして、このプラズマ・クリーニング後、
実際の成膜の工程と同様の条件で、非晶質シリコン（ａ
−Ｓｉ：Ｈ）とシリコンナイトライド（ＳｉＮX ）とを
堆積させる。尚、非晶質シリコン被膜およびシリコンナ
イトライド被膜の膜厚は、それぞれサセプタ(145) 上で
３００オングストローム、５０オングストロームとなる
ように行った。従って、反応空間外、例えば反応炉(11
3) の内壁にあっては、更に薄膜となっているが、反応
空間での非晶質シリコン被膜およびシリコンナイトライ
ド被膜の膜厚が所望の範囲内に制御されていれば良い。After this plasma cleaning,
Under the same conditions as in the actual film forming process, the amorphous silicon (a
-Si: H) and depositing a silicon nitride (SiN X). The thickness of the amorphous silicon film and the thickness of the silicon nitride film were set to 300 angstroms and 50 angstroms on the susceptor (145), respectively. Therefore, outside the reaction space, for example, in the reactor (11
Although the inner wall of 3) is further thinned, the film thickness of the amorphous silicon film and the silicon nitride film in the reaction space may be controlled within a desired range.
【００３７】このような工程を経た後に、上記したシリ
コンナイトライド膜(15b) ／半導体薄膜(17)／チャネル
保護膜(19)の３層の連続成膜を実施している。そして、
この実施例では、上記した３層の連続成膜を１サイクル
として、１０サイクルを経た後、再びプラズマ・クリー
ニング工程、プリコート工程を実施した。After passing through these steps, three layers of the above-mentioned silicon nitride film (15b) / semiconductor thin film (17) / channel protective film (19) are continuously formed. And
In this example, the above-mentioned continuous film formation of three layers was set as one cycle, and after 10 cycles, the plasma cleaning step and the precoating step were performed again.
【００３８】上記した実施例によれば、プラズマ・クリ
ーニング工程直後のＴＦＴの活性層(18)と、成膜工程を
９サイクル経た後のＴＦＴの活性層(18)とでは、移動度
に差異は認められなかった。According to the above-described embodiment, there is no difference in mobility between the TFT active layer (18) immediately after the plasma cleaning step and the TFT active layer (18) after 9 cycles of the film forming step. I was not able to admit.
【００３９】また、上記した実施例により得られたＴＦ
Ｔ（Ａ）、プラズマ・クリーニング工程後にプリコート
工程を経ることなく作成されたＴＦＴ（Ｂ）、プラズマ
・クリーニング工程後にシリコンナイトライド被膜を堆
積させない以外は実施例と同様のプリコート工程を経て
作成されたＴＦＴ（Ｃ）、プラズマ・クリーニング工程
後に非晶質シリコン被膜を堆積させない以外は実施例と
同様のプリコート工程を経て作成されたＴＦＴ（Ｄ）の
しきい値電圧をそれぞれ測定したところ、ＴＦＴ
（Ａ）：２Ｖ，ＴＦＴ（Ｂ）：５Ｖ，ＴＦＴ（Ｃ）：２
Ｖ，ＴＦＴ（Ｄ）：５Ｖであった。Further, the TF obtained by the above embodiment
T (A), a TFT (B) formed without a precoating step after the plasma cleaning step, and a precoating step similar to the example except that the silicon nitride film is not deposited after the plasma cleaning step The threshold voltages of the TFT (C) and the TFT (D) formed through the same precoating process as in the example except that the amorphous silicon film was not deposited after the plasma cleaning process were measured.
(A): 2V, TFT (B): 5V, TFT (C): 2
V, TFT (D): 5V.
【００４０】また、ＴＦＴ（Ａ）とＴＦＴ（Ｃ）の製造
途中で、サセプタ(145) 上に付着する３ミクロン以上の
パーティクルを測定したところ、ＴＦＴ（Ｃ）の製造途
中では０．０８個／ｃｍ2 であったものが、ＴＦＴ
（Ａ）製造途中では０．０５個／ｃｍ2 以下に減少させ
ることができた。Further, when the particles of 3 μm or more adhering to the susceptor (145) were measured during the manufacture of the TFT (A) and the TFT (C), 0.08 particles / What was cm 2 is TFT
(A) During production, the number could be reduced to 0.05 pieces / cm 2 or less.
【００４１】以上のように、この実施例によれば、清浄
工程直後であっても、安定した膜特性が得られ、しかも
従来に比べて製造途中でのパーティクル発生量の低い、
液晶表示装置に適した絶縁膜と非晶質シリコンの積層膜
を得ることができた。As described above, according to this embodiment, stable film characteristics can be obtained even immediately after the cleaning step, and the amount of particles generated during manufacturing is lower than that of the conventional method.
A laminated film of an insulating film and amorphous silicon suitable for a liquid crystal display device could be obtained.
【００４２】上述した実施例では、基板の主表面に対し
て平行に電極が配置され、しかも基板の主表面に対して
原料ガスが垂直に照射される平行平板型のプラズマＣＶ
Ｄ装置を例にとり説明したが、これに限定されるもので
はない。In the above-described embodiment, the parallel plate type plasma CV in which the electrodes are arranged in parallel with the main surface of the substrate and the source gas is irradiated perpendicularly to the main surface of the substrate.
Although description has been made by taking the D device as an example, the present invention is not limited to this.
【００４３】また、プリコート工程において、非晶質シ
リコン（ａ−Ｓｉ：Ｈ）被膜とシリコンナイトライド
（ＳｉＮX ）被膜とを積層する場合を例にとり説明した
が、シリコンナイトライド（ＳｉＮX ）被膜に代えて窒
素含有シリコン酸化膜（ＳｉＯＮ）を用いても良い。こ
の場合は、原料ガス供給系(151) に亜酸化窒素（Ｎ2
Ｏ）を加え、亜酸化窒素（Ｎ2 Ｏ）、シラン（ＳｉＨ
4 ）および窒素（Ｎ2 ）をプラズマ励起させて堆積すれ
ば良い。更に、プリコート工程を、シリコンナイトライ
ド被膜／非晶質シリコン被膜／シリコンナイトライド被
膜の三層構造としても良い。In the precoating process, the case where the amorphous silicon (a-Si: H) film and the silicon nitride (SiN x ) film are laminated has been described as an example, but the silicon nitride (SiN x ) film is used. Instead of this, a nitrogen-containing silicon oxide film (SiON) may be used. In this case, the nitrous oxide (N 2
O), nitrous oxide (N 2 O), silane (SiH
4 ) and nitrogen (N 2 ) may be deposited by plasma excitation. Further, the pre-coating step may have a three-layer structure of silicon nitride film / amorphous silicon film / silicon nitride film.
【００４４】[0044]
【発明の効果】この発明の半導体薄膜の製造方法によれ
ば、清浄工程直後であっても、安定した膜特性が得ら
れ、しかも従来に比べてパーティクル発生量の低い、液
晶表示装置に適した半導体薄膜を得ることができる。According to the method for manufacturing a semiconductor thin film of the present invention, stable film characteristics can be obtained even immediately after the cleaning step, and moreover, it is suitable for a liquid crystal display device in which the amount of particles generated is smaller than in the conventional case. A semiconductor thin film can be obtained.
【図１】図１は、本発明の一実施例の半導体薄膜の製造
方法に用いられる半導体薄膜製造装置の概略構成図であ
る。FIG. 1 is a schematic configuration diagram of a semiconductor thin film manufacturing apparatus used in a method for manufacturing a semiconductor thin film according to an embodiment of the present invention.
【図２】図２は、図１のＣＶＤ成膜系の概略断面図であ
る。FIG. 2 is a schematic cross-sectional view of the CVD film forming system of FIG.
【図３】図３は、本発明の一実施例の半導体薄膜の製造
プロセスを示す図である。FIG. 3 is a diagram showing a manufacturing process of a semiconductor thin film according to an embodiment of the present invention.
(101) …半導体薄膜製造装置 (111) …ＣＶＤ成膜系 (151) …原料ガス供給系 (161) …クリーニングガス供給系 (171) …排気系 (181) …電源系 (101) ... Semiconductor thin film manufacturing apparatus (111) ... CVD film forming system (151) ... Raw material gas supply system (161) ... Cleaning gas supply system (171) ... Exhaust system (181) ... Power supply system
Claims (4)
料ガスに基づいて反応炉内で基板上に半導体薄膜を堆積
させる半導体薄膜の製造方法において、 前記半導体薄膜を堆積させる前に、前記反応炉内をフッ
素（Ｆ）を含むクリーニング・ガスで清浄する清浄工程
と、前記反応炉内に少なくとも前記シリコン（Ｓｉ）を
含む半導体被膜と，前記半導体被膜上に窒化被膜もしく
は窒素含有酸化被膜を積層して堆積させる堆積工程とを
具備したことを特徴とした半導体薄膜の製造方法。1. A method of manufacturing a semiconductor thin film, comprising depositing a semiconductor thin film on a substrate in a reaction furnace based on an activated source gas containing silicon (Si), wherein the reaction is performed before the semiconductor thin film is deposited. A cleaning step of cleaning the inside of the furnace with a cleaning gas containing fluorine (F), a semiconductor coating containing at least the silicon (Si) in the reaction furnace, and a nitride coating or a nitrogen-containing oxide coating on the semiconductor coating. A method of manufacturing a semiconductor thin film, comprising:
おいて、前記半導体被膜が２００〜１０００オングスト
ロームの膜厚を有することを特徴とした半導体薄膜の製
造方法。2. The method of manufacturing a semiconductor thin film according to claim 1, wherein the semiconductor film has a film thickness of 200 to 1000 angstroms.
おいて、前記窒化被膜もしくは酸化被膜が５０〜１００
０オングストロームの膜厚を有することを特徴とした半
導体薄膜の製造方法。3. The method for producing a semiconductor thin film according to claim 1, wherein the nitride film or the oxide film is 50-100.
A method of manufacturing a semiconductor thin film having a film thickness of 0 angstrom.
おいて、前記原料ガスはプラズマにより活性化されるこ
とを特徴とした半導体薄膜の製造方法。4. The method of manufacturing a semiconductor thin film according to claim 1, wherein the source gas is activated by plasma.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18804394A JP3593363B2 (en) | 1994-08-10 | 1994-08-10 | Method for manufacturing active matrix type liquid crystal display device having semiconductor thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18804394A JP3593363B2 (en) | 1994-08-10 | 1994-08-10 | Method for manufacturing active matrix type liquid crystal display device having semiconductor thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0855804A true JPH0855804A (en) | 1996-02-27 |
| JP3593363B2 JP3593363B2 (en) | 2004-11-24 |
Family
ID=16216688
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18804394A Expired - Lifetime JP3593363B2 (en) | 1994-08-10 | 1994-08-10 | Method for manufacturing active matrix type liquid crystal display device having semiconductor thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3593363B2 (en) |
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|---|---|---|---|---|
| JP2002329671A (en) * | 2001-05-01 | 2002-11-15 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device |
| WO2004086482A1 (en) * | 2003-03-25 | 2004-10-07 | Tokyo Electron Limited | Method for cleaning thin-film forming apparatus |
| WO2009102762A3 (en) * | 2008-02-11 | 2009-11-12 | Sweeney Joseph D | Ion source cleaning in semiconductor processing systems |
| US7819981B2 (en) | 2004-10-26 | 2010-10-26 | Advanced Technology Materials, Inc. | Methods for cleaning ion implanter components |
| US8809203B2 (en) | 2007-06-05 | 2014-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device using a microwave plasma CVD apparatus |
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1994
- 1994-08-10 JP JP18804394A patent/JP3593363B2/en not_active Expired - Lifetime
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002329671A (en) * | 2001-05-01 | 2002-11-15 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device |
| JP4713759B2 (en) * | 2001-05-01 | 2011-06-29 | 東芝モバイルディスプレイ株式会社 | Manufacturing method of semiconductor device |
| US9169553B2 (en) | 2002-11-11 | 2015-10-27 | Hitachi Kokusai Electric Inc. | Semiconductor device producing method |
| WO2004086482A1 (en) * | 2003-03-25 | 2004-10-07 | Tokyo Electron Limited | Method for cleaning thin-film forming apparatus |
| US7819981B2 (en) | 2004-10-26 | 2010-10-26 | Advanced Technology Materials, Inc. | Methods for cleaning ion implanter components |
| US8809203B2 (en) | 2007-06-05 | 2014-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device using a microwave plasma CVD apparatus |
| US9991095B2 (en) | 2008-02-11 | 2018-06-05 | Entegris, Inc. | Ion source cleaning in semiconductor processing systems |
| WO2009102762A3 (en) * | 2008-02-11 | 2009-11-12 | Sweeney Joseph D | Ion source cleaning in semiconductor processing systems |
| KR20150065743A (en) * | 2012-09-27 | 2015-06-15 | 선파워 코포레이션 | Methods and structures for forming and protecting thin films on substrates |
| JP2016502748A (en) * | 2012-09-27 | 2016-01-28 | サンパワー コーポレイション | Method for forming and protecting a thin film on a substrate |
| WO2021199479A1 (en) * | 2020-04-01 | 2021-10-07 | キヤノンアネルバ株式会社 | Film formation device, device for controlling film formation device, and film formation method |
| CN115427606A (en) * | 2020-04-01 | 2022-12-02 | 佳能安内华股份有限公司 | Film forming apparatus, control apparatus for film forming apparatus, and film forming method |
| CN115427606B (en) * | 2020-04-01 | 2024-01-02 | 佳能安内华股份有限公司 | Film forming apparatus, control apparatus for film forming apparatus, and film forming method |
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|---|---|
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