JPH08330956A - Pll circuit - Google Patents

Pll circuit

Info

Publication number
JPH08330956A
JPH08330956A JP7158528A JP15852895A JPH08330956A JP H08330956 A JPH08330956 A JP H08330956A JP 7158528 A JP7158528 A JP 7158528A JP 15852895 A JP15852895 A JP 15852895A JP H08330956 A JPH08330956 A JP H08330956A
Authority
JP
Japan
Prior art keywords
frequency
signal
phase comparator
pll circuit
loop filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7158528A
Other languages
Japanese (ja)
Inventor
Tetsuya Takahashi
哲也 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Communication Equipment Co Ltd
Original Assignee
Toyo Communication Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Communication Equipment Co Ltd filed Critical Toyo Communication Equipment Co Ltd
Priority to JP7158528A priority Critical patent/JPH08330956A/en
Publication of JPH08330956A publication Critical patent/JPH08330956A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE: To provide the PLL circuit which sufficiently suppresses the side spurious level while keeping the response characteristic high-speed. CONSTITUTION: In the PLL circuit which composes a signal of a desired frequency from a given signal of a reference frequency, two PLL circuits 13 and 15 are connected in series, and a signal of an intermediate frequency is composed from the signal of the reference frequency by the first PLL circuit 13, and the signal of the desired frequency is composed from the signal of the intermediate frequency by the second PLL circuit 15, and the value of the intermediate frequency is so set that reference frequencies inputted to phase comparators 19 and 29 or PLL circuits 13 and 15 are sufficiently higher than cutoff frequencies of loop filters of PLL circuits 13 and 15.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、与えられた基準周波数
の信号から、所要の周波数の信号を合成するＰＬＬ回路
に関し、特に、応答特性を高速のまま維持してサイドス
プリアスレベルを充分に抑圧することができるＰＬＬ回
路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit for synthesizing a signal of a required frequency from a signal of a given reference frequency, and more particularly, it maintains the response characteristic at a high speed to sufficiently suppress the side spurious level. PLL circuit that can do.

【０００２】[0002]

【従来技術】一般に、無線通信機器等の局部発振器用と
して、与えられた基準周波数の信号から所要の周波数の
信号を合成するＰＬＬ回路が広く用いられている。図３
に、従来のＰＬＬ回路の一例の構成図を示す。図３に示
す様に、この従来のＰＬＬ回路は、無線機の持つ高安定
な基準発振器の出力信号（基準周波数信号：５ＭＨｚ）
から、所要の信号周波数４１．９４３０４ＭＨｚを生成
するためのもので、上記基準周波数信号を入力する第１
の分周器１と、上記第１の分周器１に接続された位相比
較器３と、上記位相比較器３に接続されたループフィル
タ５と、上記ループフィルタ５に接続されたＶＣＯ（電
圧制御発振器）７と、上記ＶＣＯ７および位相比較器３
に接続された第２の分周器９とを有している。2. Description of the Related Art Generally, a PLL circuit for synthesizing a signal of a required frequency from a signal of a given reference frequency is widely used for a local oscillator of a wireless communication device or the like. FIG.
FIG. 1 shows a configuration diagram of an example of a conventional PLL circuit. As shown in FIG. 3, this conventional PLL circuit has an output signal (reference frequency signal: 5 MHz) of a highly stable reference oscillator of a radio device.
To generate a required signal frequency of 41.94304 MHz from the first input of the reference frequency signal.
Frequency divider 1, a phase comparator 3 connected to the first frequency divider 1, a loop filter 5 connected to the phase comparator 3, and a VCO (voltage Controlled oscillator) 7, the VCO 7 and the phase comparator 3
And a second frequency divider 9 connected to.

【０００３】上記図３に示すＰＬＬ回路の動作として
は、上記５ＭＨｚの基準周波数信号が上記第１の分周器
１に入力されると、３２０Ｈｚに分周され、上記位相比
較器３へ第１の入力信号（レファレンス信号）として供
給される。上記位相比較器３は、上記第１の入力信号と
後述する上記第２の分周器９よりの第２の入力信号との
位相差が０°となる様な制御出力信号を出力し、その制
御出力信号は、上記ループフィルタ５を介して上記ＶＣ
Ｏ７の制御端子に供給され、上記ＶＣＯ７の出力周波数
が制御される。そして、上記ＶＣＯ７の出力がフィード
バックされ、上記第２の分周器９によって１／１３１０
７２に分周されて上記位相比較器３への第２の入力信号
となっている。従って、上記第１および第２の入力信号
の位相差が０°となる様に、上記ＶＣＯ７よりの出力信
号の周波数および位相が制御され、これにより、上記基
準周波数信号と同等の安定度を持つ所要の周波数（４
１．９４３０４ＭＨｚ）の信号が得られる。In the operation of the PLL circuit shown in FIG. 3, when the reference frequency signal of 5 MHz is input to the first frequency divider 1, the frequency is divided to 320 Hz and the phase comparator 3 outputs the first signal. Is supplied as an input signal (reference signal). The phase comparator 3 outputs a control output signal such that the phase difference between the first input signal and the second input signal from the second frequency divider 9 described later becomes 0 °, and The control output signal is sent to the VC via the loop filter 5.
It is supplied to the control terminal of O7 and the output frequency of the VCO 7 is controlled. Then, the output of the VCO 7 is fed back, and the second frequency divider 9 outputs 1/1310.
It is divided by 72 and becomes the second input signal to the phase comparator 3. Therefore, the frequency and phase of the output signal from the VCO 7 are controlled so that the phase difference between the first and second input signals becomes 0 °, and thus the stability is equivalent to that of the reference frequency signal. Required frequency (4
A signal of 1.94304 MHz) is obtained.

【０００４】しかしながら、上述の様な構成の従来のＰ
ＬＬ回路においては、上記位相比較器３に入力されるリ
ファレンス信号（第１の入力信号）の周波数ｆｒが３２
０Ｈｚと非常に低いため、上記ループフィルタ５でこれ
を充分除去できず、図４に示す様に所要の出力信号のス
ペクトラム上において、３２０Ｈｚおきにサイドスプリ
アスが発生する問題があった。However, the conventional P having the above-mentioned structure is used.
In the LL circuit, the frequency fr of the reference signal (first input signal) input to the phase comparator 3 is 32.
Since it is as low as 0 Hz, it cannot be sufficiently removed by the loop filter 5, and as shown in FIG. 4, there is a problem that side spurs are generated every 320 Hz on the spectrum of the required output signal.

【０００５】また、このサイドスプリアスを除去するた
めに上記ループフィルタ５のカットオフ周波数をリファ
レンス周波数ｆｒに比べて極めて低く設定すると、ＰＬ
Ｌ回路の応答特性が遅くなってしまい、同期を得られる
時間が長くなるという欠点があった。また、上記サイド
スプリアスを除去する改善策として、図５に示す様な構
成のＰＬＬ回路が提案されている。このＰＬＬ回路は、
図３に示した先の従来例におけるループフィルタ５とＶ
ＣＯ７との間に、リファレンス周波数（ｆｒ＝３２０Ｈ
ｚ）除去用のローパスフィルタ１１を設けたものであ
る。If the cutoff frequency of the loop filter 5 is set to be extremely lower than the reference frequency fr in order to remove this side spurious, PL
There is a drawback that the response characteristic of the L circuit becomes slow and the time for obtaining the synchronization becomes long. Further, as an improvement measure for removing the side spurious, a PLL circuit having a configuration as shown in FIG. 5 has been proposed. This PLL circuit is
The loop filter 5 and V in the prior art example shown in FIG.
Reference frequency (fr = 320H) between CO7
z) A low pass filter 11 for removal is provided.

【０００６】しかしながら、この従来例では、十分にサ
イドスプリアスを除去することができず、所要出力に対
するサイドスプリアスレベルの要求値がきびしいものに
ついては、その要求値を満足できないという欠点があっ
た。すなわち、リファレンス周波数のとりうる最大の周
波数は、基準信号周波数と、所要信号周波数の最大公約
数であるから図３に示すＰＬＬ回路の場合、 ５ＭＨｚ＝２6 ×５7 ４１．９４３０４ＭＨｚ＝２23×５1 より２6 ×５1 ＝３２０Ｈｚとなり、これより大きくす
ることはできなかった。そのため、上記サイドスプリア
スレベルの要求値がきびしい場合は対応できなかった。However, this conventional example has a drawback in that it is not possible to sufficiently remove the side spurious and the required value of the side spurious level with respect to the required output is severe, so that the required value cannot be satisfied. That is, since the maximum frequency that the reference frequency can take is the greatest common divisor of the reference signal frequency and the required signal frequency, in the case of the PLL circuit shown in FIG. 3, 5 MHz = 2 6 × 5 7 41.94304 MHz = 2 23 × It was 2 6 × 5 1 = 320 Hz from 5 1 and could not be made higher than this. Therefore, it was not possible to meet the demands for the above side spurious level.

【０００７】[0007]

【目的】本発明は、上記事情に鑑みてなされたものであ
って、応答特性を高速のまま維持してサイドスプリアス
レベルを充分に抑圧することができるＰＬＬ回路を提供
することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a PLL circuit capable of maintaining response characteristics at a high speed and sufficiently suppressing side spurious levels.

【０００８】[0008]

【発明の概要】上記目的を達成するため、本発明は、与
えられた基準周波数の信号から、所要の周波数の信号を
合成するＰＬＬ回路において、２つのＰＬＬ回路を直列
に接続し、第１のＰＬＬ回路で基準周波数の信号から一
旦中間的周波数の信号を合成し、第２のＰＬＬ回路で上
記中間的周波数の信号から所要の周波数の信号を合成す
ると共に、上記各ＰＬＬ回路のループフィルタのカット
オフ周波数に比べて上記各ＰＬＬ回路の位相比較器に入
力されるリファレンス周波数が十分高くなる様に、上記
中間的周波数の値を設定したことを特徴とする。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is a PLL circuit for synthesizing a signal of a required frequency from a signal of a given reference frequency, by connecting two PLL circuits in series, and The PLL circuit temporarily synthesizes an intermediate frequency signal from the reference frequency signal, the second PLL circuit synthesizes a desired frequency signal from the intermediate frequency signal, and cuts the loop filter of each of the PLL circuits. The value of the intermediate frequency is set so that the reference frequency input to the phase comparator of each PLL circuit is sufficiently higher than the off frequency.

【０００９】[0009]

【実施例】以下、本発明を図示した実施例に基づいて説
明する。図１は、本発明によるＰＬＬ回路の一実施例を
示す構成図である。この実施例の要旨は、図１におい
て、２つのＰＬＬ回路１３、１５を直列に接続して、第
１のＰＬＬ回路１３によって一旦基準周波数信号から中
間的周波数を得、第２のＰＬＬ回路１５によって上記中
間的周波数から所要周波数を得る様にすると共に、上記
中間的周波数の値を上記第１および第２のＰＬＬ回路１
３、１５それぞれの位相比較器１９、２９に入力される
リファレンス周波数がそれぞれのループフィルタ２１、
３１のカットオフ周波数に比べて充分に高い周波数とな
る様に設定して、サイドスプリアスを充分に抑制する様
にしたことである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on illustrated embodiments. FIG. 1 is a configuration diagram showing an embodiment of a PLL circuit according to the present invention. The gist of this embodiment is that in FIG. 1, two PLL circuits 13 and 15 are connected in series, an intermediate frequency is once obtained from a reference frequency signal by the first PLL circuit 13, and an intermediate frequency is obtained by the second PLL circuit 15. The required frequency is obtained from the intermediate frequency, and the value of the intermediate frequency is set to the first and second PLL circuits 1
The reference frequencies input to the phase comparators 19 and 29 of the respective 3 and 15 are the respective loop filters 21 and
This is to set the frequency to be sufficiently higher than the cut-off frequency of 31, so as to sufficiently suppress the side spurious.

【００１０】図１に示す様に、このＰＬＬ回路は、上記
基準周波数信号（５ＭＨｚ）を入力する第１の分周器１
７と、上記第１の分周器１７に接続された第１の位相比
較器１９と、上記第１の位相比較器１９に接続された第
１のループフィルタ２１と、上記第１のループフィルタ
２１に接続された第１のＶＣＯ（電圧制御発振器）２３
と、第１のＶＣＯ２３および第１の位相比較器１９に接
続された第２の分周器２５と、上記第１のＶＣＯ２３に
接続された第３の分周器２７と、上記第３の分周器２７
に接続された第２の位相比較器２９と、上記第２の位相
比較器２９に接続された第２のループフィルタ３１と、
上記第２のループフィルタ３１に接続された第２のＶＣ
Ｏ（電圧制御発振器）３３と、上記第２のＶＣＯ３３お
よび第２の位相比較器２９に接続された第４の分周器３
５とを有している。As shown in FIG. 1, the PLL circuit includes a first frequency divider 1 for inputting the reference frequency signal (5 MHz).
7, a first phase comparator 19 connected to the first frequency divider 17, a first loop filter 21 connected to the first phase comparator 19, and the first loop filter First VCO (voltage controlled oscillator) 23 connected to 21
A second frequency divider 25 connected to the first VCO 23 and the first phase comparator 19, a third frequency divider 27 connected to the first VCO 23, and a third frequency divider. Divider 27
A second phase comparator 29 connected to the second phase comparator 29, a second loop filter 31 connected to the second phase comparator 29,
Second VC connected to the second loop filter 31
O (voltage controlled oscillator) 33, and the fourth frequency divider 3 connected to the second VCO 33 and the second phase comparator 29.
5 and 5.

【００１１】次に、上記図１に示すＰＬＬ回路の動作に
ついて説明する。まず、上記５ＭＨｚの基準周波数信号
が、上記第１の分周器１７に入力されると、２００ＫＨ
ｚに分周され、上記第１の位相比較器１９へ第１の入力
信号（レファレンス信号）として供給される。上記第１
の位相比較器１９は、上記第１の入力信号と後述する上
記第２の分周器２５よりの第２の入力信号との位相差が
０°となる様な制御出力信号を出力し、その制御出力信
号は、上記第１のループフィルタ２１を介して上記第１
のＶＣＯ２３の制御端子に供給され、上記第１のＶＣＯ
２３の出力周波数が５１．２ＭＨｚの中間的周波数にな
る様に制御される。そして、上記第１のＶＣＯ２３の出
力がフィードバックされ、上記第２の分周器２５によっ
て１／２５６に分周されて上記第１の位相比較器１９へ
の第２の入力信号となっている。Next, the operation of the PLL circuit shown in FIG. 1 will be described. First, when the 5 MHz reference frequency signal is input to the first frequency divider 17, 200 KH
The frequency is divided into z and supplied to the first phase comparator 19 as a first input signal (reference signal). The first
Of the phase comparator 19 outputs a control output signal such that the phase difference between the first input signal and the second input signal from the second frequency divider 25 described later becomes 0 °, The control output signal is sent to the first loop filter 21 through the first loop filter 21.
Of the first VCO supplied to the control terminal of the VCO 23 of
The output frequency of 23 is controlled to an intermediate frequency of 51.2 MHz. Then, the output of the first VCO 23 is fed back, divided by the second frequency divider 25 into 1/256, and becomes a second input signal to the first phase comparator 19.

【００１２】ここで、上記第１の位相比較器１９に入力
されるリファレンス信号の周波数ｆｒ１が２００ＫＨｚ
と高い周波数に設定されているので、上記第１のＶＣＯ
２３の出力において発生するリファレンス周波数による
サイドスプリアスの周波数を所要周波数４１．９４３０
４ＭＨｚから離れた所に持ってくることができる。従っ
て、上記第１のループフィルタ２１のカットオフ周波数
を極端に低くする必要がなく、ＰＬＬ回路としての高速
な応答特性を維持しながら、図２に示す様に、上記サイ
ドスプリアスを充分に取り除くことができる。Here, the frequency fr1 of the reference signal input to the first phase comparator 19 is 200 KHz.
Since it is set to a high frequency, the first VCO
The frequency of the side spurious generated by the reference frequency generated at the output of 23 is the required frequency 41.9430.
It can be brought away from 4MHz. Therefore, it is not necessary to make the cutoff frequency of the first loop filter 21 extremely low, and the side spurious is sufficiently removed as shown in FIG. 2 while maintaining the high-speed response characteristics of the PLL circuit. You can

【００１３】次に、上記第１のＶＣＯ２３よりの中間的
周波数信号（５１．２ＭＨｚ）が、上記第３の分周器２
７に入力されると、８１．９２ＫＨｚに分周され、上記
第２の位相比較器２９へ第１の入力信号（レファレンス
信号）として供給される。上記第２の位相比較器２９
は、上記第１の入力信号と後述する上記第４の分周器３
５よりの第２の入力信号との位相差が０°となる様な制
御出力信号を出力し、その制御出力信号は、上記第２の
ループフィルタ３１を介して上記第２のＶＣＯ３３の制
御端子に供給され、上記第２のＶＣＯ３３の出力周波数
が４１．９４３０４ＭＨｚの所要周波数になる様に制御
される。そして、上記第２のＶＣＯ３３の出力がフィー
ドバックされ、上記第４の分周器３５によって１／５１
２に分周されて上記第２の位相比較器２９への第２の入
力信号となっている。Next, the intermediate frequency signal (51.2 MHz) from the first VCO 23 is supplied to the third frequency divider 2
When it is input to 7, the frequency is divided to 81.92 KHz and is supplied to the second phase comparator 29 as a first input signal (reference signal). The second phase comparator 29
Is the first input signal and the fourth frequency divider 3 described later.
5 outputs a control output signal having a phase difference of 0 ° with the second input signal, and the control output signal is transmitted through the second loop filter 31 to the control terminal of the second VCO 33. And is controlled so that the output frequency of the second VCO 33 becomes the required frequency of 41.94304 MHz. Then, the output of the second VCO 33 is fed back, and 1/51 is output by the fourth frequency divider 35.
It is divided into two and becomes a second input signal to the second phase comparator 29.

【００１４】ここで、上記第２の位相比較器２９に入力
されるリファレンス周波数ｆｒ２が８１．９２ＫＨｚと
高い周波数に設定されているので、上記第２のＶＣＯ３
３の出力において発生するリファレンス周波数によるサ
イドスプリアスの周波数を所要周波数４１．９４３０４
ＭＨｚから離れた所に持ってくることができる。従っ
て、上記第２のループフィルタ３１のカットオフ周波数
を極端に低くする必要がなく、ＰＬＬ回路としての高速
な応答特性を維持しながら、図２に示す様に、上記サイ
ドスプリアスを充分に取り除くことができる。Since the reference frequency fr2 input to the second phase comparator 29 is set to a high frequency of 81.92 KHz, the second VCO3 is set.
The frequency of the side spurious generated by the reference frequency generated at the output of 3 is the required frequency of 41.94304
Can be brought away from MHz. Therefore, it is not necessary to extremely reduce the cutoff frequency of the second loop filter 31, and the side spurious is sufficiently removed as shown in FIG. 2 while maintaining the high-speed response characteristics of the PLL circuit. You can

【００１５】なお、上記中間的周波数５１．２ＭＨｚ
は、基準周波数５ＭＨｚ＝２6 ×５7と所要周波数４
１．９４３０４ＭＨｚ＝２23×５1 の周波数関係からい
ずれの周波数に対しても大きい公約数を持つように２n
×５m の形で求めることができる。本実施例ではｎ＝１
４、ｍ＝５として、５１．２ＭＨｚを設定している。The above intermediate frequency of 51.2 MHz
Is the reference frequency 5MHz = 2 6 × 5 7 and the required frequency 4
Due to the frequency relationship of 1.94304 MHz = 2 23 × 5 1 , 2 n should have a large common divisor for any frequency.
It can be obtained in the form of × 5 m . In this embodiment, n = 1
4 and m = 5, and 51.2 MHz is set.

【００１６】[0016]

【発明の効果】本発明は、以上説明したように、２つの
ＰＬＬ回路を直列に接続して、第１のＰＬＬ回路によっ
て一旦基準周波数信号から中間的周波数を得、第２のＰ
ＬＬ回路によって上記中間的周波数から所要周波数を得
る様にすると共に、上記中間的周波数の値を上記第１お
よび第２のＰＬＬ回路それぞれの位相比較器に入力され
るリファレンス周波数がそれぞれのループフィルタのカ
ットオフ周波数に比べて充分に高い周波数となる様に設
定して、サイドスプリアスを充分に抑制する様にしてい
るので、応答特性を高速のまま維持してサイドスプリア
スレベルを充分に抑圧することができる。As described above, according to the present invention, two PLL circuits are connected in series, the first PLL circuit temporarily obtains an intermediate frequency from the reference frequency signal, and the second P circuit is used.
The required frequency is obtained from the intermediate frequency by the LL circuit, and the value of the intermediate frequency is input to the phase comparator of each of the first and second PLL circuits and the reference frequency of each loop filter is The frequency is set to be sufficiently higher than the cut-off frequency so that the side spurious is sufficiently suppressed, so it is possible to maintain the high speed response characteristics and sufficiently suppress the side spurious level. it can.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明によるＰＬＬ回路の一実施例を示す構成
図である。FIG. 1 is a configuration diagram showing an embodiment of a PLL circuit according to the present invention.

【図２】図１に示したＰＬＬ回路における出力スペクト
ラムを示す説明図である。FIG. 2 is an explanatory diagram showing an output spectrum in the PLL circuit shown in FIG.

【図３】従来のＰＬＬ回路の一例を示す構成図である。FIG. 3 is a configuration diagram showing an example of a conventional PLL circuit.

【図４】図１に示したＰＬＬ回路における出力スペクト
ラムを示す説明図である。FIG. 4 is an explanatory diagram showing an output spectrum in the PLL circuit shown in FIG.

【図５】従来のＰＬＬ回路の他の例を示す構成図であ
る。FIG. 5 is a configuration diagram showing another example of a conventional PLL circuit.

【符号の説明】[Explanation of symbols]

１…第１の分周器１／Ｎ、 ３…位相比
較器、５…ループフィルタ、 ７…
ＶＣＯ、９…第２の分周器１／Ｎ、 １
１…ＬＰＦ、１３…第１のループフィルタ、
１５…第２のループフィルタ、１７…第１の分周器１
／Ｎ、 １９…第１の位相比較器、２１…
第１のループフィルタ、 ２３…第１のＶＣ
Ｏ、２５…第２の分周器１／Ｍ、 ２７…
第３の分周器１／Ｋ、２９…第２の位相比較器、
３１…第２のループフィルタ、３３…第２の
ＶＣＯ、 ３５…第４の分周器１／
Ｌ、1 ... 1st frequency divider 1 / N, 3 ... Phase comparator, 5 ... Loop filter, 7 ...
VCO, 9 ... Second frequency divider 1 / N, 1
1 ... LPF, 13 ... first loop filter,
15 ... Second loop filter, 17 ... First frequency divider 1
/ N, 19 ... First phase comparator, 21 ...
First loop filter, 23 ... First VC
O, 25 ... Second frequency divider 1 / M, 27 ...
Third frequency divider 1 / K, 29 ... second phase comparator,
31 ... 2nd loop filter, 33 ... 2nd VCO, 35 ... 4th frequency divider 1 /
L,

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 与えられた基準周波数の信号から、所要
の周波数の信号を合成するＰＬＬ回路であって、上記基
準周波数の信号から一旦中間的周波数の信号を合成する
第１の回路手段と、上記中間的周波数の信号から所要の
周波数の信号を合成する第２の回路手段とを具備し、上
記第１および第２の回路手段のそれぞれが、ループフィ
ルタおよび位相比較器を有し、上記ループフィルタのカ
ットオフ周波数に比べて上記位相比較器に入力されるリ
ファレンス周波数が十分に高くなる様に、上記中間的周
波数の値が設定されていることを特徴とするＰＬＬ回
路。1. A PLL circuit for synthesizing a signal of a required frequency from a signal of a given reference frequency, and first circuit means for synthesizing an intermediate frequency signal from the signal of the reference frequency, Second circuit means for synthesizing a signal of a desired frequency from the signal of the intermediate frequency, each of the first and second circuit means having a loop filter and a phase comparator, and the loop A PLL circuit in which the value of the intermediate frequency is set such that the reference frequency input to the phase comparator is sufficiently higher than the cutoff frequency of the filter. 【請求項２】 上記第１の回路手段が、上記基準周波数
の信号を分周する第１の分周器と、上記第１の分周器よ
りのレファレンス周波数から成る第１の入力信号と第２
の入力信号との位相差が０°となる様な制御出力信号を
出力する第１の位相比較器と、上記第１の位相比較器よ
りの制御出力信号をカットオフ周波数に従ってろ波する
第１のループフィルタと、上記第１のループフィルタよ
りの制御出力信号に従った中間的周波数信号を出力する
第１の電圧制御発振器（ＶＣＯ）と、上記第１のＶＣＯ
よりの出力信号を分周して上記第１の位相比較器へ第２
の入力信号として出力する第２の分周器とを有し、上記
第２の回路手段が、上記中間的周波数信号を分周する第
３の分周器と、上記第３の分周器よりのレファレンス周
波数から成る第１の入力信号と第２の入力信号との位相
差に対応した制御出力信号を出力する第２の位相比較器
と、上記第２の位相比較器よりの制御出力信号をカット
オフ周波数に従ってろ波する第２のループフィルタと、
上記第２のループフィルタよりの制御出力信号に従った
所要の周波数信号を出力する第２の電圧制御発振器（Ｖ
ＣＯ）と、上記第２のＶＣＯよりの出力信号を分周して
上記第２の位相比較器へ第２の入力信号として出力する
第４の分周器とを有することを特徴とする請求項１に記
載のＰＬＬ回路。2. The first circuit means divides a signal of the reference frequency by a first frequency divider, a first input signal composed of a reference frequency from the first frequency divider, and a first frequency divider. Two
A first phase comparator for outputting a control output signal having a phase difference of 0 ° from the input signal and a first output for filtering the control output signal from the first phase comparator according to a cutoff frequency. Loop filter, a first voltage controlled oscillator (VCO) for outputting an intermediate frequency signal according to the control output signal from the first loop filter, and the first VCO.
The output signal from the second frequency divider to the first phase comparator
A second frequency divider for outputting as an input signal of the third frequency divider, wherein the second circuit means divides the intermediate frequency signal by a third frequency divider and the third frequency divider. A second phase comparator for outputting a control output signal corresponding to the phase difference between the first input signal and the second input signal having the reference frequency of 2 and a control output signal from the second phase comparator. A second loop filter that filters according to the cutoff frequency,
A second voltage controlled oscillator (V that outputs a required frequency signal according to the control output signal from the second loop filter).
CO) and a fourth frequency divider for dividing the output signal from the second VCO and outputting it as a second input signal to the second phase comparator. The PLL circuit described in 1. 【請求項３】 与えられた基準周波数の信号から、所要
の周波数の信号を合成するＰＬＬ回路であって、２つの
ＰＬＬ回路を直列に接続し、第１のＰＬＬ回路で上記基
準周波数の信号から一旦中間的周波数の信号を合成し、
第２のＰＬＬ回路で上記中間的周波数の信号から所要の
周波数の信号を合成すると共に、上記各ＰＬＬ回路のル
ープフィルタのカットオフ周波数に比べて上記各ＰＬＬ
回路の位相比較器に入力されるリファレンス周波数が十
分高くなる様に、上記中間的周波数の値を設定したこと
を特徴とするＰＬＬ回路。3. A PLL circuit for synthesizing a signal of a required frequency from a signal of a given reference frequency, wherein two PLL circuits are connected in series, and a first PLL circuit converts the signal of the reference frequency. Once you synthesize the signal of intermediate frequency,
The second PLL circuit synthesizes a signal of a desired frequency from the signal of the intermediate frequency, and compares each of the PLLs with the cutoff frequency of the loop filter of each of the PLL circuits.
A PLL circuit in which the value of the intermediate frequency is set so that the reference frequency input to the phase comparator of the circuit becomes sufficiently high.
JP7158528A 1995-06-01 1995-06-01 Pll circuit Pending JPH08330956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7158528A JPH08330956A (en) 1995-06-01 1995-06-01 Pll circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7158528A JPH08330956A (en) 1995-06-01 1995-06-01 Pll circuit

Publications (1)

Publication Number Publication Date
JPH08330956A true JPH08330956A (en) 1996-12-13

Family

ID=15673710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7158528A Pending JPH08330956A (en) 1995-06-01 1995-06-01 Pll circuit

Country Status (1)

Country Link
JP (1) JPH08330956A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267917A (en) * 2000-03-23 2001-09-28 Toshiba Corp Local oscillation stabilizer
JP5840283B1 (en) * 2014-12-18 2016-01-06 古河電気工業株式会社 Receiver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267917A (en) * 2000-03-23 2001-09-28 Toshiba Corp Local oscillation stabilizer
JP5840283B1 (en) * 2014-12-18 2016-01-06 古河電気工業株式会社 Receiver

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