JP2926374B2 - Superheterodyne wireless device - Google Patents
Superheterodyne wireless deviceInfo
- Publication number
- JP2926374B2 JP2926374B2 JP17182892A JP17182892A JP2926374B2 JP 2926374 B2 JP2926374 B2 JP 2926374B2 JP 17182892 A JP17182892 A JP 17182892A JP 17182892 A JP17182892 A JP 17182892A JP 2926374 B2 JP2926374 B2 JP 2926374B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- pll
- mixer
- synthesizer
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Superheterodyne Receivers (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は少なくとも２段以上の周
波数変換段を有するスーパーヘテロダイン方式の無線装
置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superheterodyne radio apparatus having at least two frequency conversion stages.
【０００２】[0002]
【従来技術】図３は従来のダブルスーパーヘテロダイン
受信機の構成を示すブロック図である。図において、１
は高周波増幅器、２は第１ミキサ、３は第１中間周波フ
ィルタ、４は第１中間周波増幅器、５は第２ミキサ、６
は第２中間周波フィルタ、７は第２中間周波増幅器、８
は第１局部発振器、９は第２局部発振器、１０は検波回
路である。2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional double superheterodyne receiver. In the figure, 1
Is a high-frequency amplifier, 2 is a first mixer, 3 is a first intermediate frequency filter, 4 is a first intermediate frequency amplifier, 5 is a second mixer, 6
Is a second intermediate frequency filter, 7 is a second intermediate frequency amplifier, 8
Denotes a first local oscillator, 9 denotes a second local oscillator, and 10 denotes a detection circuit.
【０００３】上記構成のダブルスーパーヘテロダイン受
信機において、入力端ＩＮに受信された変調波は高周波
増幅器１で増幅され、第１ミキサ２で第１局部発振器８
からの局部発振出力と混合され、第１中間周波フィルタ
３を介して第１中間周波数信号となり、第１中間周波増
幅器４で増幅される。更に、第１中間周波数信号は第２
ミキサ５で第２局部発振器９からの局部発振出力で混合
され、第２中間周波フィルタ６を介して第２中間周波増
幅器７により増幅され、検波回路１０に加えられる。In the double superheterodyne receiver having the above configuration, the modulated wave received at the input terminal IN is amplified by the high-frequency amplifier 1 and the first local oscillator 8 is amplified by the first mixer 2.
The signal is mixed with the local oscillation output from the first intermediate frequency filter 3, becomes a first intermediate frequency signal via the first intermediate frequency filter 3, and is amplified by the first intermediate frequency amplifier 4. Further, the first intermediate frequency signal is
The signal is mixed by the mixer 5 with the local oscillation output from the second local oscillator 9, amplified by the second intermediate frequency amplifier 7 via the second intermediate frequency filter 6, and applied to the detection circuit 10.
【０００４】[0004]
【発明が解決しようとする課題】近年、デジタル方式自
動車電話等のＴＤＭＡ（Time Division Multiple Acces
s：時分割多重アクセス）通信を行う無線装置において
は、第１局部発振器として高速切換えの周波数シンセサ
イザが必要不可欠となり、この周波数シンセサイザを達
成するためにプリセット方式周波数シンセサイザ（１９
９０年 電子情報通信学会秋季大会 Ｂ−３０８）、マ
ルチ周波数シンセサイザ等種々の方式が提案されてい
る。しかしながらこれらはいずれも回路が大規模とな
り、消費電力が増大するという問題があった。In recent years, TDMA (Time Division Multiple Acces) such as a digital car telephone has been proposed.
s: Time-division multiple access) In a wireless device that performs communication, a high-speed switching frequency synthesizer is indispensable as a first local oscillator. To achieve this frequency synthesizer, a preset frequency synthesizer (19) is used.
1990, IEICE Autumn Conference B-308), and various systems such as a multi-frequency synthesizer have been proposed. However, each of these has a problem that the circuit becomes large-scale and power consumption increases.
【０００５】本発明は上述の点に鑑みてなされたもので
上記問題点を除去し、ロックアップタイムの高速化、並
びに回路の小型化、低消費電力化が可能なスーパーヘテ
ロダイン方式の無線装置を提供することを目的とするも
のである。[0005] The present invention is the above-mentioned problems was removed been made in view of the above, high-speed lock-up time, parallel
It is an object of the present invention to provide a superheterodyne wireless device capable of reducing the size and power consumption of a circuit .
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
本発明は、第１及び第２段の周波数変換部を具備するス
ーパーヘテロダイン方式の無線装置において、ＰＬＬ周
波数シンセサイザ、ミキサ、１台の固定発振器、分周器
を設け、固定発振器の発振出力をミキサを介してＰＬＬ
周波数シンセサイザに供給すると共に該ＰＬＬ周波数シ
ンセサイザの出力を該ミキサを介して該ＰＬＬ周波数シ
ンセサイザに帰還させてＰＬＬを構成し、該ＰＬＬ周波
数シンセサイザの出力周波数を第１段の周波数変換部に
局部発振周波数として供給すると共に、固定発振器の出
力周波数を分周器の所定の分周比で分周して第２段の周
波数変換部に局部発振周波数として供給することを特徴
とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a superheterodyne radio apparatus having first and second frequency converters in a PLL frequency synthesizer, a mixer, and a single fixed frequency converter. An oscillator and a frequency divider are provided, and the oscillation output of the fixed oscillator is connected to a PLL via a mixer.
The PLL frequency synthesizer is supplied to the frequency synthesizer and the output of the PLL frequency synthesizer is fed back to the PLL frequency synthesizer via the mixer to form a PLL. And the frequency of the output frequency of the fixed oscillator is divided by a predetermined frequency division ratio of the frequency divider and supplied to the second-stage frequency converter as a local oscillation frequency.
【０００７】[0007]
【作用】本発明は第１及び第２段の周波数変換部を具備
するスーパーヘテロダイン方式の無線装置において、１
段ローカル用のＰＬＬ周波数シンセサイザのＶＣＯの出
力周波数をある固定周波数でダウンコンバージョンし、
低い周波数としＰＬＬのループを組むようにすると、Ｖ
ＣＯの周波数変調感度は変わらないが分周比が小さくな
るためループゲインが大きくなり、その結果ロックアッ
プタイムが速くなる。また、このダウンコンバージョン
用の固定周波数を分周したものを第２段の周波数変換部
の局部発振周波数と等しくすれば、第２段の局部発振器
を削除でき、回路の小型化、低消費電力化を図ることが
できる。The present invention comprises first and second stage frequency converters.
In a super-heterodyne wireless device,
Down-converts the output frequency of the VCO of the PLL frequency synthesizer for stage local at a certain fixed frequency,
When a low frequency is used to form a PLL loop, V
Although the frequency modulation sensitivity of the CO does not change, the loop gain increases because the frequency division ratio decreases, resulting in a faster lock-up time. The frequency obtained by dividing the fixed frequency for down-conversion is converted to a second-stage frequency converter.
If the local oscillation frequency is equal to the local oscillation frequency, the second-stage local oscillator can be omitted, and the circuit can be reduced in size and power consumption can be reduced.
【０００８】[0008]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。図１は本発明のスーパーヘテロダイン方式の無線
装置の構成を示すブロック図である。本無線装置は高周
波増幅器１、第１ミキサ２、第１中間周波フィルタ３、
第１中間周波増幅器４、第２ミキサ５、第２中間周波フ
ィルタ６、第２中間周波増幅器７及び検波回路１０を具
備する点は図３のダブルスーパーヘテロダイン受信機の
構成と同じである。２１はＰＬＬ周波数シンセサイザ、
２２は第３ミキサ、２３は第１ＬＰＦ（ローパスフィル
タ）又はＢＰＦ（バンドパスフィルタ）、２４は固定発
振器、２５は分周器、２６は第２ＬＰＦ又はＢＰＦであ
る。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a superheterodyne wireless device according to the present invention. The wireless device includes a high-frequency amplifier 1, a first mixer 2, a first intermediate frequency filter 3,
The configuration including the first intermediate frequency amplifier 4, the second mixer 5, the second intermediate frequency filter 6, the second intermediate frequency amplifier 7, and the detection circuit 10 is the same as the configuration of the double superheterodyne receiver in FIG. 21 is a PLL frequency synthesizer,
22 is a third mixer, 23 is a first LPF (low-pass filter) or BPF (band-pass filter), 24 is a fixed oscillator, 25 is a frequency divider, and 26 is a second LPF or BPF.
【０００９】ＰＬＬ周波数シンセサイザ２１の出力は第
１ミキサ２と同時に第３ミキサ２２に供給され、第３ミ
キサ２２において、固定発振器２４からの発振出力でダ
ウンコンバージョンされ、必要に応じて第１ＬＰＦ又は
ＢＰＦにより不要波を除去した後、ＰＬＬシンセサイザ
２１に帰還させる。The output of the PLL frequency synthesizer 21 is supplied to the third mixer 22 at the same time as the first mixer 2, where the output is down-converted by the oscillation output from the fixed oscillator 24 and, if necessary, the first LPF or BPF After the unnecessary wave is removed, the signal is returned to the PLL synthesizer 21.
【００１０】ＰＬＬ周波数シンセサイザのロックアップ
タイムはＰＬＬの自然周波数ωnが大きい程速くなり、
自然周波数ωnはＰＬＬのループフィルが図２に示すよ
うなラグリードフィルタを用いた場合、次式で与えられ
る。 Ｋ：ループ利得係数 Ｎ：プログラマブルカウンタの分周比[0010] The lock-up time of the PLL frequency synthesizer is faster the greater the natural frequency ω n of the PLL,
The natural frequency ω n is given by the following equation when the lag-lead filter as shown in FIG. 2 is used as the loop fill of the PLL. K: Loop gain coefficient N: Division ratio of programmable counter
【００１１】また、ＰＬＬ周波数シンセサイザ２１の出
力周波数をｆ0、基準周波数ｆrとすると、出力周波数を
ｆ0は ｆ0＝Ｎ・ｆr （２） で表され、（１）及び（２）式より となる。本発明の場合、この出力周波数をｆ0をダウン
コンバージョンし低い周波数とすることで、自然周波数
ωnを大きくしロックアップタイムを高速にするもので
ある。Further, f 0 the output frequency of the PLL frequency synthesizer 21, when the reference frequency f r, the output frequency f 0 is represented by f 0 = N · f r ( 2), (1) and (2) From the formula Becomes In the case of the present invention, the natural frequency ω n is increased and the lock-up time is shortened by setting the output frequency to a low frequency by down-converting f 0 .
【００１２】一方、固定発振器２４の発振出力は第３ミ
キサ２２と同時に分周器２５にも供給され、分周器２５
においてＮ分周された後、必要に応じてＬＰＦ又はＢＰ
Ｆ２６で不要波を除去した後、第２ミキサ５に加えられ
る。このため従来必要であった第２局部発振器が不要と
なり、回路の小型化、低消費電力化を図ることができ
る。On the other hand, the oscillation output of the fixed oscillator 24 is also supplied to the frequency divider 25 at the same time as the third mixer 22.
After dividing by N in LPF or BP as necessary
After removing unnecessary waves in F26, the unnecessary waves are added to the second mixer 5. For this reason, the second local oscillator, which has been conventionally required, becomes unnecessary, and the circuit can be reduced in size and power consumption can be reduced.
【００１３】また、固定発振器２４の発振出力をＭ分周
し第３局部発振器以降の周波数や送信側の局部発振器の
周波数にすることで、各々の局部発振器を不要とし回路
の小型化、低消費電力化を図ることも可能である。Further, by dividing the oscillation output of the fixed oscillator 24 by M and setting the frequency after the third local oscillator or the frequency of the local oscillator on the transmission side, each local oscillator is not required, and the circuit can be reduced in size and the power consumption can be reduced. It is also possible to achieve electric power.
【００１４】[0014]
【発明の効果】以上説明したように本発明によれば下記
のような優れた効果がえられる。 （１）ＰＬＬ周波数シンセサイザの出力周波数を固定発
振器の出力周波数でダウンコンバージョンし低い周波数
とすることで、ＰＬＬの自然周波数ωnを大きくしロッ
クアップタイムを高速にすることができる。As described above, according to the present invention, the following excellent effects can be obtained. (1) By a down-conversion to low frequency output frequency of the fixed oscillator the output frequency of the PLL frequency synthesizer, the lock-up time by increasing the natural frequency omega n of the PLL can be faster.
【００１５】（２）１台の固定発振器の出力周波数を分
周器の所定の分周比で分周して第２の周波数変換部以降
に局部発振周波数として供給するので、複数の局部発振
器を必要とせず無線装置の小型化、低消費電力化が図れ
る。[0015] The output frequency of (2) one of the fixed oscillator minute
Since the frequency is divided by the predetermined frequency division ratio of the frequency divider and supplied as the local oscillation frequency to the second frequency conversion unit and thereafter, a plurality of local oscillators are not required, and the size and the power consumption of the wireless device can be reduced.
【図１】本発明のスーパーヘテロダイン方式の無線装置
の構成を示すブロック図である。FIG. 1 is a block diagram illustrating a configuration of a superheterodyne wireless device of the present invention.
【図２】ＰＬＬのループフィルの構成例を示す図であ
る。FIG. 2 is a diagram illustrating a configuration example of a loop fill of a PLL.
【図３】従来のダブルスーパーヘテロダイン受信機の構
成を示すブロック図である。FIG. 3 is a block diagram showing a configuration of a conventional double superheterodyne receiver.
１ 高周波増幅器 ２ 第１ミキサ ３ 第１中間周波フィルタ ４ 第１中間周波増幅器 ５ 第２ミキサ ６ 第２中間周波フィルタ ７ 第２中間周波増幅器 １０ 検波回路 ２１ ＰＬＬ周波数シンセサイザ ２２ 第３ミキサ ２３ 第１ＬＰＦ又はＢＰＦ ２４ 固定発振器 ２５ 分周器 ２６ 第２ＬＰＦ又はＢＰＦ DESCRIPTION OF SYMBOLS 1 High frequency amplifier 2 1st mixer 3 1st intermediate frequency filter 4 1st intermediate frequency amplifier 5 2nd mixer 6 2nd intermediate frequency filter 7 2nd intermediate frequency amplifier 10 Detection circuit 21 PLL frequency synthesizer 22 3rd mixer 23 1st LPF or BPF 24 Fixed oscillator 25 Divider 26 Second LPF or BPF
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H04B 1/26 - 1/28 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 6 , DB name) H04B 1/26-1/28
Claims (1)
るスーパーヘテロダイン方式の無線装置において、 ＰＬＬ周波数シンセサイザ、ミキサ、１台の固定発振
器、分周器を設け、 前記固定発振器の発振出力を前記ミキサを介してＰＬＬ
周波数シンセサイザに供給すると共に該ＰＬＬ周波数シ
ンセサイザの出力を該ミキサを介して該ＰＬＬ周波数シ
ンセサイザに帰還させてＰＬＬを構成し、該ＰＬＬ周波
数シンセサイザの出力周波数を前記第１段の周波数変換
部に局部発振周波数として供給すると共に、前記固定発
振器の出力周波数を前記分周器の所定の分周比で分周し
て前記第２段の周波数変換部に局部発振周波数として供
給することを特徴とするスーパーヘテロダイン方式の無
線装置。1. A superheterodyne radio apparatus comprising first and second stage frequency converters, comprising: a PLL frequency synthesizer, a mixer, one fixed oscillator, and a frequency divider ; To the PLL via the mixer
The PLL frequency synthesizer is supplied to the frequency synthesizer and the output of the PLL frequency synthesizer is fed back to the PLL frequency synthesizer through the mixer to form a PLL. A super-heterodyne circuit, wherein the frequency is supplied as a frequency, and the output frequency of the fixed oscillator is frequency-divided by a predetermined frequency division ratio of the frequency divider and supplied to the second-stage frequency converter as a local oscillation frequency. Wireless device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17182892A JP2926374B2 (en) | 1992-06-05 | 1992-06-05 | Superheterodyne wireless device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17182892A JP2926374B2 (en) | 1992-06-05 | 1992-06-05 | Superheterodyne wireless device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05344017A JPH05344017A (en) | 1993-12-24 |
| JP2926374B2 true JP2926374B2 (en) | 1999-07-28 |
Family
ID=15930500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17182892A Expired - Fee Related JP2926374B2 (en) | 1992-06-05 | 1992-06-05 | Superheterodyne wireless device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2926374B2 (en) |
-
1992
- 1992-06-05 JP JP17182892A patent/JP2926374B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05344017A (en) | 1993-12-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |