JPH0831580B2 - Integrated circuit layout design method - Google Patents
Integrated circuit layout design methodInfo
- Publication number
- JPH0831580B2 JPH0831580B2 JP62094425A JP9442587A JPH0831580B2 JP H0831580 B2 JPH0831580 B2 JP H0831580B2 JP 62094425 A JP62094425 A JP 62094425A JP 9442587 A JP9442587 A JP 9442587A JP H0831580 B2 JPH0831580 B2 JP H0831580B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- area
- integrated circuit
- functional
- uncompleted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は集積回路の配置設計方法に関し、特に大規模
なマスタースライス型の集積回路の配置設計に好適の集
積回路の配置設計方法に関する。The present invention relates to an integrated circuit layout design method, and more particularly to an integrated circuit layout design method suitable for layout design of a large-scale master slice type integrated circuit.
［従来の技術］ 第６図は従来の集積回路の配置設計方法を説明するた
めの半導体基板の模式的平面図である。半導体基板10に
は機能セル13が複数個並べられた複数個のセル列11が形
成されており、各セル列11は機能セル13の配列方向に直
交する方向に配置されている。各セル列11間には、配線
領域12が形成されている。[Prior Art] FIG. 6 is a schematic plan view of a semiconductor substrate for explaining a conventional layout designing method of an integrated circuit. A plurality of cell rows 11 in which a plurality of functional cells 13 are arranged are formed on the semiconductor substrate 10, and each cell row 11 is arranged in a direction orthogonal to the arrangement direction of the functional cells 13. A wiring region 12 is formed between each cell row 11.
従来、マスタースライス型大規模集積回路の設計にお
いては、論理接続情報において関係が深い機能セルが近
い位置におかれるように機能セルを配置した後、配線領
域12において概略的に配線している。Conventionally, in the design of a master slice type large-scale integrated circuit, after arranging the functional cells so that the functional cells that are closely related to each other in the logical connection information are located close to each other, the wiring is roughly performed in the wiring region 12.
［発明が解決しようとする問題点］ しかしながら、上述した従来の配置設計方法において
は、局所的に機能セルの配置が集中した場合に、配線が
混雑してしまうので、配線が配線領域の容量を超える事
態が発生し、そうすると、未完結配線が生じてしまうと
いう欠点がある。[Problems to be Solved by the Invention] However, in the above-described conventional layout design method, when the layout of the functional cells is locally concentrated, the wiring becomes congested, so that the wiring reduces the capacity of the wiring area. There is a drawback that the situation will be exceeded, and if this happens, uncompleted wiring will occur.
この発明はかかる事情に鑑みてなされたものであっ
て、機能セルの配置が集中しても、配線の混雑が緩和さ
れ、未完結配線の発生が回避される集積回路の配置設計
方法を提供することを目的とする。The present invention has been made in view of the above circumstances, and provides a layout designing method of an integrated circuit in which congestion of wirings is alleviated and the occurrence of uncompleted wirings is avoided even if the layout of functional cells is concentrated. The purpose is to
［問題点を解決するための手段］ 本発明による方法は、複数の機能セルを機能セルに配
置し、配線領域にて各機能セルを配線して所望の論理機
能を有する集積回路を設計する集積回路の配置設計方法
において、機能セルを配置、配線するステップと、配線
が混雑して未完結配線が発生している箇所を調べるステ
ップと、未完結配線が発生している箇所の近傍に配置禁
止領域を設定して配線領域を確保するステップと、再び
機能セルを配置しなおし未完結配線が無くなるまでこれ
らの処理を繰り返すステップとを有することを特徴とし
ている。[Means for Solving the Problems] According to the method of the present invention, a plurality of functional cells are arranged in the functional cells, and each functional cell is wired in a wiring area to design an integrated circuit having a desired logic function. In the circuit layout design method, the step of arranging and wiring functional cells, the step of checking the place where uncompleted wiring is generated due to congestion of wiring, and the placement prohibition in the vicinity of the place where uncompleted wiring occurs The method is characterized by including a step of setting an area and securing a wiring area, and a step of rearranging the functional cells again and repeating these processes until there is no uncompleted wiring.
［作用］ この発明においては、機能セル領域に機能セルを配置
し、配線領域にて配線した後に、機能セルの配置と配線
の混雑度を調べ、所定の混雑度を超えるか未完結配線が
生じている場合に、機能セル領域内に機能セル配置禁止
の領域を確保する。そして、この配置禁止領域を配線領
域に変更した後、再度機能セルを配置していくから、配
線の混雑が解消され、未完結配線を回避することができ
る。[Operation] In the present invention, after the functional cells are arranged in the functional cell area and wired in the wiring area, the arrangement of the functional cells and the congestion degree of the wiring are examined, and a predetermined congestion degree is exceeded or uncompleted wiring occurs. In this case, a functional cell placement prohibited area is secured in the functional cell area. Then, after changing the placement prohibited area to the wiring area, the functional cells are placed again, so that the congestion of the wiring is eliminated and the uncompleted wiring can be avoided.
［実施例］ 次に、本発明の実施例について添付の図面を参照して
説明する。第１図は本発明方法の処理の流れを示すフロ
ーチャート図である。先ず、機能セルを配置した後（ス
テップ１）、配線を行う（ステップ２）。次いで、配線
が配線領域の容量をオーバーフローしているか否かを調
べる（ステップ３）。そして、未完結配線がある場合に
は、その近傍の機能セル領域内に配置禁止の領域を作り
（ステップ４）、再び配置からやり直す（ステップ
１）。この処理を未完結配線が無くなるまで繰り返す。[Embodiment] Next, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a flow chart showing the flow of processing of the method of the present invention. First, after arranging the functional cells (step 1), wiring is performed (step 2). Next, it is checked whether or not the wiring overflows the capacity of the wiring area (step 3). Then, if there is an uncompleted wiring, an area where the placement is prohibited is created in the functional cell area in the vicinity thereof (step 4), and the placement is started again (step 1). This process is repeated until there are no uncompleted wirings.
次に、この発明の実施例について、第２図に示す半導
体基板21の平面図を参照して具体的に説明する。この半
導体基板21上に、複数個の機能セル領域22が適宜の間隔
をおいて配列されている。この各機能セル領域22間に
は、配線領域23が配設されている。第３図は第２図の円
にて示す領域24の拡大図である。この第３図に示すよう
に、各機能セル領域22においては、複数個の機能セル25
が機能セル領域22の長手方向に配置される。Next, an embodiment of the present invention will be specifically described with reference to the plan view of the semiconductor substrate 21 shown in FIG. A plurality of functional cell regions 22 are arranged on the semiconductor substrate 21 at appropriate intervals. A wiring region 23 is arranged between the functional cell regions 22. FIG. 3 is an enlarged view of the area 24 indicated by the circle in FIG. As shown in FIG. 3, a plurality of functional cells 25 are provided in each functional cell region 22.
Are arranged in the longitudinal direction of the functional cell region 22.
この発明においては、領域24において、機能セル25が
集中して配線が混雑し、端子27と端子28との間の配線
（破線にて示す）が未完結である場合には、例えば、領
域26を機能セルの配置禁止領域とする。In the present invention, when the functional cells 25 are concentrated in the area 24 and the wiring is crowded and the wiring between the terminals 27 and 28 (shown by the broken line) is not completed, for example, the area 26 Is the area where the placement of functional cells is prohibited.
次いで、この配置禁止領域を配線領域に変更して、再
度、機能セルの配置及び配線を設計する。そうすると、
第４図に配置・配線のレイアウト図を示すように、確保
した配置禁止領域26を配線領域とすることで、配線29を
引くことができる。これにより、未完結配線が解消され
る。そして、他の領域にも未完結配線が生じていない場
合に、機能セルの配置及び配線の設計を終了する。Next, the placement prohibited area is changed to the wiring area, and the layout and wiring of the functional cell are designed again. Then,
As shown in the layout / wiring layout diagram in FIG. 4, the wiring 29 can be drawn by using the secured layout prohibited area 26 as a wiring area. This eliminates uncompleted wiring. Then, when the uncompleted wiring does not occur in other areas, the layout of the functional cells and the wiring design are completed.
なお、第５図のレイアウト図に示すように、配置禁止
領域26に配線29を引いて配置設計をした結果、なお、領
域30の周辺に未完結配線が生じている場合には、この領
域30を配置禁止領域とし、この領域30を配線領域に変更
して、再度機能セルの配置と配線とを実施する。As shown in the layout diagram of FIG. 5, when wiring 29 is drawn in the layout prohibited area 26 to perform layout design, and when uncompleted wiring is generated around the area 30, this area 30 Is set as a placement prohibited region, this region 30 is changed to a wiring region, and the placement and wiring of the functional cell are performed again.
このような操作を繰り返し、全ての領域に未完結配線
が解消された場合に、配置・配線設計を終了する。Such operations are repeated, and when the uncompleted wiring is eliminated in all areas, the layout / wiring design is finished.
［発明の効果］ 以上説明したように本発明によれば、機能セルが集中
しかつ配線が混雑してしまい未完結配線が生じている部
分に配置禁止の領域を設け、この配置禁止領域を配線領
域に変更する。これにより、従前の配置終了時点では機
能セルが置かれて配線することができなかった場所に配
線することが可能になるので、再度配置・配線をやり直
した後に、配線の局所的混雑が解消され、未完結配線が
回避される。更に、製造する集積回路に応じて機能セル
配置領域と配線専用領域を最適に設定できるため、機能
が異なる個々の集積回路に対して最小の面積で製造する
ことができるという格別の効果を奏するものです。ま
た、配線専用領域と機能セル領域の配置関係を最適に設
定できるため、機能セル間を接続する配線長を短くでき
るため、配線遅延の少ない高速な集積回路を製造できる
という大きな効果を奏す得る。EFFECTS OF THE INVENTION As described above, according to the present invention, a placement prohibited area is provided in a portion where functional cells are concentrated and wiring is congested to cause uncompleted wiring. Change to the area. As a result, it becomes possible to wire to a place where functional cells were placed and could not be wired at the end of the previous layout, so after arranging and wiring again, local congestion of wiring is eliminated. , Incomplete wiring is avoided. Further, since the functional cell placement area and the wiring exclusive area can be optimally set according to the integrated circuit to be manufactured, the particular effect that the integrated circuit can be manufactured with the minimum area for individual integrated circuits having different functions is obtained. is. Further, since the layout relationship between the dedicated wiring area and the functional cell area can be optimally set, the length of the wiring connecting the functional cells can be shortened, and a large effect that a high-speed integrated circuit with a small wiring delay can be manufactured can be obtained.
第１図は本発明の処理の流れを示すフローチャート図、
第２図は半導体基板の模式的平面図、第３図は第２図の
円領域24の拡大図、第４図及び第５図は配置・配線のレ
イアウト図、第６図は従来の方法を示す半導体基板の模
式的平面図である。 1,10;半導体基板、11,22;機能セル領域、12,23;配線領
域、13,25;機能セル、26,30;配置禁止領域、27,28;端
子、29;配線FIG. 1 is a flow chart showing the flow of processing of the present invention,
2 is a schematic plan view of the semiconductor substrate, FIG. 3 is an enlarged view of the circular area 24 of FIG. 2, FIGS. 4 and 5 are layout and wiring layout diagrams, and FIG. 6 is a conventional method. It is a schematic plan view of the semiconductor substrate shown. 1,10; semiconductor substrate, 11,22; functional cell region, 12,23; wiring region, 13,25; functional cell, 26,30; placement prohibited region, 27,28; terminal, 29; wiring
Claims (1)
領域にて各機能セルを配線して所望の論理機能を有する
集積回路を設計する集積回路の配置設計方法において、
機能セルを配置、配線するステップと、配線が混雑して
未完結配線が発生している箇所を調べるステップと、未
完結配線が発生している箇所の近傍に配置禁止領域を設
定して配線領域を確保するステップと、再び機能セルを
配置しなおし未完結配線が無くなるまでこれらの処理を
繰り返すステップとを有する集積回路の配置設計方法。1. An integrated circuit layout design method for arranging a plurality of functional cells in a functional cell and wiring each functional cell in a wiring area to design an integrated circuit having a desired logical function,
Place and route functional cells, check the location where uncompleted wiring is generated due to congestion of wiring, and set the prohibited area in the vicinity of the location where uncompleted wiring occurs and set the wiring area And a step of relocating the functional cells and repeating these processes until there are no uncompleted wirings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62094425A JPH0831580B2 (en) | 1987-04-17 | 1987-04-17 | Integrated circuit layout design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62094425A JPH0831580B2 (en) | 1987-04-17 | 1987-04-17 | Integrated circuit layout design method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63260150A JPS63260150A (en) | 1988-10-27 |
| JPH0831580B2 true JPH0831580B2 (en) | 1996-03-27 |
Family
ID=14109876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62094425A Expired - Lifetime JPH0831580B2 (en) | 1987-04-17 | 1987-04-17 | Integrated circuit layout design method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0831580B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152437A (en) * | 1991-11-29 | 1993-06-18 | Kawasaki Steel Corp | Layout-wiring method |
| JP3564295B2 (en) | 1998-05-22 | 2004-09-08 | 富士通株式会社 | Cell arrangement apparatus and method, and computer-readable recording medium recording cell arrangement program |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58200570A (en) * | 1982-05-19 | 1983-11-22 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1987
- 1987-04-17 JP JP62094425A patent/JPH0831580B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63260150A (en) | 1988-10-27 |
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