JPS63260150A - Method of designing arrangement of integrated circuit - Google Patents
Method of designing arrangement of integrated circuitInfo
- Publication number
- JPS63260150A JPS63260150A JP9442587A JP9442587A JPS63260150A JP S63260150 A JPS63260150 A JP S63260150A JP 9442587 A JP9442587 A JP 9442587A JP 9442587 A JP9442587 A JP 9442587A JP S63260150 A JPS63260150 A JP S63260150A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- region
- area
- functional
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 13
- 230000005764 inhibitory process Effects 0.000 abstract 4
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は集積回路の配Ｉ！設計方法に関し、特に大規模
なマスタースライス型の集積回路の配置設計に好適の集
積回路の配Ｉ！設計方法に関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention is directed to the arrangement of integrated circuits. Regarding the design method, I! Regarding design methods.
［従来の技術１
第６図は従来の集積回路の配置設計方法を説明するため
の半導体基板の模式的平面図である。半導体基板１０に
は機能セル１３が複数個並べられた複数個のセル列１１
が形成されており、各セル列１１は機能セル１３の配列
方向に直交する方向に配置されている。各セル列１１＆
ｌには、配１ｌＡＷＡ域１２が形成されている。[Prior Art 1] FIG. 6 is a schematic plan view of a semiconductor substrate for explaining a conventional integrated circuit layout design method. The semiconductor substrate 10 has a plurality of cell rows 11 in which a plurality of functional cells 13 are arranged.
are formed, and each cell row 11 is arranged in a direction perpendicular to the arrangement direction of the functional cells 13. Each cell column 11&
A distribution 11AWA area 12 is formed in the area 1.
従来、マスタースライス型大規模集積回路の設計におい
ては、論理接続情報において関係が深い機能セルが近い
位置におかれるように機能セルを配置した後、配ｍ領域
１２において概略的に配線している。Conventionally, in the design of a master slice type large-scale integrated circuit, functional cells are arranged so that functional cells that are closely related in terms of logical connection information are placed in close positions, and then wiring is roughly performed in the m-layout area 12. .
［発明が解決しようとする問題点１
しかしながら、上述した従来の配置設計方法においては
、局所的に機能セルの配置が集中した場合に、配線が混
雑してしまうので、ｉ！ｉ！線が配線領域の容量を超え
る事態が発生し、そうすると、未完結配線が生じてしま
うという欠点がある。[Problem to be Solved by the Invention 1] However, in the conventional layout design method described above, when the placement of functional cells is concentrated locally, the wiring becomes crowded, so i! i! There is a problem that a situation occurs in which the line exceeds the capacity of the wiring area, resulting in unfinished wiring.
この発明はかかる事情に鑑みてなされたものであって、
機能セルの配置が集中しても、配線の混雑が緩和され、
未完結配線の発生が回避される集積回路の配置設計方法
を提供することを目的とする。This invention was made in view of such circumstances, and
Even if functional cells are concentrated, wiring congestion is alleviated.
An object of the present invention is to provide an integrated circuit layout design method that avoids the occurrence of unfinished wiring.
［問題点を解決するための手段］
本発明に係る集積回路の配置設計方法は、複数の機能セ
ルを機能セル領域に配置し、配線領域にて各機能セルを
配線して所望の論理機能を有する集積回路を設計する集
積回路の配置設計方法において、機能セルが集中しかつ
配線が混雑した場合に、機能セル領域内に機能セル配置
禁止の領域を確保し、この配置禁止領域を配線領域に変
更した後、再度機能セルを配置することを特徴とする。[Means for Solving the Problems] The integrated circuit layout design method according to the present invention arranges a plurality of functional cells in a functional cell area, and wires each functional cell in a wiring area to achieve a desired logical function. In an integrated circuit layout design method for designing integrated circuits with a large number of functional cells, when functional cells are concentrated and wiring is congested, an area where functional cell placement is prohibited is secured within the functional cell area, and this placement prohibited area is converted into a wiring area. The feature is that after the change, the functional cells are placed again.
［作用］
この発明においては、機能セル領域に機能セルを配置し
、配線領域にて配線した後に、機能セルの配置と配線の
混雑度を調べ、所定の混雑度を超えるか未完結配線が生
じている場合に、機能セル領域内に機能セル配置禁止の
領域を確保する。そして、この配置禁止領域を配線領域
に変更した後、再度機能セルを配置していくから、配線
の混雑が解消され、未完結配線を回避することができる
。[Operation] In the present invention, after placing functional cells in the functional cell area and wiring in the wiring area, the placement of the functional cells and the degree of congestion of the wiring are checked, and it is determined whether the degree of congestion exceeds a predetermined degree or unfinished wiring occurs. In this case, an area where functional cell placement is prohibited is secured within the functional cell area. Then, after changing this placement-prohibited area to a wiring area, functional cells are placed again, which eliminates wiring congestion and avoids unfinished wiring.
［実施例］
次に、本発明の実施例について添付の図面を参照して説
明する。第１図は本発明方法の処理の流れを示すフロー
チャート図である。先ず、機能セルを配置した後（ステ
ップ１）、配線を行う（ステップ２）。次いで、配線が
配線領域の容量をオーバーフローしているか否かを調べ
る（ステップ３）。そして、未完結配線がある場合には
、その近傍の機能セル領域内に配置禁止の領域を作り（
ステップ４）、再び配置からやり直す（ステップ１）。[Example] Next, an example of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a flowchart showing the processing flow of the method of the present invention. First, after arranging functional cells (step 1), wiring is performed (step 2). Next, it is checked whether the wiring overflows the capacitance of the wiring area (step 3). If there is an unfinished wiring, create an area where placement is prohibited in the functional cell area near it (
Step 4), start over from the arrangement again (Step 1).
この処理を未完結配線が無くなるまで繰り返す。This process is repeated until there are no more unfinished wires.
次に、この発明の実施例について、第２図に示す半導体
基板２１の平面図を参照して具体的に説明する。この半
導体基板２１上に、複数個の機能セル領域２２が適宜の
間隔をおいて配列されている。この各機能セル領域２２
間には、配線領域２３が配設されている。第３図は第２
図の円にて示す領域２４の拡大図である。この第３図に
示すように、各機能セル領域２２においては、複数個の
機能セル２５が機能セル領域２２の長手方向に配置され
る。Next, an embodiment of the present invention will be specifically described with reference to a plan view of the semiconductor substrate 21 shown in FIG. A plurality of functional cell regions 22 are arranged on this semiconductor substrate 21 at appropriate intervals. Each functional cell area 22
A wiring area 23 is provided in between. Figure 3 is the second
It is an enlarged view of the area 24 indicated by the circle in the figure. As shown in FIG. 3, in each functional cell area 22, a plurality of functional cells 25 are arranged in the longitudinal direction of the functional cell area 22. As shown in FIG.
この発明においては、領域２４において、機能セル２５
が集中して配線が混雑し、端子２７と端子２８との間の
配線（破線にて示す）が未完結である場合には、例えば
、領域２６を機能セルの配置禁止領域とする。In this invention, in the region 24, the functional cell 25
If the wiring is congested and the wiring between the terminals 27 and 28 (indicated by a broken line) is incomplete, for example, the area 26 is set as a prohibited area for placing functional cells.
次いで、この配置禁止領域を配線領域に変更して、再度
、機能セルの配置及び配線を設計する。Next, this placement prohibited area is changed to a wiring area, and the placement and wiring of the functional cells are designed again.
そうすると、第４図に配置・配線のレイアウト図を示す
ように、確保した配置禁止領域２６を配線領域とするこ
とで、配置！２９を引くことができる。Then, as shown in the layout diagram of placement and wiring in FIG. 4, by making the secured placement prohibited area 26 a wiring area, placement is possible! You can subtract 29.
これにより、未完結配線が解消される。そして、他の領
域にも未完結配線が生じていない場合に、機能セルの配
置及び配線の設計を終了する。This eliminates unfinished wiring. Then, when no unfinished wiring occurs in other areas, the functional cell placement and wiring design are completed.
なお、第５図のレイアウト図に示すように、配置禁止領
域２６に配線２９を引いて配置設計をした結果、なお、
領域３０の周辺に未完結配線が生じている場合には、こ
の領域３０を配置禁止領域とし、この領域３０を配線領
域に変更して、再度機能セルの配置と配線とを実施する
。As shown in the layout diagram of FIG. 5, as a result of drawing the wiring 29 in the prohibited area 26 and designing the layout,
If unfinished wiring occurs around area 30, this area 30 is set as a placement prohibited area, this area 30 is changed to a wiring area, and functional cell placement and wiring are performed again.
このような操作を繰り返し、全ての領域に未完結配線が
解消された場合に、配置・配線設計を終了する。By repeating such operations, the placement and wiring design is completed when unfinished wiring is eliminated in all areas.
［発明の効果］
以上説明したように本発明によれば、機能セルが集中し
かつ配線が混雑してしまい未完結配線が生じている部分
に配置禁止の領域を設け、この配置禁止領域を配線領域
に変更する。これにより、従前の配置終了時点では機能
セルが置かれて配線することができなかった場所に配線
することが可能になるので、再度配置・配線をやり直し
た後に、配線の局所的混雑が解消され、未完線配線が回
避される。[Effects of the Invention] As explained above, according to the present invention, an area where placement is prohibited is provided in a portion where functional cells are concentrated and wiring is congested, resulting in unfinished wiring, and this placement prohibited area is used for wiring. Change to area. This makes it possible to route wiring to locations where functional cells were placed and could not be routed when the previous placement was completed, so local congestion in the wiring can be resolved after redoing the placement and routing. , unfinished line wiring is avoided.
【図面の簡単な説明】
第１図は本発明の処理の流れを示すフローチャート図、
第２図は半導体基板の模式的平面図、第３図は第２図の
円領域２４の拡大図、第４図及び第５図は配置・配線の
レイアウト図、第６図は従来の方法を示す半導体基板の
模式的平面図である。
１．１０：半導体基板、１１．２２：機能セル領域、１
２，２３：配線領域、１３．２５：機能セル、２６，３
０：配置禁止領域、２７．２８：端子、２９：配線
第１図
第２図
第３図
第６図[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a flowchart showing the process flow of the present invention;
FIG. 2 is a schematic plan view of the semiconductor substrate, FIG. 3 is an enlarged view of the circular area 24 in FIG. 2, FIGS. 4 and 5 are layout diagrams of arrangement and wiring, and FIG. FIG. 2 is a schematic plan view of a semiconductor substrate shown in FIG. 1.10: Semiconductor substrate, 11.22: Functional cell area, 1
2, 23: Wiring area, 13.25: Functional cell, 26, 3
0: Placement prohibited area, 27.28: Terminal, 29: Wiring Figure 1 Figure 2 Figure 3 Figure 6
Claims (1)
各機能セルを配線して所望の論理機能を有する集積回路
を設計する集積回路の配置設計方法において、機能セル
が集中しかつ配線が混雑した場合に、機能セル領域内に
機能セル配置禁止の領域を確保し、この配置禁止領域を
配線領域に変更した後、再度機能セルを配置することを
特徴とする集積回路の配置設計方法。In an integrated circuit layout design method in which a plurality of functional cells are placed in a functional cell area and each functional cell is wired in a wiring area to design an integrated circuit having a desired logical function, the functional cells are concentrated and the wiring is A layout design method for an integrated circuit characterized in that, in the case of congestion, an area where functional cell placement is prohibited is secured in a functional cell area, this placement prohibited area is changed to a wiring area, and then functional cells are placed again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62094425A JPH0831580B2 (en) | 1987-04-17 | 1987-04-17 | Integrated circuit layout design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62094425A JPH0831580B2 (en) | 1987-04-17 | 1987-04-17 | Integrated circuit layout design method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63260150A true JPS63260150A (en) | 1988-10-27 |
| JPH0831580B2 JPH0831580B2 (en) | 1996-03-27 |
Family
ID=14109876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62094425A Expired - Lifetime JPH0831580B2 (en) | 1987-04-17 | 1987-04-17 | Integrated circuit layout design method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0831580B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152437A (en) * | 1991-11-29 | 1993-06-18 | Kawasaki Steel Corp | Layout-wiring method |
| US6327694B1 (en) | 1998-05-22 | 2001-12-04 | Fujitsu Limited | Cell placement apparatus and method, and computer readable record medium having cell placement program recorded thereon |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58200570A (en) * | 1982-05-19 | 1983-11-22 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1987
- 1987-04-17 JP JP62094425A patent/JPH0831580B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58200570A (en) * | 1982-05-19 | 1983-11-22 | Hitachi Ltd | Semiconductor integrated circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152437A (en) * | 1991-11-29 | 1993-06-18 | Kawasaki Steel Corp | Layout-wiring method |
| US6327694B1 (en) | 1998-05-22 | 2001-12-04 | Fujitsu Limited | Cell placement apparatus and method, and computer readable record medium having cell placement program recorded thereon |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0831580B2 (en) | 1996-03-27 |
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