JPH08167738A - Semiconductor light emitting element - Google Patents
Semiconductor light emitting elementInfo
- Publication number
- JPH08167738A JPH08167738A JP33294694A JP33294694A JPH08167738A JP H08167738 A JPH08167738 A JP H08167738A JP 33294694 A JP33294694 A JP 33294694A JP 33294694 A JP33294694 A JP 33294694A JP H08167738 A JPH08167738 A JP H08167738A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- current blocking
- light emitting
- semiconductor substrate
- blocking layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体発光素子に関し、
更に詳細には半導体発光素子の発光効率向上を実現する
ための構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device,
More specifically, it relates to a structure for improving the luminous efficiency of a semiconductor light emitting device.
【０００２】[0002]
【従来の技術】例えばＡｌＧａＩｎＰから成る活性層を
クラッド層によって挾んだダブルヘテロ構造部を備えた
半導体発光ダイオードは公知である。この種の発光ダイ
オードは図１に示すように、ｎ形（第１導電形）ＧａＡ
ｓ基板層１とｎ形ＧａＡｓバッファ層２とｎ形ＡｌＧａ
ＩｎＰクラッド層３とＡｌＧａＩｎＰ活性層４とｐ形
（第２導電形）ＡｌＧａＩｎＰクラッド層５とｎ形Ａｌ
ＧａＩｎＰ電流ブロック層６とｐ形ＡｌＧａＡｓコンタ
クト層７が順次に積層された半導体基板と、コンタクト
層７の上面に形成されたアノード電極（第１の電極）８
と、ＧａＡｓ基板層１の下面に形成されたカソード電極
（第２の電極）９とから成る。なお、電流ブロック層６
はｐ形クラッド層５の上に部分的に形成され、平面的に
見てアノード電極８の下方に形成されている。この電流
ブロック層６はアノード電極８から流れる電流を素子の
周辺側に拡げて光の取り出し効率を向上させるように機
能する。即ち、もし、電流ブロック層６が形成されない
構造とすると、電極８から流れる電流はコンタクト層７
及びクラッド層５ではあまり拡がらず、電極８の直下の
活性層４に注入され、主たる発光領域がアノード電極８
の直下に生じる。このように発光領域がアノード電極８
の直下に生じると、発光領域で発生した光がアノード電
極８によって遮られて光取り出し効率が小さくなる。こ
れに対し、電流ブロック層６を図１に示すように形成す
ると、電流Ｉは矢印で示すように電流ブロック層６の外
側に流れ、主たる発光領域が平面的に見てアノード電極
８の外側に移動する。この結果、光取り出し効率の向上
が実現される。2. Description of the Related Art A semiconductor light emitting diode having a double heterostructure portion in which an active layer made of, for example, AlGaInP is sandwiched by cladding layers is known. This type of light emitting diode has an n-type (first conductivity type) GaA as shown in FIG.
Substrate layer 1, n-type GaAs buffer layer 2, and n-type AlGa
InP clad layer 3, AlGaInP active layer 4, p-type (second conductivity type) AlGaInP clad layer 5, and n-type Al
A semiconductor substrate in which a GaInP current blocking layer 6 and a p-type AlGaAs contact layer 7 are sequentially stacked, and an anode electrode (first electrode) 8 formed on the upper surface of the contact layer 7.
And a cathode electrode (second electrode) 9 formed on the lower surface of the GaAs substrate layer 1. The current blocking layer 6
Is partially formed on the p-type clad layer 5 and is formed below the anode electrode 8 in plan view. The current blocking layer 6 functions to spread the current flowing from the anode electrode 8 to the peripheral side of the device and improve the light extraction efficiency. That is, if the structure is such that the current blocking layer 6 is not formed, the current flowing from the electrode 8 is generated by the contact layer 7.
And the clad layer 5 does not spread so much and is injected into the active layer 4 immediately below the electrode 8 so that the main light emitting region is the anode electrode 8
Occurs directly below. In this way, the light emitting region is the anode electrode 8
When the light is generated immediately below, the light generated in the light emitting region is blocked by the anode electrode 8 and the light extraction efficiency decreases. On the other hand, when the current blocking layer 6 is formed as shown in FIG. 1, the current I flows to the outside of the current blocking layer 6 as shown by the arrow, and the main light emitting region is located outside the anode electrode 8 when viewed in plan. Moving. As a result, the light extraction efficiency is improved.
【０００３】[0003]
【発明が解決しようとする課題】ところで、図１に示す
半導体素子において、半導体基板の表面（側面／上面の
光取り出し面）を粗面化すると、半導体発光素子とこれ
を被覆する封止体との界面における全反射が減少し、光
を半導体素子の外部に効率良く取り出すことができ、光
取り出し効率が向上する。By the way, in the semiconductor element shown in FIG. 1, when the surface (side surface / top surface light extraction surface) of the semiconductor substrate is roughened, the semiconductor light emitting element and the sealing body for covering the same are formed. The total reflection at the interface is reduced, light can be efficiently extracted to the outside of the semiconductor element, and the light extraction efficiency is improved.
【０００４】しかしながら、この素子表面の粗面化は光
取り出し効率の向上が期待される一方、半導体基板の側
面付近での非発光再結合の増大をもたらすため、期待さ
れる程に発光効率の向上が図れないのが実状であった。
これを図４を参照して詳しく説明する。アノード電極８
とカソード電極９との間の電流Ｉと発光の光度Ｌとを対
数目盛で示す図４において、特性線Ａは半導体基板の表
面を粗面化しない通常の発光ダイオードの特性を示し、
特性線Ｂは半導体基板の表面を粗面化した発光ダイオー
ドの特性を示し、特性線Ｃは後述する本発明の実施例の
発光ダイオードの特性を示す。粗面化しない発光ダイオ
ードの特性線Ａと粗面化した発光ダイオードの特性線Ｂ
との比較から明らかなように、粗面化すると大電流領域
では、粗面化による光取り出し効果の増大の効果が発揮
され、高光度化が可能であるが、比較的小電流の領域で
は、粗面化に伴う非発光再結合による影響の方が粗面化
による光取り出し効率向上の効果よりも支配的となり、
粗面化を行わない素子よりも光度は低下してしまう。今
日では、この比較的小電流の領域での高光度化が特に望
まれている。また、粗面化した素子で比較的小電流の領
域での高光度化も図れるならば１つの粗面化した素子で
幅広い用途に供することができ、好都合である。However, while the roughening of the device surface is expected to improve the light extraction efficiency, it causes an increase in non-radiative recombination in the vicinity of the side surface of the semiconductor substrate, so that the emission efficiency is improved as expected. The reality is that this cannot be achieved.
This will be described in detail with reference to FIG. Anode electrode 8
In FIG. 4 showing the current I between the cathode electrode 9 and the cathode electrode 9 and the luminous intensity L of the light emission on a logarithmic scale, the characteristic line A shows the characteristic of a normal light emitting diode in which the surface of the semiconductor substrate is not roughened,
A characteristic line B shows the characteristics of the light emitting diode in which the surface of the semiconductor substrate is roughened, and a characteristic line C shows the characteristics of the light emitting diode of the embodiment of the present invention described later. Characteristic line A of a light-emitting diode not roughened and characteristic line B of a light-emitting diode roughened
As is clear from the comparison with, when roughening the surface, in the large current region, the effect of increasing the light extraction effect due to the roughening is exerted, and high luminous intensity is possible, but in the relatively small current region, The effect of non-radiative recombination due to roughening becomes more dominant than the effect of improving light extraction efficiency due to roughening,
The luminous intensity is lower than that of an element not roughened. Nowadays, it is particularly desired to increase the luminous intensity in this relatively small current region. In addition, if the roughened element can achieve high luminous intensity in a relatively small current region, one roughened element can be used for a wide range of applications, which is convenient.
【０００５】そこで、本発明の目的は、低電流領域の光
度を高めることができる半導体発光素子を提供すること
にある。Therefore, an object of the present invention is to provide a semiconductor light emitting device capable of increasing the luminous intensity in a low current region.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
の本発明は、少なくとも第１導電形のクラッド層と活性
層と前記第１導電形と反対の第２導電形のクラッド層と
第１導電形の電流ブロック層と第２導電形のコンタクト
層とが順に配置された半導体基板と、前記半導体基板の
一方の主面で前記コンタクト層に接続された第１の電極
と、前記半導体基板の他方の主面に配設され且つ前記第
１導電形のクラッド層に電気的に接続された第２の電極
とを備えた半導体発光素子において、前記第１の電極は
前記半導体基板の一方の主面の中央部分に設けられ、前
記電流ブロック層は第１及び第２の電流ブロック層から
成り、前記第１の電流ブロック層は平面的に見て前記第
１の電極と重なり合う部分を有するように配置され、前
記第２の電流ブロック層は平面的に見て前記コンタクト
層を介して前記第１の電流ブロック層を包囲し且つ前記
半導体基板の側面に露出するように形成されていること
を特徴とする半導体発光素子に係わるものである。な
お、請求項２に示すように、半導体基板の側面を粗面化
することが望ましい。また、請求項３に示すように、側
面と主面の両方を粗面化することが望ましい。The present invention for achieving the above object comprises at least a first conductivity type cladding layer, an active layer, a second conductivity type cladding layer opposite to the first conductivity type, and a first conductivity type cladding layer. A semiconductor substrate in which a conductivity type current blocking layer and a second conductivity type contact layer are sequentially arranged; a first electrode connected to the contact layer on one main surface of the semiconductor substrate; In a semiconductor light emitting device having a second electrode disposed on the other main surface and electrically connected to the first conductivity type cladding layer, the first electrode is one main surface of the semiconductor substrate. The current blocking layer is provided in a central portion of the surface, and the current blocking layer includes first and second current blocking layers, and the first current blocking layer has a portion overlapping with the first electrode in plan view. Is arranged and said second current block A layer relating to a semiconductor light-emitting device, characterized in that the layer is formed so as to surround the first current blocking layer via the contact layer in plan view and to be exposed at a side surface of the semiconductor substrate. Is. It is desirable that the side surface of the semiconductor substrate is roughened as described in claim 2. Further, as described in claim 3, it is desirable to roughen both the side surface and the main surface.
【０００７】[0007]
【発明の作用及び効果】各請求項の発明では、第２の電
流ブロック層が半導体基板の側面に露出するように形成
されているので、側面近傍に電流が実質的に流れない。
半導体基板の側面近傍はダイシング等に基づく微小クラ
ックを有し、非発光の再結合が生じるトラップを多く含
む。従って、側面近傍に電流が流れても発光に寄与しな
い再結合が生じ、発光効率の低下を招く。これに対し、
本発明では第２の電流ブロック層の働きで側面近傍に電
流が流れないので、発光に寄与しない電流量が少なくな
り、効率が良くなる。なお、請求項２に示す側面を粗面
化すると、側面方向に放射された光の側面における全反
射が阻止され、光の取り出し効率が良くなる。なお、粗
面化することによって半導体基板の側面近傍にクラック
等が生じ、発光に寄与しない再結合を起すトラップが多
くなるが、第２の電流ブロック層によって側面近傍の電
流が制限されているので、特に小電流領域での効率の低
下を低減することができる。請求項３に示すように、主
面も粗面化すると、ここでの全反射が防止され、特に大
電流領域での効率を高めることができる。According to the invention of each claim, since the second current blocking layer is formed so as to be exposed at the side surface of the semiconductor substrate, the current does not substantially flow in the vicinity of the side surface.
The vicinity of the side surface of the semiconductor substrate has minute cracks due to dicing or the like, and includes many traps in which non-radiative recombination occurs. Therefore, even if a current flows in the vicinity of the side surface, recombination that does not contribute to light emission occurs, resulting in a decrease in light emission efficiency. In contrast,
In the present invention, since the current does not flow in the vicinity of the side surface due to the function of the second current blocking layer, the amount of current that does not contribute to light emission is reduced and efficiency is improved. When the side surface described in claim 2 is roughened, total reflection on the side surface of the light emitted in the side surface direction is blocked, and the light extraction efficiency is improved. Note that the roughening causes cracks and the like near the side surface of the semiconductor substrate to increase recombination which does not contribute to light emission, but the current near the side surface is limited by the second current blocking layer. In particular, it is possible to reduce the decrease in efficiency particularly in the small current region. When the main surface is also roughened as described in claim 3, total reflection is prevented here, and the efficiency can be increased particularly in a large current region.
【０００８】[0008]
【実施例】以下、図２及び図３を参照して本発明の一実
施例に係わる半導体発光素子即ち発光ダイオードについ
て説明する。図２に示す本実施例の発光ダイオード（Ｌ
ＥＤ）は、ｎ形ＧａＡｓ基板層１１とｎ形ＧａＡｓバッ
ファ層１２とｎ形ＡｌＧａＩｎＰクラッド層１３とＡｌ
ＧａＩｎＰ活性層１４とｐ形ＡｌＧａＩｎＰクラッド層
１５と第１及び第２のｎ形ＡｌＧａＩｎＰ電流ブロック
層１６ａ、１６ｂとｐ形ＡｌＧａＡｓコンタクト層１７
が順次に積層された半導体基板と、コンタクト層１７の
上面に形成されたアノード電極（第１の電極）１８と、
基板層１１の下面に形成されたカソード電極（第２の電
極）１９とを有する。なお、図２の発光ダイオードの第
１及び第２の電流ブロック層１６ａ、１６ｂを除いた部
分は図１と実質的に同一に構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor light emitting device, that is, a light emitting diode according to an embodiment of the present invention will be described below with reference to FIGS. The light emitting diode (L
ED) is an n-type GaAs substrate layer 11, an n-type GaAs buffer layer 12, an n-type AlGaInP clad layer 13 and Al.
GaInP active layer 14, p-type AlGaInP clad layer 15, first and second n-type AlGaInP current blocking layers 16a and 16b, and p-type AlGaAs contact layer 17
A semiconductor substrate in which layers are sequentially stacked, an anode electrode (first electrode) 18 formed on the upper surface of the contact layer 17,
It has a cathode electrode (second electrode) 19 formed on the lower surface of the substrate layer 11. The portion of the light emitting diode of FIG. 2 excluding the first and second current blocking layers 16a and 16b is substantially the same as that of FIG.
【０００９】アノード電極１８は図３で鎖線で示すよう
に、平面的に見てコンタクト層１７の上面の中央部分に
形成されており、略円形の平面形状を有する。なお、ア
ノード電極１８の平面形状は円形に限られず、素子の平
面形状に合わせて略四角形の平面形状としてもよい。コ
ンタクト層１７の上面のアノード電極１８が形成されて
いない領域即ち平面的に見てアノード電極１８を包囲す
る環状の領域は、光取り出し領域２０となる。カソード
電極１９はＧａＡｓ基板層１１の下面全体に形成されて
いるが、場合によってはその外縁を素子外縁から若干内
側に離間させてもよい。As shown by the chain line in FIG. 3, the anode electrode 18 is formed in the central portion of the upper surface of the contact layer 17 in plan view and has a substantially circular planar shape. The planar shape of the anode electrode 18 is not limited to the circular shape, and may be a substantially rectangular planar shape in accordance with the planar shape of the element. A region on the upper surface of the contact layer 17 where the anode electrode 18 is not formed, that is, a ring-shaped region surrounding the anode electrode 18 in plan view becomes a light extraction region 20. Although the cathode electrode 19 is formed on the entire lower surface of the GaAs substrate layer 11, the outer edge of the cathode electrode 19 may be slightly spaced inward from the outer edge of the element.
【００１０】第１の電流ブロック層１６ａはアノード電
極１８に対向して配置され、第２の電流ブロック層１６
ｂは平面的に見て第１の電流ブロック層１６ａを離間し
て包囲するように配置されている。第１の電流ブロック
層１６ａはアノード電極１８と同一の円形の平面形状を
有しており、平面的に見てその全周にわたってアノード
電極１８の外縁よりも外側に僅かに突き出ている。即
ち、図３に示すように、平面的に見るとアノード電極１
８は第１の電流ブロック層１６ａの内側に包含される。
アノード電極１８の外縁と第１の電流ブロック層１６ａ
の外縁との間隔即ち第１の電流ブロック層１６ａのアノ
ード電極１８の直下からの突出幅Ｌ1 は、その全周にわ
たって等しくなっている。第１の電流ブロック層１６ａ
の上面及び側面はコンタクト層１７に接してその界面に
ｐｎ接合を形成する。また、第１の電流ブロック層１６
ａの下面はｐ形ＡｌＧａＩｎＰクラッド層１５の上面に
接してその界面にｐｎ接合を形成している。第２の電流
ブロック層１６ｂは図３に示すように、コンタクト層１
７を介して第１の電流ブロック層１６ａから離間して素
子周辺側に環状に形成され、半導体基板の側面に露出し
ている。なお、第１の電流ブロック層１６ａと第２の電
流ブロック層１６ｂとの間隔Ｌ2 は、その全周にわたっ
て等しくなっている。第２の電流ブロック層１６ｂの上
面と内周側側面はコンタクト層１７に接して、その界面
にｐｎ接合を形成している。また、第２の電流ブロック
層１６ｂの下面はｐ形ＡｌＧａＩｎＰクラッド層１５に
接してその界面にｐｎ接合を形成している。この結果、
ｐ形ＡｌＧａＩｎＰクラッド層１５の上面は、コンタク
ト層１７に環状に接している。第１及び第２の電流ブロ
ック層１６ａ、１６ｂの間の環状のコンタクト層１７は
電流通路となり、この上方は光取り出し上面２０になっ
ている。The first current blocking layer 16a is arranged so as to face the anode electrode 18, and the second current blocking layer 16 is provided.
b is arranged so as to surround the first current block layer 16a with a space therebetween when seen in a plan view. The first current blocking layer 16a has the same circular planar shape as the anode electrode 18, and slightly protrudes outward from the outer edge of the anode electrode 18 over the entire circumference in plan view. That is, as shown in FIG. 3, when viewed in plan, the anode electrode 1
8 is included inside the first current blocking layer 16a.
The outer edge of the anode electrode 18 and the first current blocking layer 16a
The distance from the outer edge of the first current blocking layer 16a, that is, the width L1 of the projection of the first current blocking layer 16a from directly below the anode electrode 18 is equal over the entire circumference. First current blocking layer 16a
The upper surface and the side surface of are contacted with the contact layer 17 to form a pn junction at the interface. In addition, the first current blocking layer 16
The lower surface of a is in contact with the upper surface of the p-type AlGaInP cladding layer 15 to form a pn junction at the interface. As shown in FIG. 3, the second current blocking layer 16b has a contact layer 1
The first current block layer 16a is separated from the first current block layer 16a by a ring shape 7 and is formed in a ring shape on the element peripheral side, and is exposed on the side surface of the semiconductor substrate. The distance L2 between the first current blocking layer 16a and the second current blocking layer 16b is equal over the entire circumference. The upper surface and the inner peripheral side surface of the second current block layer 16b are in contact with the contact layer 17, and a pn junction is formed at the interface. The lower surface of the second current block layer 16b is in contact with the p-type AlGaInP clad layer 15 to form a pn junction at its interface. As a result,
The upper surface of the p-type AlGaInP cladding layer 15 is in contact with the contact layer 17 in a ring shape. The annular contact layer 17 between the first and second current blocking layers 16a and 16b serves as a current path, and the upper portion thereof is the light extraction upper surface 20.
【００１１】半導体基板の側面２１及び光取り出し上面
２０は好ましくは高さ１〜２０μｍの範囲の微小の凹凸
を有する粗面となっている。側面２１の粗面加工はウエ
ハをダイヤモンド製のシングルブレードの高速回転刃で
ダイシングし、このダイシング面をＨＣｌ：Ｈ2 Ｏ2 ：
Ｈ2 Ｏ＝６：１：６のエッチング液でエッチングするこ
とによって形成されている。なお、側面２１の近傍領域
はダイシング及び／又は粗面化のために発光に寄与しな
い再結合が生じる領域である。本発明に従う第２の電流
ブロック層１６ｂは側面２１の近傍の非発光再結合領域
に対応して形成されている。半導体基板の上面２０は、
ここを特別に鏡面仕上しないことによって粗面化されて
いる。The side surface 21 and the light extraction top surface 20 of the semiconductor substrate are preferably rough surfaces having minute irregularities in the height range of 1 to 20 μm. For the roughening of the side surface 21, the wafer is diced with a diamond single blade high-speed rotary blade, and this dicing surface is subjected to HCl: H 2 O 2 :
It is formed by etching with an etching solution of H 2 O = 6: 1: 6. The region near the side surface 21 is a region where recombination that does not contribute to light emission occurs due to dicing and / or roughening. The second current blocking layer 16b according to the present invention is formed corresponding to the non-radiative recombination region near the side surface 21. The upper surface 20 of the semiconductor substrate is
The surface is roughened by not mirror-finishing it.
【００１２】この発光ダイオード素子は、アノード電極
１８の直下に第１の電流ブロック層１６ａを有し、この
第１の電流ブロック層１６ｂを離間して包囲するように
側面２１に隣接して環状の第２の電流ブロック層１６ｂ
を有する。このため、アノード電極１８からカソード電
極１９に向って流れる電流は、第１の電流ブロック層１
６ａと第２の電流ブロック層１６ｂの間を通って活性層
１４へと流れ込む。この結果、主たる発光領域は第１の
電流ブロック層１６ａと第２の電流ブロック層１６ｂの
間の直下に形成される。この主たる発光領域の上にはア
ノード電極１８がないので、上方に取り出される光がア
ノード電極１８によって遮られない。また、第２の電流
ブロック層１６ｂによって側面２１の近傍に向う電流の
流れが抑制されているので、側面２１を粗面化すること
に伴って生ずる側面近傍での非発光再結合の増大の問題
が解消されている。このため、表面を粗面化することに
よって光取り出し効率を向上させる効果が比較的小さい
電流領域でも非発光再結合によって減殺されることなく
良好に発揮される。勿論、大電流領域でもこの光取り出
し効率の向上効果は良好に発揮される。結果として、図
４の特性線Ｃに示すように小電流領域から大電流領域ま
で幅広い領域での高光度化が実現される。This light emitting diode element has a first current blocking layer 16a immediately below the anode electrode 18, and is annularly adjacent to the side surface 21 so as to surround the first current blocking layer 16b at a distance. Second current blocking layer 16b
Have. Therefore, the current flowing from the anode electrode 18 toward the cathode electrode 19 is the first current blocking layer 1
It flows into the active layer 14 through between 6a and the second current blocking layer 16b. As a result, the main light emitting region is formed immediately below between the first current blocking layer 16a and the second current blocking layer 16b. Since the anode electrode 18 is not present on the main light emitting region, the light extracted upward is not blocked by the anode electrode 18. In addition, since the current flow toward the vicinity of the side surface 21 is suppressed by the second current blocking layer 16b, the problem of increase of non-radiative recombination near the side surface caused by roughening the side surface 21. Has been resolved. For this reason, the effect of improving the light extraction efficiency by roughening the surface can be satisfactorily exhibited without being reduced by the non-radiative recombination even in the current region where the light extraction efficiency is relatively small. Of course, even in a large current region, the effect of improving the light extraction efficiency is satisfactorily exhibited. As a result, as shown by the characteristic line C in FIG. 4, high luminous intensity is realized in a wide range from a small current region to a large current region.
【００１３】なお、本実施例ではウエハのダイシング時
において、側面（切断面）に光取り出し効率を向上する
に適した粗面が形成され、これをそのまま全反射防止用
の粗面として利用している。従って、製造プロセスの簡
単化が達成される。例えば、主面が粗面化したウエハを
利用すれば実質的にブレーキング即ちダイシングのみで
上面２０及び側面２１が光取り出し効率の向上に適した
粗面を有する半導体チップが得られる。なお、主面が粗
面化していないウエハを利用するときは、ダイシングし
た後に素子表面（上面、側面）をエッチングすることに
よって粗面とすることができる。このとき、上面のみを
選択的にエッチングしてもよい。In this embodiment, a rough surface suitable for improving the light extraction efficiency is formed on the side surface (cut surface) at the time of dicing the wafer, and is used as it is as a rough surface for preventing total reflection. There is. Therefore, simplification of the manufacturing process is achieved. For example, if a wafer having a roughened main surface is used, a semiconductor chip having a rough surface on the upper surface 20 and the side surface 21 suitable for improving the light extraction efficiency can be obtained substantially only by braking or dicing. When a wafer whose main surface is not roughened is used, it can be roughened by etching the element surface (top surface, side surface) after dicing. At this time, only the upper surface may be selectively etched.
【００１４】[0014]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） ｐ形ＡｌＧａＩｎＰクラッド層１５が厚すぎた
り、不純物濃度が高すぎたりすると、ｐ形ＡｌＧａＩｎ
Ｐクラッド層１５内において、電流が素子の平面方向に
広がり易くなり、第２の電流ブロック層１６ｂを形成し
た効果が損われてしまうおそれがある。従って、ｐ形Ａ
ｌＧａＩｎＰクラッド層１５の厚みと不純物濃度はそれ
ぞれ１μｍ以下、５×１０17ｃｍ-3以下とすることが望
ましい。即ち、実用的には、ＮＤ積（不純物濃度×厚
み）を５×１０12ｃｍ-2以下とするのが望ましいから、
厚みを０．５μｍ程度としたときは不純物濃度を１×１
０7ｃｍ-3程度以下とすることが望ましい。 （２） ｐ形ＡｌＧａＩｎＰクラッド層１５の不純物濃
度は電流の横方向広がりを防止する点においては低濃度
とする方が望ましいが、あるレベルまで低濃度とする
と、ｐ形ＡｌＧａＩｎＰクラッド層１５の活性層１４に
対する電位障壁の高さが低くなることに伴うオーバーフ
ローの影響が顕著となる。このような場合は、ｐ形Ａｌ
ＧａＩｎＰクラッド層１５の活性層１４側に部分的にそ
の不純物濃度を高めた層（オーバーフロー抑制層）を形
成するとよい。なお、オーバーフロー層はあまり薄いと
オーバーフローを抑制する効果が十分に発揮されず、ま
た、あまり厚いと電流の横方向広がりが生ずるので、１
００〜５００オングストロ−ムの範囲に設定するのが望
ましい。 （３） 上面２０を特別に粗面化しないで、側面２１又
は側面２１の光放射領域のみを粗面化してもそれなりの
効果を得ることができる。 （４） 第１の電流ブロック層１６ａはアノード電極１
８のほぼ下側に位置していればよく、また複数個に分割
されていてもよい。第２の電流ブロック層１６ｂは環状
であることが望ましいが、実質的に環状であれば複数個
に分割されていてもよい。 （５） 本発明に従う粗面は、例えば１〜２０μｍの間
隔で凹凸が点在しているもの、又はストライプ状、格子
状等に凹凸が配置されているものでもよい。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) If the p-type AlGaInP cladding layer 15 is too thick or the impurity concentration is too high, the p-type AlGaInP is too thick.
In the P clad layer 15, the current tends to spread in the planar direction of the element, and the effect of forming the second current blocking layer 16b may be impaired. Therefore, p-type A
It is desirable that the thickness and the impurity concentration of the 1GaInP cladding layer 15 be 1 μm or less and 5 × 10 17 cm −3 or less, respectively. That is, in practice, it is desirable to set the ND product (impurity concentration × thickness) to 5 × 10 12 cm −2 or less,
When the thickness is about 0.5 μm, the impurity concentration is 1 × 1.
It is desirable to set it to about 0 7 cm -3 or less. (2) It is desirable that the impurity concentration of the p-type AlGaInP clad layer 15 be low in order to prevent the current from spreading laterally. The effect of overflow due to the decrease in the height of the potential barrier with respect to 14 becomes significant. In such a case, p-type Al
On the active layer 14 side of the GaInP clad layer 15, it is preferable to form a layer (overflow suppression layer) whose impurity concentration is partially increased. If the overflow layer is too thin, the effect of suppressing the overflow will not be fully exerted, and if it is too thick, the current will spread laterally.
It is desirable to set it in the range of 00 to 500 angstrom. (3) Even if the side surface 21 or only the light emitting region of the side surface 21 is roughened without particularly roughening the upper surface 20, some effects can be obtained. (4) The first current blocking layer 16a is the anode electrode 1
It suffices that it is located substantially below 8 and may be divided into a plurality of parts. The second current blocking layer 16b is preferably ring-shaped, but may be divided into a plurality if it is substantially ring-shaped. (5) The rough surface according to the present invention may be, for example, one having irregularities scattered at intervals of 1 to 20 μm, or one having irregularities arranged in a stripe shape, a lattice shape, or the like.
【図１】従来の発光ダイオードを示す中央縦断面図であ
る。FIG. 1 is a central longitudinal sectional view showing a conventional light emitting diode.
【図２】本発明の実施例の発光ダイオードを示す中央縦
断面図である。FIG. 2 is a central vertical sectional view showing a light emitting diode according to an embodiment of the present invention.
【図３】図２のＡ−Ａ線を示す断面図である。FIG. 3 is a sectional view taken along line AA of FIG.
【図４】従来の発光ダイオードの表面を粗面化しないも
のとしたもの及び本発明の実施例の発光ダイオードの電
流と光度の関係を示す特性図である。FIG. 4 is a characteristic diagram showing a relationship between current and luminous intensity of a conventional light emitting diode having a non-roughened surface and a light emitting diode of an embodiment of the present invention.
１３ ｎ形クラッド層 １４ 活性層 １５ ｐ形クラッド層 １６ａ、１６ｂ 第１及び第２の電流ブロック層 １７ コンタクト層 １８ アノード電極 13 n-type clad layer 14 active layer 15 p-type clad layer 16a, 16b first and second current blocking layers 17 contact layer 18 anode electrode
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成７年６月２日[Submission date] June 2, 1995
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Name of item to be amended] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【特許請求の範囲】[Claims]
Claims (3)
性層と前記第１導電形と反対の第２導電形のクラッド層
と第１導電形の電流ブロック層と第２導電形のコンタク
ト層とが順に配置された半導体基板と、前記半導体基板
の一方の主面で前記コンタクト層に接続された第１の電
極と、前記半導体基板の他方の主面に配設され且つ前記
第１導電形のクラッド層に電気的に接続された第２の電
極とを備えた半導体発光素子において、 前記第１の電極は前記半導体基板の一方の主面の中央部
分に設けられ、 前記電流ブロック層は第１及び第２の電流ブロック層か
ら成り、 前記第１の電流ブロック層は平面的に見て前記第１の電
極と重なり合う部分を有するように配置され、 前記第２の電流ブロック層は平面的に見て前記コンタク
ト層を介して前記第１の電流ブロック層を包囲し且つ前
記半導体基板の側面に露出するように形成されているこ
とを特徴とする半導体発光素子。1. A clad layer of a first conductivity type, an active layer, a clad layer of a second conductivity type opposite to the first conductivity type, a current blocking layer of a first conductivity type, and a contact layer of a second conductivity type. Are sequentially arranged, a first electrode connected to the contact layer on one main surface of the semiconductor substrate, and a first electrode of the first conductivity type provided on the other main surface of the semiconductor substrate. In a semiconductor light emitting device including a second electrode electrically connected to a clad layer, the first electrode is provided in a central portion of one main surface of the semiconductor substrate, and the current blocking layer is a first electrode. And a second current blocking layer, wherein the first current blocking layer is arranged so as to have a portion that overlaps with the first electrode when seen in a plan view, and the second current blocking layer is seen in a plan view. Through the contact layer The semiconductor light emitting device characterized in that it is formed so that the first current blocking layer is exposed on the side surfaces of the enclosure to and the semiconductor substrate.
射領域が粗面に形成されていることを特徴とする半導体
発光素子。2. A semiconductor light emitting device, wherein at least a light emitting region on a side surface of the semiconductor substrate is formed into a rough surface.
記一方の主面の光放射領域が粗面に形成されていること
を特徴とする請求項２記載の半導体発光素子。3. The semiconductor light emitting device according to claim 2, wherein at least a side surface of the semiconductor substrate and a light emitting region of the one main surface are formed into a rough surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33294694A JPH08167738A (en) | 1994-12-14 | 1994-12-14 | Semiconductor light emitting element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33294694A JPH08167738A (en) | 1994-12-14 | 1994-12-14 | Semiconductor light emitting element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08167738A true JPH08167738A (en) | 1996-06-25 |
Family
ID=18260583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33294694A Pending JPH08167738A (en) | 1994-12-14 | 1994-12-14 | Semiconductor light emitting element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08167738A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002359399A (en) * | 2001-05-31 | 2002-12-13 | Shin Etsu Handotai Co Ltd | Light emitting element and method of manufacturing the same |
| WO2006080958A1 (en) * | 2005-01-24 | 2006-08-03 | Cree, Inc. | Led with curent confinement structure and surface roughening |
| US7247985B2 (en) | 2003-10-30 | 2007-07-24 | Sharp Kabushiki Kaisha | Semiconductor light-emitting device having annular shape light emitting region and current blocking layer |
| JP2007324326A (en) * | 2006-05-31 | 2007-12-13 | Aisin Seiki Co Ltd | Light-emitting diode chip and wafer division processing method |
| US7524428B2 (en) | 2003-02-26 | 2009-04-28 | Kabushiki Kaisha Toshiba | Display device and method of manufacturing transparent substrate for display device |
| JP2010258039A (en) * | 2009-04-21 | 2010-11-11 | Shin Etsu Handotai Co Ltd | Method of manufacturing light emitting element, and light emitting element |
| JP2012019234A (en) * | 2000-04-26 | 2012-01-26 | Osram Opto Semiconductors Gmbh | GaN BASED LIGHT-EMITTING DIODE CHIP AND METHOD OF MANUFACTURING LIGHT-EMITTING DIODE STRUCTURE ELEMENT |
| JP2020010056A (en) * | 2019-09-11 | 2020-01-16 | 晶元光電股▲ふん▼有限公司Ｅｐｉｓｔａｒ Ｃｏｒｐｏｒａｔｉｏｎ | Semiconductor light-emitting component |
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| JPH04116162U (en) * | 1991-03-28 | 1992-10-16 | 三洋電機株式会社 | light emitting diode |
| JPH05167101A (en) * | 1991-12-12 | 1993-07-02 | Toshiba Corp | Semiconductor light emitting element |
| JPH05267715A (en) * | 1992-03-24 | 1993-10-15 | Toshiba Corp | Semiconductor light-emitting device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04116162U (en) * | 1991-03-28 | 1992-10-16 | 三洋電機株式会社 | light emitting diode |
| JPH05167101A (en) * | 1991-12-12 | 1993-07-02 | Toshiba Corp | Semiconductor light emitting element |
| JPH05267715A (en) * | 1992-03-24 | 1993-10-15 | Toshiba Corp | Semiconductor light-emitting device |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012019234A (en) * | 2000-04-26 | 2012-01-26 | Osram Opto Semiconductors Gmbh | GaN BASED LIGHT-EMITTING DIODE CHIP AND METHOD OF MANUFACTURING LIGHT-EMITTING DIODE STRUCTURE ELEMENT |
| JP2002359399A (en) * | 2001-05-31 | 2002-12-13 | Shin Etsu Handotai Co Ltd | Light emitting element and method of manufacturing the same |
| US7524428B2 (en) | 2003-02-26 | 2009-04-28 | Kabushiki Kaisha Toshiba | Display device and method of manufacturing transparent substrate for display device |
| US8395305B2 (en) | 2003-02-26 | 2013-03-12 | Kabushiki Kaisha Toshiba | Display device and method of manufacturing transparent substrate for display device |
| CN100376042C (en) * | 2003-10-30 | 2008-03-19 | 夏普株式会社 | Semiconductor light-emitting device |
| US7247985B2 (en) | 2003-10-30 | 2007-07-24 | Sharp Kabushiki Kaisha | Semiconductor light-emitting device having annular shape light emitting region and current blocking layer |
| US7335920B2 (en) | 2005-01-24 | 2008-02-26 | Cree, Inc. | LED with current confinement structure and surface roughening |
| JP2011160006A (en) * | 2005-01-24 | 2011-08-18 | Cree Inc | Led with current confinement structure and surface roughening |
| WO2006080958A1 (en) * | 2005-01-24 | 2006-08-03 | Cree, Inc. | Led with curent confinement structure and surface roughening |
| US8772792B2 (en) | 2005-01-24 | 2014-07-08 | Cree, Inc. | LED with surface roughening |
| JP2007324326A (en) * | 2006-05-31 | 2007-12-13 | Aisin Seiki Co Ltd | Light-emitting diode chip and wafer division processing method |
| JP2010258039A (en) * | 2009-04-21 | 2010-11-11 | Shin Etsu Handotai Co Ltd | Method of manufacturing light emitting element, and light emitting element |
| JP2020010056A (en) * | 2019-09-11 | 2020-01-16 | 晶元光電股▲ふん▼有限公司Ｅｐｉｓｔａｒ Ｃｏｒｐｏｒａｔｉｏｎ | Semiconductor light-emitting component |
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