JP2020010056A - Semiconductor light-emitting component - Google Patents

Semiconductor light-emitting component Download PDF

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JP2020010056A
JP2020010056A JP2019165187A JP2019165187A JP2020010056A JP 2020010056 A JP2020010056 A JP 2020010056A JP 2019165187 A JP2019165187 A JP 2019165187A JP 2019165187 A JP2019165187 A JP 2019165187A JP 2020010056 A JP2020010056 A JP 2020010056A
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semiconductor
layer
semiconductor stack
emitting component
stack
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チィ チウ，シン
Hsin-Chih Chiu
チィ チウ，シン
アイ チェン，シィ
Shih-I Chen
アイ チェン，シィ
チアン ルー，チィ
Chih-Chiang Lu
チアン ルー，チィ
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Epistar Corp
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Epistar Corp
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Abstract

To provide a semiconductor light-emitting component.SOLUTION: A light-emitting component includes an epitaxy layer and a main emission layer. The epitaxy layer includes a first semiconductor layer, a second semiconductor layer, and an active layer located between the first and second semiconductor layers, and radiating a light beam. The main emission layer is located above the first semiconductor layer, and the light beam is transmitted through the main emission surface. The main emission surface has a first emission zone, a second emission zone, and a maximum near field light intensity. The near field light intensity in the first emission zone is between 70%-100% of the maximum near field light intensity, and the near field light intensity in the second emission zone is between 0%-70% of the maximum near field light intensity.SELECTED DRAWING: Figure 2A

Description

本発明は発光ダイオードの構造に関するものである。   The present invention relates to a structure of a light emitting diode.

図１を参照すると、これは従来の発光ダイオード１００（Light Emitting Diode、ＬＥＤ）を示す図である。この発光ダイオード１００は、基板５ｂと、エピタキシ構造１ｂと、２つの電極２及び９ｂとを含み、該エピタキシ構造１ｂは、第一半導体積層１１ｂと、活性層１０ｂと、第二半導体積層１２ｂを含む。電極２は、エピタキシ構造１ｂの上表面に形成されかつ金属導線２ｂによって外部の電源に電気的に接続され、電極９ｂは基板５ｂの下方に形成される。電極２及び９ｂによって外部電源の電流が活性層１０ｂで流れるとき、活性層１０ｂ中のホール（Electron hole）が互いに複合（recombination）し、所定の波長を有する光子が釈放されるので、発光ダイオード１００が発光することができる。しかし、発光ダイオードの体積が小さくなればなるほど、エッチングによって結晶粒子の側壁に形成される結晶格子の欠陥により、非輻射複合効果（non−radiative recombination）に関する影響が激しくなり、発光効率が低下する欠点を有している。   FIG. 1 is a view showing a conventional light emitting diode (LED) 100. As shown in FIG. The light emitting diode 100 includes a substrate 5b, an epitaxy structure 1b, and two electrodes 2 and 9b, and the epitaxy structure 1b includes a first semiconductor stack 11b, an active layer 10b, and a second semiconductor stack 12b. . The electrode 2 is formed on the upper surface of the epitaxy structure 1b and is electrically connected to an external power supply by a metal conductor 2b, and the electrode 9b is formed below the substrate 5b. When a current of an external power supply flows through the active layer 10b by the electrodes 2 and 9b, holes (Electron holes) in the active layer 10b recombine with each other and photons having a predetermined wavelength are released. Can emit light. However, as the volume of the light emitting diode becomes smaller, the effect of non-radiative recombination becomes more severe due to defects in the crystal lattice formed on the sidewalls of the crystal grains by etching, and the luminous efficiency decreases. have.

本発明に係る発光部品はエピタキシ層と主出射面を含む。前記エピタキシ層は、第一半導体積層、第二半導体積層及び、第一半導体積層と第二半導体積層との間に位置しかつ光線を放射する活性層を含む。前記主出射面は前記第一半導体積層上に位置し、前記光線は該主出射面を透過する。前記主出射面は、第一出射区域、第二出射区域及び最大近接場光度を有する。前記第一出射区域内の近接場光度は最大近接場光度の７０％〜１００％の間に入り、前記第二出射区域内の近接場光度は最大近接場光度の０％〜７０％の間に入る。   The light emitting component according to the present invention includes an epitaxy layer and a main emission surface. The epitaxy layer includes a first semiconductor stack, a second semiconductor stack, and an active layer located between the first semiconductor stack and the second semiconductor stack and emitting light. The main exit surface is located on the first semiconductor stack, and the light beam transmits through the main exit surface. The main exit surface has a first exit area, a second exit area, and a maximum near-field luminous intensity. The near-field luminosity in the first exit area falls between 70% and 100% of the maximum near-field luminosity, and the near-field luminosity in the second exit area falls between 0% and 70% of the maximum near-field luminosity. enter.

従来の半導体発光ダイオードを示す図である。FIG. 2 is a diagram illustrating a conventional semiconductor light emitting diode. 本発明の第一実施例に係る半導体発光部品を示す図である。FIG. 2 is a view showing a semiconductor light emitting component according to the first embodiment of the present invention. 本発明の第一実施例に係る半導体発光部品を示す図である。FIG. 2 is a view showing a semiconductor light emitting component according to the first embodiment of the present invention. 本実施例の第一実施例に係る半導体発光部品を示す平面図である。FIG. 2 is a plan view showing a semiconductor light emitting component according to a first embodiment of the present embodiment. 本発明の第二実施例に係る半導体発光部品を示す図である。FIG. 6 is a view illustrating a semiconductor light emitting component according to a second embodiment of the present invention. 本発明の第二実施例に係る半導体発光部品を示す図である。FIG. 6 is a view illustrating a semiconductor light emitting component according to a second embodiment of the present invention. 本発明の他の実施例に係る半導体発光部品を示す図である。FIG. 9 is a view illustrating a semiconductor light emitting component according to another embodiment of the present invention.

（第一実施例）
図２Ａは、本発明の第一実施例に係る半導体発光部品１Ａを示す図である。半導体発光部品１Ａはエピタキシ構造１（エピタキシ層とも言う）を含み、このエピタキシ構造１は第一半導体積層１１、活性層１０及び第二半導体積層１２を含む。第一半導体積層１１の上表面１１ａの中心位置には正面電極２１が形成され、これは第一半導体積層１１と電気接続する。第一半導体積層１１の上表面１１ａにおいて、正面電極２１に覆われていない部分が粗い表面であることにより、光取出し率を向上させることができる。第二半導体積層１２の下表面１２ａの中心位置には第二抵抗接触構造２２が形成され、この第二抵抗接触構造２２は第二半導体積層１２と電気接続する。第二半導体積層１２の下表面１２ａ上には反射積層３が形成され、この反射積層３は第二半導体積層１２と第二抵抗接触構造２２を覆う。反射積層３は、第二半導体積層１２及び第二抵抗接触構造２２を覆う透明導電層３１と、透明導電層３１を覆う金属反射層３２と、金属反射層３２を覆う遮断層３３とを含む。反射積層３には粘着層４によって接着される導電基板５がある。反射積層３と対向する導電基板５の他側には背面電極９が設置される。正面電極２１と背面電極９で電流が流れるとき、活性層１０が発光し、活性層１０の光線は第一半導体積層１１と第二半導体積層１２を透過することができる。第一半導体積層１１及び第二半導体積層１２のバンドギャップが活性層１０のバンドギャップより大きいことにより、活性層１０が放射する光線に対して第一半導体積層１１及び第二半導体積層１２の透明度は５０％以上になる。この光線は、第一半導体積層１１を直接透過してから上表面１１ａ又はエピタキシ構造１の側面１Ｓから出射するか、或いは反射積層３に反射された後第一半導体積層１１の上表面１１ａ又はエピタキシ構造１の側面１Ｓから出射することができる。 (First embodiment)
FIG. 2A is a view showing a semiconductor light emitting component 1A according to the first embodiment of the present invention. The semiconductor light emitting component 1A includes an epitaxy structure 1 (also referred to as an epitaxy layer). The epitaxy structure 1 includes a first semiconductor stack 11, an active layer 10, and a second semiconductor stack 12. A front electrode 21 is formed at the center of the upper surface 11a of the first semiconductor stack 11, and is electrically connected to the first semiconductor stack 11. Since the portion of the upper surface 11a of the first semiconductor stack 11 that is not covered by the front electrode 21 is a rough surface, the light extraction rate can be improved. A second resistance contact structure 22 is formed at a center position of the lower surface 12 a of the second semiconductor stack 12, and the second resistance contact structure 22 is electrically connected to the second semiconductor stack 12. A reflective stack 3 is formed on the lower surface 12 a of the second semiconductor stack 12 and covers the second semiconductor stack 12 and the second resistance contact structure 22. The reflective laminate 3 includes a transparent conductive layer 31 covering the second semiconductor laminate 12 and the second resistance contact structure 22, a metal reflective layer 32 covering the transparent conductive layer 31, and a blocking layer 33 covering the metal reflective layer 32. The reflective laminate 3 has a conductive substrate 5 bonded by an adhesive layer 4. On the other side of the conductive substrate 5 facing the reflective laminate 3, a back electrode 9 is provided. When a current flows between the front electrode 21 and the back electrode 9, the active layer 10 emits light, and the light of the active layer 10 can pass through the first semiconductor stack 11 and the second semiconductor stack 12. Since the band gap of the first semiconductor stack 11 and the second semiconductor stack 12 is larger than the band gap of the active layer 10, the transparency of the first semiconductor stack 11 and the second semiconductor stack 12 with respect to the light emitted by the active layer 10 is increased. 50% or more. This light beam passes through the first semiconductor stack 11 directly and then exits from the upper surface 11a or the side surface 1S of the epitaxy structure 1, or is reflected by the reflective stack 3 and then is reflected from the upper surface 11a or the epitaxy The light can be emitted from the side surface 1S of the structure 1.

活性層１０は多重量子井戸（Multiple Quantum Wells）構造を含む。第一半導体積層１１は、第一電気制限層（confining layer）１１１、第一電気包装層（cladding layer）１１２、第一電気窓口層（window layer）１１３及び第一電気接触層（contact layer）１１４を含む。第二半導体積層１２は、第二電気制限層１２１、第二電気包装層１２２、第二電気窓口層１２３及び第二電気接触層１２４を含む。第一電気包装層１１２及び第二電気包装層１２２がそれぞれ提供する電子、ホールは活性層１０中で複合して発光し、第一電気包装層１１２及び第二電気包装層１２２は活性層１０より大きいバンドギャップを有している。第一電気制限層１１１及び第一電気包装層１１２は、電子、ホールが活性層１０中で複合する確率を向上させ、かつ活性層１０より大きいバンドギャップを有している。第一電気窓口層１１３及び第二電気窓口層１２３が包装層より小さいシート抵抗（sheet resistance）を有していることにより、電流流れを分散させるとともに活性層１０から出射する光線の取出し率を向上させることができる。第一電気接触層１１４及び第二電気接触層１２４は、正面電極２１及び第二抵抗接触構造２２に電気的に接続される。第一半導体積層１１、活性層１０及び第二半導体積層１２の材料はIII−Ｖ族半導体材料、例えばAlxInyGa(1-x-y)N又はAlxInyGa(1-x-y)Pを含むことができ、１≦ｘ、ｙ≦１、（ｘ+ｙ）≦１である。第一電気性及び第二電気性は、異なる元素を入れることにより異なる電気性を有する。例えば、第一電気性はｎ型であり、第二電気性はＰ型であるか、或いは第一半導体積層１１はｎ型半導体であり、第二半導体積層１２はＰ型半導体であることができる。活性層１０の材料によってエピタキシ構造１は、波長が６１０ｎｍ〜６５０ｎｍである赤色光を放射するか、或いは波長が５３０ｎｍ〜５７０ｎｍである緑色光を放射するか、或いは波長が４４０ｎｍ〜４９０ｎｍである青色光を放射することができる。   The active layer 10 has a multiple quantum wells structure. The first semiconductor stack 11 includes a first electrical limiting layer 111, a first electrical packaging layer 112, a first electrical window layer 113, and a first electrical contact layer 114. including. The second semiconductor stack 12 includes a second electrical restriction layer 121, a second electrical packaging layer 122, a second electrical window layer 123, and a second electrical contact layer 124. Electrons and holes provided by the first and second electric wrapping layers 112 and 122, respectively, emit light in a combined manner in the active layer 10, and the first and second electric wrapping layers 112 and 122 are separated from the active layer 10. It has a large band gap. The first electric restriction layer 111 and the first electric packaging layer 112 improve the probability that electrons and holes are combined in the active layer 10 and have a band gap larger than that of the active layer 10. Since the first electrical window layer 113 and the second electrical window layer 123 have a sheet resistance smaller than that of the packaging layer, the current flow is dispersed and the light extraction efficiency of the light emitted from the active layer 10 is improved. Can be done. The first electrical contact layer 114 and the second electrical contact layer 124 are electrically connected to the front electrode 21 and the second resistance contact structure 22. The material of the first semiconductor stack 11, the active layer 10, and the second semiconductor stack 12 may include a III-V semiconductor material, for example, AlxInyGa (1-xy) N or AlxInyGa (1-xy) P, where 1 ≦ x , Y ≦ 1, (x + y) ≦ 1. The first electrical property and the second electrical property have different electrical properties by incorporating different elements. For example, the first electrical property may be n-type and the second electrical property may be p-type, or the first semiconductor stack 11 may be an n-type semiconductor and the second semiconductor stack 12 may be a p-type semiconductor. . Depending on the material of the active layer 10, the epitaxy structure 1 emits red light having a wavelength of 610 nm to 650 nm, emits green light having a wavelength of 530 nm to 570 nm, or blue light having a wavelength of 440 nm to 490 nm. Can be radiated.

図３は、本実施例の半導体発光部品１Ａを示す平面図である。半導体発光部品１Ａが具備する辺縁８により上表面１１ａの形状が形成される。本実施例において、上表面１１ａの形状が円形であるが、他の実施例において、上表面１１ａの形状は、長方形、不等辺五角形、不等辺六角形などのような多辺形であるか、或いは正方形、正五角形、正六角形などのような正多辺形であることができる。正面電極２１と第二抵抗接触構造２２がそれぞれ上表面１１ａと下表面１２ａの中心に位置することにより、エピタキシ構造１の側面１Ｓで流れる電流の比率を低減することができる。本実施例において、正面電極２１と第二抵抗接触構造２２の面積は、第一半導体積層１１の上表面１１ａと第二半導体積層１２の下表面１２ａの面積の約１％〜１０％を占める。したがって、正面電極２１と第二抵抗接触構造２２の面積が大きすぎることによって光線が遮光されることを避け、かつ正面電極２１の面積が小さすぎることによって正方向スレッショルド電圧（forward threshold voltage）が非常に高くなりかつ発光効率が低下することを避けることができる。正面電極２１と第二抵抗接触構造２２の面積が上表面１１ａと下表面１２ａの面積の約２％を占めるとき、最高の発光効率を獲得することができる。本実施例において、第一半導体積層１１の面積と第二半導体積層１２の面積が同様であってもよい。   FIG. 3 is a plan view showing the semiconductor light emitting component 1A of the present embodiment. The shape of the upper surface 11a is formed by the edge 8 of the semiconductor light emitting component 1A. In this embodiment, the shape of the upper surface 11a is circular, but in other embodiments, the shape of the upper surface 11a is a polygon, such as a rectangle, a trapezoidal pentagon, a trapezoidal hexagon, or the like. Alternatively, it may be a regular polygon such as a square, a regular pentagon, a regular hexagon, or the like. Since the front electrode 21 and the second resistance contact structure 22 are located at the centers of the upper surface 11a and the lower surface 12a, respectively, the ratio of the current flowing on the side surface 1S of the epitaxy structure 1 can be reduced. In this embodiment, the area of the front electrode 21 and the second resistance contact structure 22 occupies about 1% to 10% of the area of the upper surface 11a of the first semiconductor stack 11 and the lower surface 12a of the second semiconductor stack 12. Therefore, it is possible to prevent light from being shielded by the area of the front electrode 21 and the second resistance contact structure 22 being too large, and the forward threshold voltage is extremely reduced by the area of the front electrode 21 being too small. And a decrease in luminous efficiency can be avoided. When the area of the front electrode 21 and the second resistance contact structure 22 occupies about 2% of the area of the upper surface 11a and the lower surface 12a, the highest luminous efficiency can be obtained. In this embodiment, the area of the first semiconductor stack 11 and the area of the second semiconductor stack 12 may be the same.

本実施例において、第一半導体積層１１の上表面１１ａの面積が１００００μｍ２より小さいか、或いは上表面１１ａの周辺長さが４００μｍより小さい。正面電極２１は上表面１１ａの中心に位置し、正面電極２１と辺縁８との間の最小距離は５０μｍより小さい。エピタキシ構造１の厚さが１０μｍであるとき、エピタキシ構造１の厚さと上表面１１ａの周辺長さとの間の比率は少なくとも１％以上であるが、好ましくは２．５％以上である。これにより、電流流れがエピタキシ構造１内で容易に散布されることができ、半導体発光部品１Ａのエピタキシ構造１の側面１Ｓで流れる電流の比率を増加させることができる。本実施例において、エピタキシ構造１の総厚さを３μｍ以下まで薄くするか或いは１μｍ〜３μｍの範囲に入るようにすることができるが、好ましくは１μｍ〜２μｍの範囲に入ることである。エピタキシ構造１の厚さと上表面１１ａの周辺長さとの間の比率が少なくとも０．７５％以下になることにより、半導体発光部品１Ａの非輻射複合問題を低減し、発光効率を向上させることができる。第一半導体積層１１の総厚さは、活性層１０の上方から上表面１１ａの下方までのエピタキシ構造の総厚さであり、第二半導体積層１２の総厚さは、活性層１０の下方から下表面１２ａの上方までのエピタキシ構造の総厚さである。本実施例において、第一半導体積層１１の総厚さは、１μｍより大きくないが、好ましくは１０００Å〜５０００Åの範囲に入る。第二半導体積層１２の総厚さは１μｍより大きくないが、好ましくは１０００Å〜５０００Åの範囲に入る。第一半導体積層１１の第一電気制限層１１１、第一電気包装層１１２及び第一電気窓口層１１３において、各層の厚さは２０００Åより大きくないが、好ましくは５００Å〜１５００Åの範囲に入る。第二半導体積層１２の第二電気制限層１２１、第二電気包装層１２２及び第二電気窓口層１２３において、各層の厚さは２０００Åより大きくないが、好ましくは５００Å〜１５００Åの範囲に入る。第一電気接触層１１４と第二電気接触層１２４の厚さは２０００Åより大きくないが、好ましくは３００Å〜１５００Åの範囲に入る。第一半導体積層１１の総厚さは１０００Å〜５０００Åの範囲に入る。第一半導体積層１１の粗い表面はドライエッチング又はウエットエッチング方法で形成することができるが、エッチングの深さを精密に制御するため、誘導結合プラズマ（Inductively Coupled Plasma、ＩＣＰ）エッチング方法を採用することができる。この場合、エッチングの深さを精密に制御できないことによって第一半導体積層１１の構造を貫通し、漏電経路が形成される問題を避けることができる。第一半導体積層１１の粗い表面上において、隣接する頂部と谷部との間の垂直方向の距離は５００Å〜３０００Åの範囲に入る。 In this embodiment, the area of the upper surface 11a of the first semiconductor stack 11 is smaller than 10000 μm 2 , or the peripheral length of the upper surface 11a is smaller than 400 μm. The front electrode 21 is located at the center of the upper surface 11a, and the minimum distance between the front electrode 21 and the edge 8 is smaller than 50 μm. When the thickness of the epitaxy structure 1 is 10 μm, the ratio between the thickness of the epitaxy structure 1 and the peripheral length of the upper surface 11a is at least 1% or more, preferably 2.5% or more. As a result, the current flow can be easily dispersed in the epitaxy structure 1, and the ratio of the current flowing on the side surface 1S of the epitaxy structure 1 of the semiconductor light emitting component 1A can be increased. In this embodiment, the total thickness of the epitaxy structure 1 can be reduced to 3 μm or less or within the range of 1 μm to 3 μm, but preferably within the range of 1 μm to 2 μm. When the ratio between the thickness of the epitaxy structure 1 and the peripheral length of the upper surface 11a is at least 0.75% or less, the combined non-radiative problem of the semiconductor light emitting component 1A can be reduced and the luminous efficiency can be improved. . The total thickness of the first semiconductor stack 11 is the total thickness of the epitaxy structure from above the active layer 10 to below the upper surface 11a, and the total thickness of the second semiconductor stack 12 is from below the active layer 10 The total thickness of the epitaxy structure up to above the lower surface 12a. In the present embodiment, the total thickness of the first semiconductor stack 11 is not larger than 1 μm, but preferably falls within a range of 1000 ° to 5000 °. The total thickness of the second semiconductor stack 12 is not greater than 1 μm, but preferably falls within the range of 1000-5000 °. In the first electrical limiting layer 111, the first electrical packaging layer 112, and the first electrical window layer 113 of the first semiconductor laminate 11, the thickness of each layer is not larger than 2000 °, but preferably falls within the range of 500 ° to 1500 °. In the second electric limiting layer 121, the second electric packaging layer 122, and the second electric window layer 123 of the second semiconductor laminate 12, the thickness of each layer is not larger than 2000 °, but preferably falls within the range of 500 ° to 1500 °. The thickness of first electrical contact layer 114 and second electrical contact layer 124 is not greater than 2000 °, but preferably falls within the range of 300 ° -1500 °. The total thickness of the first semiconductor stack 11 is in the range of 1000-5000 °. The rough surface of the first semiconductor laminate 11 can be formed by a dry etching or wet etching method, but in order to precisely control the etching depth, an inductively coupled plasma (ICP) etching method is used. Can be. In this case, it is possible to avoid a problem that the depth of the etching cannot be precisely controlled, thereby penetrating the structure of the first semiconductor stack 11 and forming a leakage path. On the rough surface of the first semiconductor stack 11, the vertical distance between adjacent peaks and valleys is in the range of 500-3000 °.

本実施例において、半導体発光部品１Ａの上表面１１ａの形状が円形であり、エピタキシ構造１の側面１ＳをＩＣＰエッチングで形成することが好ましい。エピタキシ構造１の側面１Ｓが粗い面或いは凸凹な表面であるとき、半導体発光部品１Ａのエピタキシ構造１の側面１Ｓで流れる電流流れの比率が増加し、非輻射複合効果による影響が激しくなることにより、発光効率が低下する。エピタキシ構造１の側面１Ｓの面積を低減するため、上表面１１ａの面積がいずれも１００００μｍ２である半導体発光部品１Ａにおいて、上表面１１ａの形状が円形でありかつこの周辺長さが３５４μｍであるものを採用することは、上表面１１ａの形状が正方形でありかつこの周辺長さが４００μｍであるものを採用することよりよい。すなわち、上表面１１ａの周辺長さが短ければ短いほど、エピタキシ構造１の側面１Ｓの面積が低下し、粗い側面１Ｓの非輻射複合効果を低減することができる。上表面１１ａの形状が円形であるとき、上表面１１ａの中心の正面電極２１と辺縁８との間の距離が同様であるので、電流の伝播経路をエピタキシ構造１の内部区域に限定することができる。 In this embodiment, it is preferable that the shape of the upper surface 11a of the semiconductor light emitting component 1A is circular, and the side surface 1S of the epitaxy structure 1 is formed by ICP etching. When the side surface 1S of the epitaxy structure 1 is a rough surface or a rough surface, the ratio of the current flow flowing on the side surface 1S of the epitaxy structure 1 of the semiconductor light emitting component 1A increases, and the influence of the non-radiation combined effect becomes severe. The luminous efficiency decreases. In order to reduce the area of the side surface 1S of the epitaxy structure 1, in a semiconductor light emitting component 1A having an upper surface 11a of 10,000 μm 2 , the upper surface 11a has a circular shape and a peripheral length of 354 μm. Is better than that having a square upper surface 11a and a peripheral length of 400 μm. That is, as the peripheral length of the upper surface 11a is shorter, the area of the side surface 1S of the epitaxy structure 1 is reduced, and the non-radiation combined effect of the rough side surface 1S can be reduced. When the shape of the upper surface 11a is circular, the distance between the front electrode 21 at the center of the upper surface 11a and the edge 8 is the same, so that the current propagation path is limited to the inner area of the epitaxy structure 1. Can be.

図３に示されるとおり、半導体発光部品１Ａの上表面１１ａは主出射面を含み、該主出射面は第一出射区域７１と第二出射区域７２を含む。第一出射区域７１は上表面１１ａの中央部分に位置し、第二出射区域７２は第一出射区域７１と辺縁８との間に位置する。発光部品１Ａを表示パネルなどの小電流の駆動装置、例えば駆動電流密度が０．１〜１Ａ／ｃｍ２の間にある駆動装置に応用するとき、上表面１１ａは近接場光度（near−field luminous intensity）分布Ｓを具備する。最大近接場光度１００％は第一出射区域７１内に位置し、第一出射区域７１内の近接場光度はいずれも最大近接場光度の７０％より大きく、第二出射区域７２内の近接場光度は最大近接場光度の０％〜７０％の間に入るが、好ましくは３０％〜７０％の間に入る。本実施例において、エピタキシ構造１の厚さが大幅に減少することにより、エピタキシ構造１を通過する電流の間の距離を低減し、電流流れがエピタキシ構造１の内部に集中しかつエピタキシ構造１の辺縁に拡散しないように制限することができる。また、正面電極２１と第二抵抗接触構造２２がそれぞれ上表面１１ａと下表面１２ａの中心に位置することにより、半導体発光部品１Ａの上表面１１ａで流れる電流流れの比率を低減し、かつ非輻射複合効果による発光効率の損失を低減することができる。第一出射区域７１の形状は上表面１１ａの形状と類似する円形であり、第一出射区域７１と第二出射区域７２の面積比は０．２５〜０．４５の間に入る。本実施例において、活性層１０と主出射面との間には分布ブラッグ反射層（ＤＢＲ）が設けられていない。 As shown in FIG. 3, the upper surface 11a of the semiconductor light emitting component 1A includes a main emission surface, and the main emission surface includes a first emission area 71 and a second emission area 72. The first emission area 71 is located at the center of the upper surface 11a, and the second emission area 72 is located between the first emission area 71 and the edge 8. When the light emitting component 1A is applied to a driving device of a small current such as a display panel, for example, a driving device having a driving current density of 0.1 to 1 A / cm 2 , the upper surface 11a has a near-field luminous intensity. intensity) distribution S. The maximum near-field intensity of 100% is located in the first exit area 71, the near-field intensity in the first exit area 71 is greater than 70% of the maximum near-field intensity, and the near-field intensity in the second exit area 72. Falls between 0% and 70% of the maximum near-field luminous intensity, but preferably falls between 30% and 70%. In this embodiment, the thickness of the epitaxy structure 1 is greatly reduced, so that the distance between the currents passing through the epitaxy structure 1 is reduced, the current flow is concentrated inside the epitaxy structure 1 and the epitaxy structure 1 It can be restricted so as not to diffuse to the periphery. Further, since the front electrode 21 and the second resistance contact structure 22 are located at the centers of the upper surface 11a and the lower surface 12a, respectively, the ratio of the current flowing on the upper surface 11a of the semiconductor light emitting component 1A is reduced, and The loss of luminous efficiency due to the combined effect can be reduced. The shape of the first emission area 71 is a circle similar to the shape of the upper surface 11a, and the area ratio between the first emission area 71 and the second emission area 72 falls between 0.25 and 0.45. In this embodiment, no distributed Bragg reflection layer (DBR) is provided between the active layer 10 and the main emission surface.

本実施例において、半導体発光部品１Ａの上表面１１ａの面積は１００００μｍ２より小さく、かつ上表面１１ａの形状が正方形であるとき、この周辺長さは４００μｍより小さく、上表面１１ａの形状が円形であるとき、この周辺長さは３５４μｍより小さい。外部の電流を流入させるため、幅が約５〜１０μｍの金属導線で正面電極２１を上表面１１ａ上に電気接続させるとき、金属導線に遮蔽される部分が上表面１１ａの少なくとも２．５％以上を占めるので、正面出射面の面積が低下する。このため、図２Ｂに示すとおり、半導体発光部品１Ａを応用するとき、背面電極９をサブ基板（sub-mount）６Ｂ上の電気回路構造、例えば導線構造に電気接続させることにより電気接続を形成し、かつ外部の透明電極６Ａを半導体発光部品１Ａの電極２１に電気接続させることにより外部の電流を流入させることができる。透明電極６Ａの材料は、導電性酸化物、例えば、酸化インジウム亜鉛、酸化インジウムスズ、ＩＧＺＯ（indium gallium zinc oxide）、酸化亜鉛又は酸化アルミニウム亜鉛を含む。他の実施例において、複数個の半導体発光部品１Ａとサブ基板６Ｂ上の電気回路構造とを電気接続させ、かつ透明電極６Ａで複数個の半導体発光部品１Ａの電極を電気接続させることにより、並列接続、直列接続又はこれらの組合せを形成することができる。本実施例の第一半導体積層１１は、例えばｎ型半導体であり、透明電極６Ａと電極２１は電気接続する。正面電極２１は金属材料で構成され、この材料はゲルマニウム（Ｇｅ）、金（Ａｕ）、ニッケル（Ｎi）、ゲルマニウム金合金又はゲルマニウム金ニッケル合金を含む。第二抵抗接触構造２２は、エピタキシ構造１の上表面１１ａと対向する下表面１２ａ上に位置し、かつ第二半導体積層１２と電気接続する。第二半導体積層１２の第二電気接触層１２４の不純物濃度は約１＊１０１９／ｃｍ３であり、第二抵抗接触構造２２の材料が透明酸化金属材料、例えば酸化インジウムスズであることにより、第二半導体積層１２と電気接続し、かつ光線が第二半導体積層１２の下表面１２ａを透過する比率を増加させることができる。第二抵抗接触構造２２の透明導電層３１の材料は、酸化インジウム亜鉛、ＩＧＺＯ（indium gallium zinc oxide）、酸化亜鉛又は酸化アルミニウム亜鉛を含むことができるが、これらに限定されるものではない。第二抵抗接触構造２２の金属反射層３２の材料は、銀（Ａｇ）、アルミニウム（Ａl）又は金（Ａｕ）などの放射光線に対する反射率が９５より大きい材料を含むことができる。透明導電層３１は、金属反射層３２と第二半導体積層１２を隔離することにより両者が直接接触することを防止し、かつ半導体発光部品１Ａを電流で長く駆動するとき、金属反射層３２と第二半導体積層１２との間に物理又は化学反応が発生することにより反射率又は導電率が低下することを防止することができる。透明導電層３１は、電流を反射積層３に分散させることにより、熱が反射積層３の一部分の区域に集中することを避けることもできる。透明導電層３１の屈折率が少なくとも第二半導体積層１２の屈折率の０．１以上であるので、両者の間の屈折率の差によって全反射面が形成され、かつ活性層１０が放射する一部分の光線を反射することができる。反射されていない他の光線は、透明導電層３１を透過した後再び金属反射層３２に反射される。金属反射層３２上を覆う遮断層３３の材料は、チタン（Ｔi）、プラチナ（Ｐｔ）、金（Ａｕ）、タングステン（Ｗ）、クラム（Ｃｒ）、これらの合金又はこれらの積層を含むことができる。遮断層３３は、金属反射層３２と粘着層４を隔離することにより、金属反射層３２の安定性を維持し、金属反射層３２と粘着層４との間に物理又は化学反応が発生することにより反射率又は導電率が低下することを防止する。粘着層４は、導電基板５と反射積層３を接合し、かつ電流が反射積層３と導電基板５との間で流れるようにする。粘着層４の材料は、インジウム（Iｎ）、チタン（Ｔi）、スズ（Ｓｎ）、金（Ａｕ）、これらの合金又はこれらの積層を含むことができる。導電基板５の材料は、シリコン（Ｓi）、ヒ化ガリウム（ＧａＡｓ）、銅タングステン合金（ＣｕＷ）、銅（Ｃｕ）又はモリブデン（Ｍｏ）を含むが、本発明はこれらに限定されるものではない。反射積層３の反対側の導電基板５上に設けられる背面電極９は金（Ａｕ）を含み、外部電流を流入させることに用いられる。 In this embodiment, when the area of the upper surface 11a of the semiconductor light emitting component 1A is smaller than 10000 μm 2 and the shape of the upper surface 11a is square, the peripheral length is smaller than 400 μm and the shape of the upper surface 11a is circular. At times, this perimeter is less than 354 μm. When the front electrode 21 is electrically connected to the upper surface 11a with a metal wire having a width of about 5 to 10 μm so that an external current flows, a portion shielded by the metal wire is at least 2.5% of the upper surface 11a. Therefore, the area of the front emission surface decreases. For this reason, as shown in FIG. 2B, when the semiconductor light emitting component 1A is applied, an electric connection is formed by electrically connecting the back electrode 9 to an electric circuit structure on the sub-substrate (sub-mount) 6B, for example, a conductor structure. In addition, by electrically connecting the external transparent electrode 6A to the electrode 21 of the semiconductor light emitting component 1A, an external current can flow. The material of the transparent electrode 6A includes a conductive oxide, for example, indium zinc oxide, indium tin oxide, IGZO (indium gallium zinc oxide), zinc oxide, or aluminum zinc oxide. In another embodiment, the plurality of semiconductor light emitting components 1A and the electric circuit structure on the sub-substrate 6B are electrically connected, and the electrodes of the plurality of semiconductor light emitting components 1A are electrically connected by the transparent electrode 6A, so that the parallel connection is achieved. Connections, series connections, or combinations thereof can be formed. The first semiconductor stack 11 of this embodiment is, for example, an n-type semiconductor, and the transparent electrode 6A and the electrode 21 are electrically connected. The front electrode 21 is made of a metal material, and this material includes germanium (Ge), gold (Au), nickel (Ni), a germanium gold alloy, or a germanium gold nickel alloy. The second resistance contact structure 22 is located on the lower surface 12 a facing the upper surface 11 a of the epitaxy structure 1 and is electrically connected to the second semiconductor stack 12. The impurity concentration of the second electrical contact layer 124 of the second semiconductor stack 12 is about 1 * 10 19 / cm 3 , and the material of the second resistance contact structure 22 is a transparent metal oxide material, for example, indium tin oxide. It is possible to increase the ratio of light transmitted through the lower surface 12 a of the second semiconductor stack 12 while being electrically connected to the second semiconductor stack 12. The material of the transparent conductive layer 31 of the second resistance contact structure 22 may include, but is not limited to, indium zinc oxide, IGZO (indium gallium zinc oxide), zinc oxide, or aluminum zinc oxide. The material of the metal reflective layer 32 of the second resistive contact structure 22 may include a material having a reflectivity of more than 95 for the emitted light, such as silver (Ag), aluminum (Al), or gold (Au). The transparent conductive layer 31 separates the metal reflective layer 32 and the second semiconductor laminate 12 from each other to prevent direct contact therebetween, and when the semiconductor light emitting component 1A is driven for a long time by the current, the metal conductive layer 31 and the second semiconductor laminate 12 are separated from each other. It is possible to prevent a decrease in reflectance or conductivity due to a physical or chemical reaction occurring between the two semiconductor layers 12. The transparent conductive layer 31 can also prevent the heat from being concentrated on a partial area of the reflective stack 3 by dispersing the current to the reflective stack 3. Since the refractive index of the transparent conductive layer 31 is at least 0.1 or more than the refractive index of the second semiconductor laminate 12, the total reflection surface is formed by the difference in the refractive index between the two, and the active layer 10 emits a portion. Of light can be reflected. Other light beams that are not reflected are transmitted through the transparent conductive layer 31 and then reflected again by the metal reflection layer 32. The material of the blocking layer 33 covering the metal reflective layer 32 may include titanium (Ti), platinum (Pt), gold (Au), tungsten (W), crumb (Cr), an alloy thereof, or a laminate thereof. it can. The blocking layer 33 maintains the stability of the metal reflection layer 32 by isolating the metal reflection layer 32 and the adhesive layer 4, so that a physical or chemical reaction occurs between the metal reflection layer 32 and the adhesion layer 4. Prevents the reflectivity or conductivity from decreasing. The adhesive layer 4 joins the conductive substrate 5 and the reflective laminate 3 and allows a current to flow between the reflective laminate 3 and the conductive substrate 5. The material of the adhesive layer 4 can include indium (In), titanium (Ti), tin (Sn), gold (Au), an alloy thereof, or a laminate thereof. The material of the conductive substrate 5 includes silicon (Si), gallium arsenide (GaAs), copper-tungsten alloy (CuW), copper (Cu), or molybdenum (Mo), but the present invention is not limited thereto. . The back electrode 9 provided on the conductive substrate 5 on the opposite side of the reflective laminate 3 contains gold (Au) and is used to allow an external current to flow.

（第二実施例）
図４Ａと図４Ｂは、本発明の第二実施例に係る半導体発光部品１Ｂと１Ｃを示す図である。第二実施例と第一実施例の相違点は、第二実施例のエピタキシ構造１が制御層１３をことにある。図４Ａに示す半導体発光部品１Ｂにおいて、制御層１３は第一半導体積層１１中に設けられ、図４Ｂに示す半導体発光部品１Ｃにおいて、制御層１３は第二半導体積層１２中に設けられる。制御層１３は、導電区域１３ｂと酸化区域１３ａを含み、酸化区域１３ａは、導電区域１３ｂを包囲するとともにエピタキシ構造１の側面１Ｓを露出させる。導電区域１３ｂの材料は、導電性の（AlxGa1-x)Asであり、０．９＜ｘ≦１であることができる。酸化区域１３ａの材料は、電気絶縁性のAlyOであり、０＜ｙ≦１であることができる。導電区域１３ｂと正面電極２１及び第二抵抗接触構造２２とが垂直方向に重なることにより、電流がエピタキシ構造１の一部分の場所で流れるようにする。図４Ｃは、本発明の他の実施例に係る半導体発光部品１Ｄを示す図である。この実施例において、第二抵抗接触構造２２は第二半導体積層１２の下表面１２ａ全面を覆う。第二抵抗接触構造２２は、横方向へ電流を拡散させること以外、第二抵抗接触構造２２と金属反射層３２を接合することができる。本実施例の第二抵抗接触構造２２、透明導電層３１及び金属反射層３２の材料として、第一実施例と同様な材料を採用することができる。 (Second embodiment)
4A and 4B are views showing semiconductor light emitting components 1B and 1C according to a second embodiment of the present invention. The difference between the second embodiment and the first embodiment is that the epitaxy structure 1 of the second embodiment has a control layer 13. In the semiconductor light emitting component 1B shown in FIG. 4A, the control layer 13 is provided in the first semiconductor stack 11, and in the semiconductor light emitting component 1C shown in FIG. 4B, the control layer 13 is provided in the second semiconductor stack 12. The control layer 13 includes a conductive area 13b and an oxidized area 13a. The oxidized area 13a surrounds the conductive area 13b and exposes the side surface 1S of the epitaxy structure 1. The material of the conductive area 13b is conductive (Al x Ga 1 -x ) As, and 0.9 <x ≦ 1. The material of the oxidized area 13a is electrically insulating Al y O, and 0 <y ≦ 1. The vertical overlap of the conductive area 13b with the front electrode 21 and the second resistive contact structure 22 allows current to flow at a portion of the epitaxy structure 1. FIG. 4C is a view showing a semiconductor light emitting component 1D according to another embodiment of the present invention. In this embodiment, the second resistance contact structure 22 covers the entire lower surface 12 a of the second semiconductor stack 12. The second resistance contact structure 22 can join the second resistance contact structure 22 and the metal reflection layer 32, other than spreading the current in the lateral direction. As the material of the second resistance contact structure 22, the transparent conductive layer 31, and the metal reflection layer 32 of the present embodiment, the same material as that of the first embodiment can be adopted.

以上、これらの発明の実施例を図面により詳述してきたが、実施例はこの発明の例示にしか過ぎないものであるため、この発明は実施例の構成にのみ限定されるものではなく、この発明の要旨を逸脱しない範囲の設計の変更等があってもこの発明に含まれることは勿論である。   As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, since the embodiments are merely examples of the present invention, the present invention is not limited only to the configurations of the embodiments. Of course, even if there is a change in the design within a range not departing from the gist of the invention, it is included in the present invention.

１Ａ、１Ｂ、１Ｃ、１Ｄ 半導体発光部品
１ エピタキシ構造
１Ｓ 側面
１０ 活性層
１１ 第一半導体積層
１１１ 第一電気制限層
１１２ 第一電気包装層
１１３ 第一電気窓口層
１１４ 第一電気接触層
１１ａ 上表面
１２ 第二半導体積層
１２１ 第二電気制限層
１２２ 第二電気包装層
１２３ 第二電気窓口層
１２４ 第二電気接触層
１２ａ 下表面
１３ 制御層
１３ａ 酸化区域
１３ｂ 導電区域
２１ 正面電極
２２ 第二抵抗接触構造
３ 反射積層
３１ 透明導電層
３２ 金属反射層
３３ 遮断層
４ 粘着層
５ 導電基板
６Ａ 透明電極
６Ｂ サブ基板
７１ 第一出射区域
７２ 第二出射区域
８ 辺縁
９ 背面電極
Ｓ 近接場光度分布 Reference Signs List 1A, 1B, 1C, 1D Semiconductor light emitting component 1 Epitaxy structure 1S Side surface 10 Active layer 11 First semiconductor lamination 111 First electric limiting layer 112 First electric packaging layer 113 First electric window layer 114 First electric contact layer 11a Upper surface DESCRIPTION OF SYMBOLS 12 2nd semiconductor lamination 121 2nd electric restriction layer 122 2nd electric packaging layer 123 2nd electric contact layer 124 2nd electric contact layer 12a Lower surface 13 Control layer 13a Oxidation area 13b Conduction area 21 Front electrode 22 Second resistance contact structure Reference Signs List 3 reflective laminate 31 transparent conductive layer 32 metal reflective layer 33 blocking layer 4 adhesive layer 5 conductive substrate 6A transparent electrode 6B sub-substrate 71 first emission area 72 second emission area 8 edge 9 back electrode S near-field luminous intensity distribution

Claims (10)

半導体発光部品であって、
上表面を有し、かつ、第一半導体積層、第二半導体積層、及び前記第一半導体積層と前記第二半導体積層との間に位置して光線を生成する活性層を含みエピタキシ層と、
前記第一半導体積層の上に位置する正面電極と、
前記エピタキシ層の下に位置する背面電極と、
前記正面電極と前記背面電極との間に位置する接触構造とを含み、
前記正面電極、前記背面電極及び前記接触構造が垂直方向に重なる、半導体発光部品。 A semiconductor light emitting component,
Having an upper surface, and a first semiconductor stack, a second semiconductor stack, and an epitaxy layer including an active layer that generates a light beam located between the first semiconductor stack and the second semiconductor stack,
A front electrode located on the first semiconductor stack,
A back electrode located below the epitaxy layer;
Including a contact structure located between the front electrode and the back electrode,
A semiconductor light emitting component, wherein the front electrode, the back electrode, and the contact structure vertically overlap. 半導体発光部品であって、
上表面を有し、かつ、第一半導体積層、第二半導体積層、及び前記第一半導体積層と前記第二半導体積層との間に位置して光線を生成する活性層を含みエピタキシ層と、
前記エピタキシ層の中に位置し、かつ、導電区域及び前記導電区域を囲む電気絶縁区域を含む制御層と、
前記第一半導体積層の上に位置する正面電極と、
前記エピタキシ層の下に位置する背面電極と、
前記正面電極と前記背面電極との間に位置する接触構造とを含み、
前記導電区域、前記正面電極、前記背面電極及び前記接触構造が垂直方向に重なる、半導体発光部品。 A semiconductor light emitting component,
Having an upper surface, and a first semiconductor stack, a second semiconductor stack, and an epitaxy layer including an active layer that generates a light beam located between the first semiconductor stack and the second semiconductor stack,
A control layer located in the epitaxy layer and including a conductive area and an electrically insulating area surrounding the conductive area;
A front electrode located on the first semiconductor stack,
A back electrode located below the epitaxy layer;
Including a contact structure located between the front electrode and the back electrode,
A semiconductor light emitting component wherein the conductive area, the front electrode, the back electrode, and the contact structure vertically overlap. 半導体発光部品であって、
基板と、
前記基板の上に位置し、かつ上表面を有し、かつ、第一半導体積層、第二半導体積層、及び前記第一半導体積層と前記第二半導体積層との間に位置して光線を生成する活性層を含みエピタキシ層と、
前記第一半導体積層の上に位置する正面電極と、
前記エピタキシ層の下に位置する背面電極と、
前記正面電極と前記背面電極との間に位置する接触構造と、
前記第二半導体積層及び前記接触構造を覆う反射積層とを含み、
前記正面電極、前記背面電極及び前記接触構造が垂直方向に重なる、半導体発光部品。 A semiconductor light emitting component,
Board and
It is located on the substrate and has an upper surface, and generates a light beam located between the first semiconductor stack, the second semiconductor stack, and the second semiconductor stack, and the first semiconductor stack. An epitaxy layer including an active layer;
A front electrode located on the first semiconductor stack,
A back electrode located below the epitaxy layer;
A contact structure located between the front electrode and the back electrode,
Including the second semiconductor stack and a reflective stack that covers the contact structure,
A semiconductor light emitting component, wherein the front electrode, the back electrode, and the contact structure vertically overlap. 前記導電区域の材料は（ＡｌｘＧａ１−ｘ）Ａｓであり、かつ０．９＜ｘ≦１であり、
前記電気絶縁区域の材料はＡｌｙＯであり、０＜ｙ＜１である、請求項２に記載の半導体発光部品。 The material of the conductive area is (Al x Ga 1-x ) As, and 0.9 <x ≦ 1;
The semiconductor light-emitting component according to claim 2, wherein a material of the electrically insulating area is Al y O, and 0 <y <1. 前記接触構造は透明導電材料を含む、請求項１〜４のいずれか一項に記載の半導体発光部品。   The semiconductor light-emitting component according to claim 1, wherein the contact structure includes a transparent conductive material. 前記正面電極は前記上表面の面積の１％〜１０％を占める、請求項１〜５のいずれか一項に記載の半導体発光部品。   The semiconductor light-emitting component according to claim 1, wherein the front electrode occupies 1% to 10% of the area of the upper surface. 半導体発光部品であって、
基板と、
前記基板の上に位置し、かつ第一厚さ及び上表面を有するエピタキシ層と
反射積層とを含み、
前記エピタキシ層は、
第一半導体積層と、
前記第一半導体積層の上に位置して光線を生成する活性層と、
前記活性層の上に位置し、かつ第二厚さを有する第二半導体積層とを含み、
前記反射積層は前記第二半導体積層を覆い、
前記上表面は第一周長を有し、かつ前記第一厚さと前記第一周長の比は０．７５％以下であり、かつ、第二厚さは１μｍ以下である、半導体発光部品。 A semiconductor light emitting component,
Board and
An epitaxy layer located on the substrate and having a first thickness and an upper surface, and a reflective stack,
The epitaxy layer,
A first semiconductor stack;
An active layer for generating a light beam located on the first semiconductor stack;
A second semiconductor stack located on the active layer, and having a second thickness,
The reflective stack covers the second semiconductor stack;
The semiconductor light emitting component, wherein the upper surface has a first peripheral length, a ratio of the first thickness to the first peripheral length is 0.75% or less, and a second thickness is 1 μm or less. 半導体発光部品であって、
基板と、
前記基板の上に位置し、かつ第一厚さ及び上表面を有するエピタキシ層と
前記エピタキシ層の中に位置し、かつ、導電区域及び前記導電区域を囲む電気絶縁区域を含む制御層と、
反射積層とを含み、
前記エピタキシ層は、
第一半導体積層と、
前記第一半導体積層の上に位置して光線を生成する活性層と、
前記活性層の上に位置し、かつ第二厚さを有する第二半導体積層とを含み、
前記反射積層は前記第二半導体積層を覆い、
前記第一厚さは３μｍより小さく、かつ、第二厚さは１μｍ以下である、半導体発光部品。 A semiconductor light emitting component,
Board and
An epitaxy layer located on the substrate and having a first thickness and an upper surface; and a control layer located in the epitaxy layer and including a conductive area and an electrically insulating area surrounding the conductive area;
Including a reflective laminate,
The epitaxy layer,
A first semiconductor stack;
An active layer for generating a light beam located on the first semiconductor stack;
A second semiconductor stack located on the active layer, and having a second thickness,
The reflective stack covers the second semiconductor stack;
The semiconductor light emitting component, wherein the first thickness is less than 3 μm and the second thickness is 1 μm or less. 前記反射積層は、
前記第二半導体積層を覆う透明導電層と、
前記透明導電層を覆う金属反射層と、
前記金属反射層を覆う遮断層とを含む、請求項７または８に記載の半導体発光部品。 The reflective laminate,
A transparent conductive layer covering the second semiconductor stack,
A metal reflective layer covering the transparent conductive layer,
The semiconductor light-emitting component according to claim 7, further comprising: a blocking layer that covers the metal reflective layer. 前記活性層が生成する光線は前記上表面を透過し、
前記上表面は、第一出射区域、第二出射区域及び最大近接場光度を有し、
前記第一出射区域内の近接場光度は最大近接場光度の７０％〜１００％の間にあり、前記第二出射区域内の近接場光度は最大近接場光度の０％〜７０％の間にあり、前記第一出射区域の面積と前記第二出射区域の面積の比は０．２５〜０．４５の間にある、請求項１〜９のいずれか一項に記載の半導体発光部品。 Light rays generated by the active layer are transmitted through the upper surface,
The upper surface has a first exit area, a second exit area, and a maximum near-field luminosity,
The near-field light intensity in the first exit area is between 70% and 100% of the maximum near-field intensity, and the near-field intensity in the second exit area is between 0% and 70% of the maximum near-field intensity. The semiconductor light emitting component according to any one of claims 1 to 9, wherein a ratio of an area of the first emission area to an area of the second emission area is between 0.25 and 0.45.
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