JPH07153951A - Composite semiconductor element and manufacture thereof - Google Patents
Composite semiconductor element and manufacture thereofInfo
- Publication number
- JPH07153951A JPH07153951A JP5301463A JP30146393A JPH07153951A JP H07153951 A JPH07153951 A JP H07153951A JP 5301463 A JP5301463 A JP 5301463A JP 30146393 A JP30146393 A JP 30146393A JP H07153951 A JPH07153951 A JP H07153951A
- Authority
- JP
- Japan
- Prior art keywords
- region
- electrode
- conductivity type
- conductivity
- igbt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000002131 composite material Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims abstract description 55
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052710 silicon Inorganic materials 0.000 abstract description 15
- 239000010703 silicon Substances 0.000 abstract description 15
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000003754 machining Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000010485 coping Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、高耐圧、大電流を扱
う電力用トランジスタ特に絶縁ゲート型バイポーラトラ
ンジスタ（以下、本文では「ＩＧＢＴ」と略す）とＭＯ
Ｓ型電界効果トランジスタ（以下、本文では「ＭＯＳＦ
ＥＴ」と略す）を含む複合型半導体素子およびその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power transistor for handling a high withstand voltage and a large current, particularly an insulated gate bipolar transistor (hereinafter abbreviated as "IGBT" in the text) and an MO transistor.
S-type field effect transistor (hereinafter referred to as "MOSF"
And a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来の高耐圧、大電流用のＩＧＢＴとＭ
ＯＳＦＥＴの典型的な構造と等価回路を図５（ａ）
（ｂ）および図６（ａ）（ｂ）に示す。図５，図６にお
いて、１はＰ+ シリコン基板、２はＮ+ 領域、３はＮ-
領域、４はＰ+ 領域、５はＮ+ 領域、６はゲート酸化
膜、７はポリシリコン膜、８はアルミニウム膜からなる
電極、９は電極用の金属膜である。2. Description of the Related Art Conventional IGBT and M for high breakdown voltage and large current
A typical structure of an OSFET and an equivalent circuit are shown in FIG.
6B and FIG. 6A and FIG. 6B. 5 and 6, 1 is a P + silicon substrate, 2 is an N + region, and 3 is N −.
Regions 4 are P + regions, 5 are N + regions, 6 is a gate oxide film, 7 is a polysilicon film, 8 is an electrode made of an aluminum film, and 9 is a metal film for electrodes.
【０００３】図５に示すＩＧＢＴと図６に示すＭＯＳＦ
ＥＴとの構造上の違いは、ＩＧＢＴはコレクタ領域とし
てＰ+ 領域（Ｐ+ シリコン基板１）を有していることで
あり、そのためにＩＧＢＴの出力段はバイポーラモード
となることである。The IGBT shown in FIG. 5 and the MOSF shown in FIG.
The structural difference from ET is that the IGBT has a P + region (P + silicon substrate 1) as a collector region, and therefore the output stage of the IGBT is in a bipolar mode.
【０００４】[0004]
【発明が解決しようとする課題】そのため、電子機器に
用いる際、特に周波数特性に留意して、低速タイプには
ＩＧＢＴを用い、また高速タイプにはＭＯＳＦＥＴを用
いるというように使い分けなければならなかった。ま
た、ＩＧＢＴをモータ駆動用として用いる際には、還流
用ダイオードとして高速ダイオードをＩＧＢＴのコレク
タ・エミッタ間に外付けする必要があった。Therefore, when used in electronic equipment, it is necessary to use IGBTs for low-speed types and MOSFETs for high-speed types, paying particular attention to frequency characteristics. . Further, when the IGBT is used for driving a motor, it is necessary to externally attach a high speed diode as a free wheeling diode between the collector and the emitter of the IGBT.
【０００５】この発明の第１の目的は、種々の電子機器
の仕様に対応させるために、１チップ内にＩＧＢＴとＭ
ＯＳＦＥＴを共存させることによって幅広い周波数変化
に対応できる複合型半導体素子およびその製造方法を提
供することである。また、この発明の第２の目的は、Ｉ
ＧＢＴのコレクタ・エミッタ間に寄生の高速ダイオード
を形成した複合型半導体素子およびその製造方法を提供
することである。A first object of the present invention is to provide an IGBT and an M in one chip in order to meet the specifications of various electronic devices.
It is to provide a composite semiconductor element capable of coping with a wide range of frequency changes by coexisting OSFETs, and a manufacturing method thereof. A second object of the present invention is I
To provide a composite type semiconductor device in which a parasitic high speed diode is formed between a collector and an emitter of a GBT and a method for manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】請求項１記載の複合型半
導体素子は、一導電型基板と、この一導電型基板の一主
面上に形成するとともに一導電型基板がわに露出面を形
成した高濃度他導電型の第１の領域と、この第１の領域
上に形成した低濃度他導電型の第２の領域と、この第２
の領域内の表面に形成した高濃度一導電型の第３の領域
と、この第３の領域内の表面に形成した高濃度他導電型
の第４の領域とを備えている。そして、第３の領域の上
部に第１の電極を設け、第３および第４の領域上に第２
の電極を設け、第１の領域の露出面および一導電型基板
に接続する共通電極を設けている。According to a first aspect of the present invention, there is provided a composite type semiconductor device having a one-conductivity type substrate and a one-conductivity type substrate formed on one main surface of the one-conductivity type substrate. The formed high concentration other conductivity type first region, the low concentration other conductivity type second region formed on the first region, and the second region
A high-concentration one-conductivity type third region formed on the surface in the region and a high-concentration other-conductivity type fourth region formed on the surface in the third region. Then, the first electrode is provided on the third region, and the second electrode is provided on the third and fourth regions.
Is provided, and a common electrode connected to the exposed surface of the first region and the one conductivity type substrate is provided.
【０００７】請求項２記載の複合型半導体素子は、一導
電型基板と、この一導電型基板の一主面上に形成すると
ともに一導電型基板がわに露出面を形成した高濃度他導
電型の第１の領域と、この第１の領域上に形成した低濃
度他導電型の第２の領域と、この第２の領域内の表面に
形成した高濃度一導電型の第３の領域と、この第３の領
域内の表面に形成した高濃度他導電型の第４の領域とを
備えている。そして、第３の領域の上部に第１の電極を
設け、第３および第４の領域上に第２の電極を設け、第
１の領域の露出面に接続する第３の電極を設け、一導電
型基板に接続する第４の電極を設けている。According to a second aspect of the present invention, there is provided a composite type semiconductor device having a one-conductivity type substrate and a high-concentration other conductor formed on one main surface of the one-conductivity type substrate and having an exposed surface of the one-conductivity type substrate. Type first region, a low concentration other conductivity type second region formed on the first region, and a high concentration one conductivity type third region formed on the surface in the second region. And a high-concentration other conductivity type fourth region formed on the surface of the third region. A first electrode is provided on the third region, a second electrode is provided on the third and fourth regions, and a third electrode connected to the exposed surface of the first region is provided. A fourth electrode connected to the conductive type substrate is provided.
【０００８】請求項３記載の複合型半導体素子は、一導
電型基板と、この一導電型基板の一主面上に形成すると
ともに一導電型基板がわに露出面を形成した高濃度他導
電型の第１の領域と、この第１の領域上に形成した低濃
度他導電型の第２の領域と、この第２の領域内の表面に
複数形成した高濃度一導電型の第３の領域と、この複数
の第３の領域内の表面に形成した高濃度他導電型の第４
の領域とを備えている。そして、複数の第３の領域の上
部に第１の電極を設け、複数の第３および第４の領域上
に第２の電極を設け、第１の領域の露出面に接続する第
３の電極を設け、一導電型基板に接続する第４の電極を
設けている。According to a third aspect of the present invention, there is provided a composite type semiconductor device comprising a one-conductivity type substrate and a high-concentration other conductor formed on one main surface of the one-conductivity type substrate and having an exposed surface of the one-conductivity type substrate. Type first region, a low concentration other conductivity type second region formed on the first region, and a plurality of high concentration one conductivity type third regions formed on the surface in the second region. Region and a high-concentration-other-conductivity-type fourth layer formed on the surface in the plurality of third regions.
Area. A first electrode is provided on the plurality of third regions, a second electrode is provided on the plurality of third and fourth regions, and a third electrode is connected to the exposed surface of the first region. And a fourth electrode connected to the one conductivity type substrate.
【０００９】請求項４記載の複合型半導体素子の製造方
法は、一導電型基板の一主面上に高濃度他導電型の第１
の領域を形成し、この第１の領域上に低濃度他導電型の
第２の領域を形成し、この第２の領域内の表面に高濃度
一導電型の第３の領域を形成し、この第３の領域内の表
面に高濃度他導電型の第４の領域を形成する工程と、一
導電型基板の他主面から第１の領域に達するまで部分的
に除去して凹部を形成する工程と、第３の領域の上部、
第３および第４の領域上、第１の領域の露出面、および
一導電型基板の他主面に、それぞれ電極を形成する工程
とを含むことを特徴とする。According to a fourth aspect of the present invention, there is provided a method of manufacturing a composite type semiconductor device, wherein a high-concentration other-conductivity-type first substrate is provided on one main surface of a one-conductivity-type substrate.
Region is formed, a low concentration other conductivity type second region is formed on the first region, and a high concentration one conductivity type third region is formed on the surface in the second region, A step of forming a fourth region of a high-concentration other conductivity type on the surface in the third region, and a recess by partially removing from the other main surface of the one conductivity type substrate until reaching the first region. And the upper part of the third region,
Forming an electrode on each of the third and fourth regions, the exposed surface of the first region, and the other main surface of the one conductivity type substrate.
【００１０】[0010]
【作用】請求項１記載の構成によれば、ゲートを共通と
するＩＧＢＴとＭＯＳＦＥＴとが１チップ内に共存して
いる。すなわち、ＩＧＢＴは、第１の電極をゲート電極
とし、第２の電極をエミッタ電極とし、共通電極をコレ
クタ電極として、一導電型基板（コレクタ），第１の領
域，第２の領域，第３の領域および第４の領域（エミッ
タ）からなる。また、ＭＯＳＦＥＴは、露出面を形成し
た第１の領域（ドレイン），第２の領域，第３の領域お
よび第４の領域（ソース）からなる。そして、第１の領
域の露出面と一導電型基板を共通電極で接続しているこ
とにより、ＭＯＳＦＥＴの寄生ダイオード（第２および
第３の領域）がＩＧＢＴのコレクタ・エミッタ間に形成
されることになる。According to the structure of the first aspect, the IGBT and the MOSFET having the common gate coexist in one chip. That is, the IGBT uses the first electrode as a gate electrode, the second electrode as an emitter electrode, and the common electrode as a collector electrode, and has one conductivity type substrate (collector), a first region, a second region, and a third region. Area and a fourth area (emitter). The MOSFET is composed of a first region (drain), a second region, a third region and a fourth region (source) having an exposed surface. The parasitic diode (second and third regions) of the MOSFET is formed between the collector and the emitter of the IGBT by connecting the exposed surface of the first region and the substrate of one conductivity type with a common electrode. become.
【００１１】請求項２記載の構成によれば、請求項１と
同様、ゲートを共通とするＩＧＢＴとＭＯＳＦＥＴとが
１チップ内に共存している。そして、第１の領域の露出
面に接続した第３の電極がＭＯＳＦＥＴのドレイン電極
となり、一導電型基板に接続した第４の電極がＩＧＢＴ
のコレクタ電極となる。したがって、ＩＧＢＴとＭＯＳ
ＦＥＴを選択的に動作させることができる。また、第３
の電極と第４の電極を接続すれば、請求項１と同様、Ｍ
ＯＳＦＥＴの寄生ダイオードがＩＧＢＴのコレクタ・エ
ミッタ間に形成されることになる。According to the second aspect of the invention, similarly to the first aspect, the IGBT and the MOSFET having the common gate coexist in one chip. The third electrode connected to the exposed surface of the first region becomes the drain electrode of the MOSFET, and the fourth electrode connected to the one conductivity type substrate is the IGBT.
Will be the collector electrode of. Therefore, IGBT and MOS
The FET can be selectively operated. Also, the third
If the electrode of 4 and the fourth electrode are connected, M
The parasitic diode of the OSFET will be formed between the collector and the emitter of the IGBT.
【００１２】請求項３記載の構成によれば、第２の領域
内の表面に複数の第３の領域を形成し、この複数の第３
の領域内の表面に第４の領域を形成し、複数の第３の領
域の上部に第１の電極を設け、複数の第３および第４の
領域上に第２の電極を設けることにより、複数の第１・
第２の電極をＩＧＢＴのゲート・エミッタ電極とＭＯＳ
ＦＥＴのゲート・ソース電極とに使い分けるようにして
いる。そして、第１の領域の露出面に接続した第３の電
極がＭＯＳＦＥＴのドレイン電極となり、一導電型基板
に接続した第４の電極がＩＧＢＴのコレクタ電極とな
る。したがって、ＩＧＢＴとＭＯＳＦＥＴは１チップ内
に独立した構成となり、選択的に動作させることができ
る。また、電極間の接続の仕方により、請求項１または
請求項２と同様の動作を行うことができる。According to the structure of claim 3, a plurality of third regions are formed on the surface in the second region, and the plurality of third regions are formed.
By forming the fourth region on the surface in the region of, the first electrode is provided on the plurality of third regions, and the second electrode is provided on the plurality of third and fourth regions, Multiple 1st
The second electrode is the gate / emitter electrode of the IGBT and the MOS
The gate and source electrodes of the FET are used separately. The third electrode connected to the exposed surface of the first region becomes the drain electrode of the MOSFET, and the fourth electrode connected to the one conductivity type substrate becomes the collector electrode of the IGBT. Therefore, the IGBT and the MOSFET have independent structures in one chip and can be selectively operated. Further, the same operation as in claim 1 or claim 2 can be performed depending on the way of connecting the electrodes.
【００１３】[0013]
【実施例】以下、この発明の実施例を図面を参照しなが
ら説明する。図１（ａ）はこの発明の第１の実施例の複
合型半導体素子の模式断面図、図１（ｂ）はその等価回
路図である。図１において、１はＰ+ シリコン基板（一
導電型基板）、２はＮ+ 領域（第１の領域）、２ａは露
出面、３はＮ- 領域（第２の領域）、４はＰ+ 領域（第
３の領域）、５はＮ+ 領域（第４の領域）、６はゲート
酸化膜、７はポリシリコン膜、８ａはアルミニウム膜か
らなるゲート電極（第１の電極）、８ｂはアルミニウム
膜からなるエミッタ電極（第２の電極）、９は電極用の
金属膜（共通電極）である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a schematic sectional view of a composite type semiconductor device according to a first embodiment of the present invention, and FIG. 1B is its equivalent circuit diagram. In FIG. 1, 1 is a P + silicon substrate (one conductivity type substrate), 2 is an N + region (first region), 2a is an exposed surface, 3 is an N − region (second region), and 4 is P +. Region (third region), 5 is N + region (fourth region), 6 is a gate oxide film, 7 is a polysilicon film, 8a is a gate electrode (first electrode) made of an aluminum film, and 8b is aluminum. An emitter electrode (second electrode) made of a film, and 9 is a metal film (common electrode) for the electrode.
【００１４】この複合型半導体素子には、ゲートを共通
とするＩＧＢＴとＭＯＳＦＥＴとが１チップ内に共存し
ている。すなわち、ＩＧＢＴは、Ｐ+ シリコン基板１
と、Ｎ + 領域２と、Ｎ- 領域３と、Ｐ+ 領域４と、Ｎ+
領域５とからなる。また、ＭＯＳＦＥＴは、Ｐ+ シリコ
ン基板１を除去した露出面２ａ上のＮ+ 領域２と、Ｎ-
領域３と、Ｐ+ 領域４と、Ｎ+ 領域５とからなる。A gate is commonly used for this composite semiconductor device.
IGBT and MOSFET coexist in the same chip
ing. That is, the IGBT is P+Silicon substrate 1
And N +Region 2 and N-Region 3 and P+Region 4 and N+
And area 5. Also, the MOSFET is P+Silico
N on the exposed surface 2a from which the substrate 1 has been removed+Region 2 and N-
Region 3 and P+Region 4 and N+And area 5.
【００１５】このように構成される複合型半導体素子の
製造方法を説明する。（１００）面のＰ+ シリコン基板
１にＮ+ 層２をエピタキシャル法で形成し、つづいてＮ
- 層３をエピタキシャル法で形成する。つぎにＮ- 層内
３に選択拡散によってＰ+ 領域４を形成し、さらにその
Ｐ+ 領域４内に拡散によってＮ+ 領域５を形成する。Ｐ
+ シリコン基板１はＩＧＢＴのコレクタ領域となり、Ｎ
+ 層は２はバッファ領域、Ｎ+ 領域５はエミッタ領域と
なる。A method of manufacturing the composite semiconductor device having the above structure will be described. An N + layer 2 is formed by an epitaxial method on a P + silicon substrate 1 having a (100) plane, and then N
- forming a layer 3 in the epitaxial method. Next, a P + region 4 is formed in the N − layer 3 by selective diffusion, and an N + region 5 is further formed in the P + region 4 by diffusion. P
+ Silicon substrate 1 becomes the collector region of the IGBT, and N
The + layer 2 serves as a buffer region, and the N + region 5 serves as an emitter region.
【００１６】さらに、ＩＧＢＴのゲートとして、Ｐ+ 領
域４上に厚み５００〜１０００Åの二酸化珪素膜６を形
成し、その上にポリシリコン膜７を形成する。その後、
アルミニウム膜からなるゲート電極８ａとエミッタ電極
８ｂを形成する。このようにして得たＩＧＢＴのコレク
タ領域（Ｐ+ シリコン基板１）の一部を機械的、化学的
方法などでバッファ領域（Ｎ+ 層２）に到達する深さま
で除去して露出面２ａを形成し、その後ＩＧＢＴのコレ
クタ面およびＮ+ 層２の露出面２ａ（凹部）に電極用金
属膜９を形成する。Further, as a gate of the IGBT, a silicon dioxide film 6 having a thickness of 500 to 1000 Å is formed on the P + region 4, and a polysilicon film 7 is formed thereon. afterwards,
A gate electrode 8a and an emitter electrode 8b made of an aluminum film are formed. An exposed surface 2a is formed by removing a part of the collector region (P + silicon substrate 1) of the IGBT thus obtained by a mechanical or chemical method to a depth reaching the buffer region (N + layer 2). After that, the electrode metal film 9 is formed on the collector surface of the IGBT and the exposed surface 2a (recess) of the N + layer 2.
【００１７】このようにしてゲートを共通とするＩＧＢ
ＴとＭＯＳＦＥＴの複合型半導体素子が完成する。この
実施例によれば、ＩＧＢＴのコレクタ領域（Ｐ+ シリコ
ン基板１）とＮ+層２の露出面２ａを金属膜９で接続す
ることにより、図１（ｂ）に示すように、ＭＯＳＦＥＴ
の寄生ダイオード１０がＩＧＢＴのコレクタ・エミッタ
間に形成される。そのため、モータ駆動用として用いる
際に、別のダイオードを外付けする必要がない。このよ
うに、ダイオード１０を内臓したＩＧＢＴを容易に得る
ことができ、これを電子機器に用いることによって幅広
い周波数に対応でき、その結果、部品点数の削減、部品
材料費の低減、信頼性の向上などに効果がある。Thus, the IGB having the common gate
A composite semiconductor element of T and MOSFET is completed. According to this embodiment, by connecting the collector region (P + silicon substrate 1) of the IGBT and the exposed surface 2a of the N + layer 2 with the metal film 9, as shown in FIG.
Is formed between the collector and the emitter of the IGBT. Therefore, when used for driving a motor, it is not necessary to attach another diode externally. As described above, it is possible to easily obtain an IGBT having the diode 10 built therein, and it is possible to support a wide range of frequencies by using the IGBT in an electronic device. As a result, the number of parts, the material cost of parts, and the reliability are improved. And so on.
【００１８】図２（ａ）はこの発明の第２の実施例の複
合型半導体素子の模式断面図、図２（ｂ）はその等価回
路図である。図２において、図１と対応する部分には同
一符号を付し、その説明を省略する。この実施例が第１
の実施例と異なるところは、ＩＧＢＴのコレクタ領域
（Ｐ+シリコン基板１）とＮ+ 層２の露出面２ａを二酸
化珪素膜１１などで絶縁し、Ｐ + シリコン基板１にＩＧ
ＢＴのコレクタ電極となる電極用金属膜（第４の電極）
９ａを形成するとともに、Ｎ+ 層２の露出面２ａ（凹
部）にＭＯＳＦＥＴのドレイン電極となる電極用金属膜
（第３の電極）９ｂを形成したことである。FIG. 2A shows a second embodiment of the present invention.
FIG. 2B is a schematic cross-sectional view of the compound semiconductor element
It is a road map. 2 are the same as those in FIG.
A reference numeral is given and its description is omitted. This embodiment is the first
The difference from the embodiment is that the collector region of the IGBT is
(P+Silicon substrate 1) and N+The exposed surface 2a of layer 2 is diacid
Insulate with silicon oxide film 11 etc. +IG on silicon substrate 1
Metal film for electrode that becomes the collector electrode of BT (4th electrode)
9a is formed and N+Exposed surface 2a of layer 2 (concave
Part), a metal film for an electrode to be the drain electrode of the MOSFET
That is, (third electrode) 9b is formed.
【００１９】この実施例によれば、ＩＧＢＴとＭＯＳＦ
ＥＴを選択的に動作させることができる。また、電極用
金属膜９ａと９ｂを接続すれば、第１の実施例と同様、
ＭＯＳＦＥＴの寄生ダイオード１０がＩＧＢＴのコレク
タ・エミッタ間に形成されることになる。図３（ａ）は
この発明の第３の実施例の複合型半導体素子の模式断面
図、図３（ｂ）はその等価回路図である。図３におい
て、図２と対応する部分には同一符号を付し、その説明
を省略する。According to this embodiment, the IGBT and the MOSF are
The ET can be selectively operated. Further, if the electrode metal films 9a and 9b are connected, as in the first embodiment,
The parasitic diode 10 of the MOSFET is formed between the collector and the emitter of the IGBT. FIG. 3A is a schematic sectional view of a composite type semiconductor device according to a third embodiment of the present invention, and FIG. 3B is its equivalent circuit diagram. 3, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.
【００２０】この実施例が第２の実施例と異なるところ
は、ＩＧＢＴとＭＯＳＦＥＴのそれぞれに対応するＰ+
領域４、Ｎ+ 領域５、ゲート酸化膜６、ポリシリコン膜
７およびアルミニウム膜からなる電極８ａ，８ｂを設け
たことであり、それぞれ専用のゲートＧ1 ，Ｇ2 を設け
ている。この実施例によれば、１チップ内にＩＧＢＴと
ＭＯＳＦＥＴを独立させた複合型半導体素子を得ること
ができる。電極８ａ，８ｂ間および電極用金属膜９ａ，
９ｂ間の接続の仕方により、第１の実施例または第２の
実施例と同様の動作を行うことができる。The difference of this embodiment from the second embodiment is that P + corresponding to each of the IGBT and the MOSFET.
The regions 4, N + regions 5, the gate oxide film 6, the polysilicon film 7 and the electrodes 8a and 8b made of an aluminum film are provided, and dedicated gates G 1 and G 2 are provided respectively. According to this embodiment, it is possible to obtain a composite semiconductor device in which the IGBT and the MOSFET are independent in one chip. Between the electrodes 8a and 8b and the electrode metal film 9a,
The same operation as that of the first or second embodiment can be performed depending on the connection method between 9b.
【００２１】なお、上記実施例では説明を容易にするた
め図面では、ＩＧＢＴのコレクタ領域（Ｐ+ シリコン基
板１）を左側とし、Ｎ+ 層２の露出面２ａ（凹部）を右
側とした。しかし、実際の製造工程においては、Ｐ+ シ
リコン基板１の破損を防ぐため、図４に示すように、凹
部として小さな穴２１や溝２２を組み合わせることが多
い。また、電流容量を高めるために穴２１や溝２２を増
やす必要があり、穴２１や溝２２を精密加工する必要が
あり、たとえば、超音波加工、レーザー加工、放電加工
などで行う。また、複数個の穴２１や溝２２への電極形
成は、まずバンブ技術またはフリップチップ技術それに
基盤配線技術によって簡単に実現できる。なお、図４
（ａ），（ｂ）はそれぞれ穴２１，溝２２を形成したＰ
+ シリコン基板１の平面図であり、図４（ｃ）はそのと
きの模式断面図である。In the above embodiment, the collector region (P + silicon substrate 1) of the IGBT is on the left side and the exposed surface 2a (recess) of the N + layer 2 is on the right side in the drawings for ease of explanation. However, in the actual manufacturing process, in order to prevent damage to the P + silicon substrate 1, as shown in FIG. 4, small holes 21 and grooves 22 are often combined as recesses. Further, it is necessary to increase the holes 21 and the grooves 22 in order to increase the current capacity, and the holes 21 and the grooves 22 need to be precisely machined. For example, ultrasonic machining, laser machining, electric discharge machining or the like is performed. Further, the electrodes can be easily formed in the plurality of holes 21 and the grooves 22 by the bump technique, the flip chip technique and the substrate wiring technique. Note that FIG.
(A) and (b) are P in which the hole 21 and the groove 22 were formed, respectively.
+ Is a plan view of a silicon substrate 1, FIG. 4 (c) is a schematic cross-sectional view at that time.
【００２２】また、上記実施例では、一導電型をＰ型と
し、他導電型をＮ型として説明したが、これに限られる
ものではない。In the above embodiment, one conductivity type is P type and the other conductivity type is N type. However, the present invention is not limited to this.
【００２３】[0023]
【発明の効果】この発明によれば、一導電型基板（コレ
クタ），第１の領域，第２の領域，第３の領域および第
４の領域（エミッタ）からなるＩＧＢＴと、露出面上の
第１の領域（ドレイン），第２の領域，第３の領域およ
び第４の領域（ソース）からなるＭＯＳＦＥＴとを有し
ている。その結果、この複合型半導体素子を電子機器に
用いることによって幅広い周波数に対応でき、部品点数
の削減、信頼性の向上など総合的な原価低減を実現でき
る。そして、ＭＯＳＦＥＴの寄生ダイオードをＩＧＢＴ
のコレクタ・エミッタ間に容易に設けることができ、モ
ータ駆動用として用いる際に、別のダイオードを外付け
する必要がない。According to the present invention, an IGBT composed of a substrate of one conductivity type (collector), a first region, a second region, a third region and a fourth region (emitter) and an exposed surface. And a MOSFET including a first region (drain), a second region, a third region, and a fourth region (source). As a result, a wide range of frequencies can be supported by using this composite type semiconductor device in electronic equipment, and the total cost reduction such as the reduction of the number of parts and the improvement of reliability can be realized. Then, the parasitic diode of the MOSFET is
It can be easily provided between the collector and the emitter, and when used for driving a motor, it is not necessary to attach another diode externally.
【図１】この発明の第１の実施例の複合型半導体素子の
模式断面図と等価回路図である。FIG. 1 is a schematic cross-sectional view and an equivalent circuit diagram of a composite semiconductor device according to a first embodiment of the present invention.
【図２】この発明の第２の実施例の複合型半導体素子の
模式断面図と等価回路図である。FIG. 2 is a schematic sectional view and an equivalent circuit diagram of a composite type semiconductor device according to a second embodiment of the present invention.
【図３】この発明の第３の実施例の複合型半導体素子の
模式断面図と等価回路図である。FIG. 3 is a schematic sectional view and an equivalent circuit diagram of a composite type semiconductor device according to a third embodiment of the present invention.
【図４】この発明の実施例における凹部の形成方法を説
明するための図である。FIG. 4 is a diagram for explaining a method of forming a recess in the embodiment of the present invention.
【図５】従来のＩＧＢＴの模式断面図と等価回路図であ
る。FIG. 5 is a schematic cross-sectional view and an equivalent circuit diagram of a conventional IGBT.
【図６】従来のＭＯＳＦＥＴの模式断面図と等価回路図
である。FIG. 6 is a schematic cross-sectional view and an equivalent circuit diagram of a conventional MOSFET.
１ Ｐ+ シリコン基板（一導電型基板） ２ Ｎ+ 層（第１の領域） ２ａ 露出面 ３ Ｎ- 層（第２の領域） ４ Ｐ+ 領域（第３の領域） ５ Ｎ+ 領域（第４の領域） ８ａ ゲート電極（第１の電極） ８ｂ エミッタ電極（第２の電極） ９ 電極用金属膜（共通電極） ９ａ 電極用金属膜（第４の電極） ９ｂ 電極用金属膜（第３の電極） １０ ダイオード ２１ 穴（凹部） ２２ 溝（凹部）1 P + silicon substrate (one conductivity type substrate) 2 N + layer (first region) 2a exposed surface 3 N − layer (second region) 4 P + region (third region) 5 N + region (first region) Region 4) 8a gate electrode (first electrode) 8b emitter electrode (second electrode) 9 metal film for electrodes (common electrode) 9a metal film for electrodes (fourth electrode) 9b metal film for electrodes (third) Electrode) 10 diode 21 hole (recess) 22 groove (recess)
Claims (4)
主面上に形成するとともに前記一導電型基板がわに露出
面を形成した高濃度他導電型の第１の領域と、この第１
の領域上に形成した低濃度他導電型の第２の領域と、こ
の第２の領域内の表面に形成した高濃度一導電型の第３
の領域と、この第３の領域内の表面に形成した高濃度他
導電型の第４の領域とを備え、 前記第３の領域の上部に第１の電極を設け、前記第３お
よび第４の領域上に第２の電極を設け、前記第１の領域
の露出面および前記一導電型基板に接続する共通電極を
設けた複合型半導体素子。1. A one-conductivity-type substrate, and a high-concentration other-conductivity-type first region formed on one main surface of the one-conductivity-type substrate and having an exposed surface of the one-conductivity-type substrate, This first
Second region of low-concentration other conductivity type formed on the region of No. 3 and high-concentration one conductivity type of third region formed on the surface in the second region.
And a fourth region of high-concentration other conductivity type formed on the surface in the third region, a first electrode is provided on the third region, and the third and fourth regions are provided. 2. A composite semiconductor device having a second electrode provided on the region, and a common electrode connected to the exposed surface of the first region and the one conductivity type substrate.
主面上に形成するとともに前記一導電型基板がわに露出
面を形成した高濃度他導電型の第１の領域と、この第１
の領域上に形成した低濃度他導電型の第２の領域と、こ
の第２の領域内の表面に形成した高濃度一導電型の第３
の領域と、この第３の領域内の表面に形成した高濃度他
導電型の第４の領域とを備え、 前記第３の領域の上部に第１の電極を設け、前記第３お
よび第４の領域上に第２の電極を設け、前記第１の領域
の露出面に接続する第３の電極を設け、前記一導電型基
板に接続する第４の電極を設けた複合型半導体素子。2. A one-conductivity-type substrate, and a first region of a high-concentration other-conductivity type formed on one main surface of the one-conductivity-type substrate and having an exposed surface of the one-conductivity-type substrate. This first
Second region of low-concentration other conductivity type formed on the region of No. 3 and high-concentration one conductivity type of third region formed on the surface in the second region.
And a fourth region of high-concentration other conductivity type formed on the surface in the third region, a first electrode is provided on the third region, and the third and fourth regions are provided. 2. A composite semiconductor device having a second electrode on the region, a third electrode connected to the exposed surface of the first region, and a fourth electrode connected to the one conductivity type substrate.
主面上に形成するとともに前記一導電型基板がわに露出
面を形成した高濃度他導電型の第１の領域と、この第１
の領域上に形成した低濃度他導電型の第２の領域と、こ
の第２の領域内の表面に複数形成した高濃度一導電型の
第３の領域と、この複数の第３の領域内の表面に形成し
た高濃度他導電型の第４の領域とを備え、 前記複数の第３の領域の上部に第１の電極を設け、前記
複数の第３および第４の領域上に第２の電極を設け、前
記第１の領域の露出面に接続する第３の電極を設け、前
記一導電型基板に接続する第４の電極を設けた複合型半
導体素子。3. A one-conductivity-type substrate, and a first region of a high-concentration other-conductivity type formed on one main surface of the one-conductivity-type substrate and having an exposed surface of the one-conductivity-type substrate. This first
A second region of low-concentration other conductivity type formed on the region, a plurality of high-concentration one-conductivity type regions formed on the surface in the second region, and a third region of the plurality of third regions A fourth region of high-concentration other conductivity type formed on the surface of the plurality of third regions, a first electrode provided on the plurality of third regions, and a second region formed on the plurality of third and fourth regions. And a third electrode connected to the exposed surface of the first region, and a fourth electrode connected to the one conductivity type substrate.
型の第１の領域を形成し、この第１の領域上に低濃度他
導電型の第２の領域を形成し、この第２の領域内の表面
に高濃度一導電型の第３の領域を形成し、この第３の領
域内の表面に高濃度他導電型の第４の領域を形成する工
程と、 前記一導電型基板の他主面から前記第１の領域に達する
まで部分的に除去して凹部を形成する工程と、 前記第３の領域の上部、前記第３および第４の領域上、
前記第１の領域の露出面、および前記一導電型基板の他
主面に、それぞれ電極を形成する工程とを含むことを特
徴とする複合型半導体素子の製造方法。4. A high-concentration other-conductivity type first region is formed on one main surface of a one-conductivity type substrate, and a low-concentration other-conductivity type second region is formed on the first region, Forming a high-concentration-one-conductivity-type third region on the surface in the second region and forming a high-concentration-other-conductivity-type fourth region on the surface in the third region; Forming a recess by partially removing from the other main surface of the conductivity type substrate until reaching the first region; and an upper part of the third region, on the third and fourth regions,
And a step of forming electrodes on the exposed surface of the first region and the other main surface of the one conductivity type substrate, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5301463A JPH07153951A (en) | 1993-12-01 | 1993-12-01 | Composite semiconductor element and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5301463A JPH07153951A (en) | 1993-12-01 | 1993-12-01 | Composite semiconductor element and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07153951A true JPH07153951A (en) | 1995-06-16 |
Family
ID=17897206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5301463A Pending JPH07153951A (en) | 1993-12-01 | 1993-12-01 | Composite semiconductor element and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07153951A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009094105A (en) * | 2007-10-03 | 2009-04-30 | Denso Corp | Semiconductor device, and manufacturing method thereof |
| US7759696B2 (en) | 2005-10-20 | 2010-07-20 | Panasonic Corporation | High-breakdown voltage semiconductor switching device and switched mode power supply apparatus using the same |
| WO2011129443A1 (en) * | 2010-04-15 | 2011-10-20 | 富士電機株式会社 | Semiconductor device |
| JP2013110373A (en) * | 2011-08-02 | 2013-06-06 | Rohm Co Ltd | Semiconductor device and manufacturing method of the same |
| JP2014143852A (en) * | 2013-01-24 | 2014-08-07 | Denso Corp | Overcurrent protection circuit |
-
1993
- 1993-12-01 JP JP5301463A patent/JPH07153951A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7759696B2 (en) | 2005-10-20 | 2010-07-20 | Panasonic Corporation | High-breakdown voltage semiconductor switching device and switched mode power supply apparatus using the same |
| JP2009094105A (en) * | 2007-10-03 | 2009-04-30 | Denso Corp | Semiconductor device, and manufacturing method thereof |
| US8786024B2 (en) | 2010-04-15 | 2014-07-22 | Yoshitaka Sugawara | Semiconductor device comprising bipolar and unipolar transistors including a concave and convex portion |
| CN102782845A (en) * | 2010-04-15 | 2012-11-14 | 菅原良孝 | Semiconductor device |
| JPWO2011129443A1 (en) * | 2010-04-15 | 2013-07-18 | 良孝 菅原 | Semiconductor device |
| WO2011129443A1 (en) * | 2010-04-15 | 2011-10-20 | 富士電機株式会社 | Semiconductor device |
| JP5638067B2 (en) * | 2010-04-15 | 2014-12-10 | 良孝 菅原 | Semiconductor device |
| JP2013110373A (en) * | 2011-08-02 | 2013-06-06 | Rohm Co Ltd | Semiconductor device and manufacturing method of the same |
| US9419117B2 (en) | 2011-08-02 | 2016-08-16 | Rohm Co., Ltd. | Semiconductor device, and manufacturing method for same |
| US9620588B2 (en) | 2011-08-02 | 2017-04-11 | Rohm Co., Ltd. | Semiconductor device |
| US10192865B2 (en) | 2011-08-02 | 2019-01-29 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device |
| US10461077B2 (en) | 2011-08-02 | 2019-10-29 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device |
| US10692861B2 (en) | 2011-08-02 | 2020-06-23 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device |
| JP2014143852A (en) * | 2013-01-24 | 2014-08-07 | Denso Corp | Overcurrent protection circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4948748A (en) | Manufacture of a substrate structure for a composite semiconductor device using wafer bonding and epitaxial refill | |
| JP3269475B2 (en) | Semiconductor device | |
| JP2635828B2 (en) | Semiconductor device | |
| WO2019085577A1 (en) | Insulated gate bipolar transistor device and manufacturing method therefor, and power electronic equipment | |
| JP3198959B2 (en) | High voltage integrated circuit | |
| JP2005064472A (en) | Semiconductor device | |
| JPH07153951A (en) | Composite semiconductor element and manufacture thereof | |
| US5969401A (en) | Silicon on insulator substrate with improved insulation patterns | |
| US5475243A (en) | Semiconductor device including an IGBT and a current-regenerative diode | |
| US5569952A (en) | Semiconductor device with a semiconductor element provided in a mesa structure | |
| JPH10270689A (en) | Semiconductor device | |
| JPH03129764A (en) | Semiconductor device | |
| JP3340177B2 (en) | Field-effect transistor | |
| JPH10200104A (en) | Voltage-driven semiconductor device and its manufacturing method | |
| JP3217552B2 (en) | Horizontal high voltage semiconductor device | |
| JP3952967B2 (en) | High voltage IC | |
| JPH0251279A (en) | Vertical field effect transistor | |
| JPS60154671A (en) | Semiconductor device | |
| JP2008091932A (en) | High voltage integrated circuit | |
| JPH05206485A (en) | Diode bridge device | |
| JPH09283747A (en) | Lateral field effect transistor | |
| JPH01290265A (en) | Mos type semiconductor device | |
| JPH02271672A (en) | Semiconductor device | |
| JPH0513768A (en) | Insulating gate type bipolar transistor | |
| KR0131369B1 (en) | Manufacturing method for power semiconductor device |