JPH07142754A - Manufacture of polycrystal silicon element - Google Patents
Manufacture of polycrystal silicon elementInfo
- Publication number
- JPH07142754A JPH07142754A JP5290517A JP29051793A JPH07142754A JP H07142754 A JPH07142754 A JP H07142754A JP 5290517 A JP5290517 A JP 5290517A JP 29051793 A JP29051793 A JP 29051793A JP H07142754 A JPH07142754 A JP H07142754A
- Authority
- JP
- Japan
- Prior art keywords
- fluorine
- substrate
- thin film
- polycrystalline silicon
- crystal grain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体工業における半
導体素子及びその製造方法に関するものであり、特に多
結晶シリコンを主材料とした半導体素子の製造方法に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in the semiconductor industry and a method for manufacturing the same, and more particularly to a method for manufacturing a semiconductor device mainly made of polycrystalline silicon.
【０００２】[0002]
【従来の技術】従来の多結晶シリコン半導体素子の製造
において、多結晶シリコン中に存在する結晶粒界に含ま
れる欠陥を補償するために、多結晶シリコンに水素を注
入、あるいは拡散させることによって導入させるという
方法があった。2. Description of the Related Art In manufacturing a conventional polycrystalline silicon semiconductor device, hydrogen is introduced into or diffused into polycrystalline silicon in order to compensate for defects contained in grain boundaries existing in the polycrystalline silicon. There was a way to let it.
【０００３】[0003]
【発明が解決しようとする課題】従来の技術で、多結晶
シリコンに水素を注入、あるいは拡散させるという方法
は、水素とシリコンとの結合エネルギーが３．１ｅＶと
小さく、約３００℃以上で脱離し始めるため、熱的に不
安定であるという課題があった。また、水素のみで結晶
粒界中の欠陥を補償する場合に、水素が多結晶シリコン
中を極めて速く拡散するため、多結晶シリコン基板ある
いは薄膜全体にわたる結晶粒界中の欠陥補償が可能であ
る反面、水素による欠陥の補償を行う効率が低く、結晶
粒界中の欠陥の量に対して数倍〜数十倍の量の水素を多
結晶シリコンに対して導入しなければならないという課
題があった。特に半導体接合を有する多結晶シリコン素
子の場合には、特性に大きな影響を及ぼす接合部及び空
乏層領域の様な、接合部周辺の限定された領域に存在す
る結晶粒界中の欠陥の補償が十分に行われず、良好な特
性を得ることが困難であるという課題があった。According to the conventional method of injecting or diffusing hydrogen into polycrystalline silicon, the binding energy between hydrogen and silicon is as small as 3.1 eV, and desorption occurs at about 300 ° C. or higher. To get started, there was the problem of being thermally unstable. Further, when the defects in the crystal grain boundaries are compensated only by hydrogen, the hydrogen diffuses very rapidly in the polycrystal silicon, so that it is possible to compensate the defects in the crystal grain boundaries over the polycrystal silicon substrate or the whole thin film. However, the efficiency of compensating for defects by hydrogen is low, and there is a problem that hydrogen of several times to several tens times the amount of defects in the grain boundaries must be introduced into polycrystalline silicon. . Particularly in the case of a polycrystalline silicon device having a semiconductor junction, it is possible to compensate for defects in grain boundaries existing in a limited region around the junction, such as the junction and depletion layer regions, which have a large effect on the characteristics. There was a problem that it was not performed sufficiently and it was difficult to obtain good characteristics.
【０００４】[0004]
【課題を解決するための手段】以上の課題を解決するた
めに本発明では、多結晶シリコンからなる基板あるいは
薄膜の何れか一方に弗素を導入させる、或いは多結晶シ
リコンからなる基板あるいは薄膜の何れか一方に弗素及
び水素を基板あるいは薄膜の何れかの中に導入させると
いう手段を用いる。In order to solve the above problems, according to the present invention, fluorine is introduced into either a substrate or a thin film made of polycrystalline silicon, or a substrate or a thin film made of polycrystalline silicon is used. On the other hand, a means of introducing fluorine and hydrogen into either the substrate or the thin film is used.
【０００５】[0005]
【作用】弗素とシリコンとの結合エネルギーが５．６ｅ
Ｖと水素よりも大きいことから、弗素を多結晶シリコン
基板あるいは薄膜に導入することにより、水素を用いる
場合よりも高い温度でも安定な、結晶粒界中の欠陥の補
償を行うことができる。[Function] The binding energy between fluorine and silicon is 5.6e.
Since it is larger than V and hydrogen, by introducing fluorine into the polycrystalline silicon substrate or thin film, it is possible to perform stable compensation of defects in crystal grain boundaries even at a higher temperature than when hydrogen is used.
【０００６】また弗素により、特性に大きな影響を及ぼ
す接合部周辺の限定された領域に存在する結晶粒界中の
欠陥の補償を行うことができる。[0006] Fluorine can also compensate for defects in the grain boundaries existing in a limited region around the junction, which greatly affects the characteristics.
【０００７】さらに弗素及び水素を、多結晶シリコン基
板あるいは薄膜中に導入させる場合には、特性に大きな
影響を及ぼす接合部及びその周辺に存在する結晶粒界中
の欠陥の補償を弗素で行うとともに、多結晶シリコン基
板あるいは薄膜の全体にわたる結晶粒界中の欠陥を水素
により補償することができる。Further, when fluorine and hydrogen are introduced into the polycrystalline silicon substrate or the thin film, the defects in the grain boundaries existing at and around the junction, which greatly affects the characteristics, are compensated by the fluorine. The defects in the grain boundaries throughout the polycrystalline silicon substrate or the thin film can be compensated by hydrogen.
【０００８】[0008]
【実施例】以下図面を用いて本発明の第１実施例につい
てさらに詳しく説明する。結晶粒界１を有する多結晶シ
リコン基板２の片側には、ドーパント元素を含んだドー
ピング層３をイオン注入，熱拡散等により予め形成す
る。このドーピング層は、例えば多結晶シリコン基板２
がｐ型の場合には、ＰＯＣｌ3などのＰを含んだガス雰
囲気中での熱拡散を行い、ｎ型のドーパントであるＰを
ドーピングすることによって形成する。これにより例え
ば図１−ａに示すように、多結晶シリコン基板２中に、
接合部４が形成される。The first embodiment of the present invention will be described in more detail with reference to the drawings. On one side of the polycrystalline silicon substrate 2 having the crystal grain boundaries 1, a doping layer 3 containing a dopant element is formed in advance by ion implantation, thermal diffusion or the like. This doping layer is, for example, a polycrystalline silicon substrate 2
Is p-type, it is formed by performing thermal diffusion in a gas atmosphere containing P such as POCl 3 to dope P, which is an n-type dopant. Thereby, for example, as shown in FIG. 1-a, in the polycrystalline silicon substrate 2,
The joint part 4 is formed.
【０００９】この後、例えば図１−ｂに示すように、多
結晶シリコン基板２に弗素イオン５を打ち込む。素子の
構造・種類によっては、多結晶シリコン基板ではなく、
石英基板等の別種の基板上に堆積し、ドーパント元素の
ドーピングによって接合を形成した多結晶シリコン薄膜
に対して弗素イオン５を打ち込んでも良い。Thereafter, as shown in FIG. 1B, for example, fluorine ions 5 are implanted into the polycrystalline silicon substrate 2. Depending on the structure and type of device, instead of a polycrystalline silicon substrate,
Fluorine ions 5 may be implanted into a polycrystalline silicon thin film, which is deposited on another type of substrate such as a quartz substrate and has a junction formed by doping with a dopant element.
【００１０】例えば５０ｋｅＶのＦ+イオンを、１ｃｍ2
当たりの照射量として１０13〜１０ 17個打ち込んだ場
合、例えば図１−ｃに示すように、深さ約１００ｎｍに
１０17〜１０21ｃｍ-3の弗素濃度のピークを持つ弗素注
入層６が形成される。For example, F of 50 keV+Ion is 1 cm2
10 as the irradiation dose13-10 17The place where you typed in
In the case of, for example, as shown in FIG.
1017-10twenty onecm-3Fluorine injection with peak fluorine concentration
The entry layer 6 is formed.
【００１１】この後に、熱処理を行い、多結晶シリコン
基板２中の接合部４及びその周辺にある結晶粒界１に弗
素を拡散させ、例えば図１−ｄに示すように、弗素によ
り欠陥を補償された結晶粒界７により、結晶粒界中の欠
陥を補償する。Thereafter, heat treatment is performed to diffuse fluorine into the junction 4 in the polycrystalline silicon substrate 2 and the crystal grain boundaries 1 in the periphery thereof, and for example, as shown in FIG. 1-d, defects are compensated by fluorine. The crystal grain boundaries 7 thus compensated for defects in the crystal grain boundaries.
【００１２】この熱処理によって、例えば図２に示すよ
うに、弗素が結晶粒から結晶粒界へ拡散・凝集し、結晶
粒内よりも結晶粒界での弗素の濃度が大きくなるととも
に、弗素が拡散した領域にある結晶粒界中の欠陥が弗素
により結晶粒界欠陥を補償されることを発明者らは見い
だした。ここで図２は、５０ｋｅＶのＦ+イオンを１０
15ｃｍ-2注入後、窒素雰囲気中で７００℃，３０分熱処
理を行った後の弗素の深さ方向の濃度分布であり、実線
が多結晶シリコン（結晶粒界あり），点線が結晶シリコ
ン（結晶粒界なし）中の弗素の分布である。By this heat treatment, for example, as shown in FIG. 2, fluorine diffuses and agglomerates from the crystal grain to the crystal grain boundary, the concentration of the fluorine at the crystal grain boundary becomes larger than that in the crystal grain, and the fluorine diffuses. The inventors have found that the defects in the grain boundary in the above region are compensated by the fluorine for the grain boundary defects. Here, FIG. 2 shows that 10 F + ions of 50 keV are used.
The concentration distribution of fluorine in the depth direction after heat treatment at 700 ° C. for 30 minutes in a nitrogen atmosphere after implantation of 15 cm −2 , the solid line is polycrystalline silicon (with grain boundaries), and the dotted line is crystalline silicon ( This is the distribution of fluorine in (without grain boundaries).
【００１３】なお、弗素注入後における熱処理の温度と
して５００℃以下では弗素の分布が変化せず、また１２
００℃以上では弗素が多結晶シリコン基板２の外に脱離
して多結晶シリコン中の弗素の濃度が極端に減少する。
従って熱処理の温度範囲としては、５００℃以上１２０
０℃以下が好ましく、その中でも６００℃以上９００℃
以下の温度範囲が弗素の分布及び量として好ましい。When the temperature of the heat treatment after the implantation of fluorine is 500 ° C. or less, the distribution of fluorine does not change.
At temperatures above 00 ° C., fluorine is desorbed to the outside of the polycrystalline silicon substrate 2 and the concentration of fluorine in the polycrystalline silicon is extremely reduced.
Therefore, the temperature range of the heat treatment is 500 ° C or higher and 120
0 ° C or lower is preferable, and above 600 ° C and 900 ° C
The following temperature range is preferable as the distribution and amount of fluorine.
【００１４】また、５０ｋｅＶのＦ+イオンを用いた場
合の弗素イオンの注入量は、イオン注入により生じる欠
陥が少なく、かつ結晶粒界の欠陥を補償する範囲とし
て、１０14〜１０16ｃｍ-2が好ましい。Further, when the F + ions of 50 keV are used, the implantation amount of fluorine ions is within a range of 10 14 to 10 16 cm -2 so that the number of defects caused by the ion implantation is small and the defects at the crystal grain boundaries are compensated. Is preferred.
【００１５】なお、イオン注入・熱処理後に、結晶粒界
以外の欠陥が注入層に形成・残留している場合には、欠
陥を含んだ注入層をエッチングして除去する。例えば図
２で示される様な弗素の導入では、表面から深さ１００
ｎｍ程度までの領域に弗素注入によって生じた欠陥が残
留していることから、１００ｎｍ程度エッチング除去す
ればよい。When defects other than crystal grain boundaries are formed and remain in the implantation layer after the ion implantation / heat treatment, the implantation layer containing the defects is etched and removed. For example, when fluorine is introduced as shown in FIG.
Since a defect caused by fluorine implantation remains in a region up to about nm, it may be removed by etching about 100 nm.
【００１６】ここで本実施例では、イオン注入と熱拡散
を用いた方法を示しているが、弗化珪素，弗化水素等の
弗素を含んだ気体の雰囲気中で熱処理することや、弗素
化非晶質シリコン等の弗素を含んだ薄膜を形成した後に
熱処理することによって、弗素を多結晶シリコン２中の
接合部４及びその周辺にある結晶粒界に導入させてもよ
い。これら場合でも熱処理の温度として、６００℃以上
９００℃以下の温度範囲が好ましい。In this embodiment, a method using ion implantation and thermal diffusion is shown. However, heat treatment in a gas atmosphere containing fluorine such as silicon fluoride or hydrogen fluoride, or fluorination is carried out. By forming a thin film containing fluorine such as amorphous silicon and then performing heat treatment, fluorine may be introduced into the junction 4 in the polycrystalline silicon 2 and the crystal grain boundaries around the junction 4. Even in these cases, the temperature range of the heat treatment is preferably 600 ° C. or higher and 900 ° C. or lower.
【００１７】弗素を含んだ気体の雰囲気中で熱処理する
場合に、高周波等を印加することによって気体を放電励
起させても良い。さらに、多結晶シリコン基板あるいは
薄膜の形成を、弗素を含んだ雰囲気中で行うことによっ
て、形成時から基板あるいは薄膜中に弗素を導入させて
もよい。When heat treatment is performed in a gas atmosphere containing fluorine, the gas may be excited by discharge by applying a high frequency wave or the like. Further, the polycrystalline silicon substrate or the thin film may be formed in an atmosphere containing fluorine to introduce fluorine into the substrate or the thin film from the time of formation.
【００１８】以上の様にして接合部４及びその周辺にあ
る結晶粒界中の欠陥を弗素によって補償することによ
り、接合特性の優れた多結晶シリコン素子を提供でき
る。また弗素を用いていることにより、熱的に安定な欠
陥の補償を行うことができる。As described above, by compensating the defects in the crystal grain boundaries at the junction 4 and the periphery thereof with fluorine, it is possible to provide a polycrystalline silicon element having excellent junction characteristics. Further, by using fluorine, it is possible to compensate for a thermally stable defect.
【００１９】次に、本発明の第２実施例についてさらに
詳しく説明する。まず、実施例１と同様に、例えば図３
−ａに示すように、接合部８を有する多結晶シリコン基
板９に、イオン注入装置等により弗素イオン１０を打ち
込んで弗素注入層１１を形成し、この後に、例えば図３
−ｂに示すように、熱処理により多結晶シリコン中の接
合部８及びその周辺にある結晶粒界１２に、弗素を導入
させて弗素により欠陥が補償された結晶粒界１３のよう
に、結晶粒界中の欠陥の補償を行う。Next, the second embodiment of the present invention will be described in more detail. First, as in the first embodiment, for example, FIG.
As shown in FIG. 3A, a fluorine ion 10 is implanted into the polycrystalline silicon substrate 9 having the joint portion 8 by an ion implantation device or the like to form a fluorine implantation layer 11. After that, for example, as shown in FIG.
As shown in FIG. 6B, crystal grains such as crystal grain boundaries 13 in which fluorine is introduced into the crystal grain boundaries 12 in and around the junction 8 in the polycrystalline silicon by heat treatment and defects are compensated by the fluorine are formed. Compensate for defects in the world.
【００２０】この熱処理の温度範囲としては、５００℃
以上１２００℃以下が好ましく、その中でも６００℃以
上９００℃以下の温度範囲が弗素の分布及び量として好
ましい。The temperature range of this heat treatment is 500 ° C.
Above 1200 ° C. is preferable, and among them, a temperature range of above 600 ° C. and below 900 ° C. is preferable as the distribution and amount of fluorine.
【００２１】また、Ｆ+イオン注入を用いた場合の弗素
イオンの注入量は、注入欠陥が少なく、かつ結晶粒界の
欠陥を補償する範囲として、１０13〜１０16ｃｍ-2が好
ましい。Further, when the F + ion implantation is used, the amount of fluorine ion implantation is preferably 10 13 to 10 16 cm -2 as a range in which the number of implantation defects is small and the defects of crystal grain boundaries are compensated.
【００２２】さらにイオン注入・熱処理後に、結晶粒界
以外の欠陥が注入層に形成・残留している場合には、欠
陥を含んだ注入層をエッチングして除去することを行
う。Further, after the ion implantation / heat treatment, when defects other than crystal grain boundaries are formed / remained in the implantation layer, the implantation layer containing the defects is removed by etching.
【００２３】なお、接合部８及びその周辺にある結晶粒
界に弗素を導入させる方法として、弗素を含んだ気体の
雰囲気中で熱処理する方法や、弗素を含んだ薄膜を形成
した後に熱処理する方法等を用いてもよい。その場合で
も熱処理の温度として、６００℃以上９００℃以下の温
度範囲が好ましい。As a method of introducing fluorine into the junction 8 and the crystal grain boundaries in the periphery thereof, a method of heat treatment in an atmosphere of a gas containing fluorine or a method of heat treatment after forming a thin film containing fluorine. Etc. may be used. Even in that case, the temperature range of 600 ° C. or more and 900 ° C. or less is preferable as the temperature of the heat treatment.
【００２４】以上の様にして弗素を接合部８及びその周
辺にある結晶粒界に導入した後に、例えば図３−ｃに示
すように、水素イオン１４を打ち込んで、水素導入層１
５を形成するとともに、基板全体にわたる結晶粒界中の
欠陥の補償を行う。After the fluorine is introduced into the junction 8 and the crystal grain boundaries around the junction 8 as described above, hydrogen ions 14 are implanted to the hydrogen introduction layer 1 as shown in FIG.
5 is formed and defects in crystal grain boundaries over the entire substrate are compensated.
【００２５】このときの水素注入の条件としては、３ｋ
ｅＶの水素イオンを用いた場合の注入量として１０17〜
１０18ｃｍ-2台、基板温度として２５０℃以上４００℃
以下とする。この温度範囲で水素は多結晶シリコン中を
速く拡散するため、多結晶シリコン基板あるいは薄膜の
全体にわたる結晶粒界中の欠陥補償がある程度行われ
る。The condition of hydrogen injection at this time is 3 k
The implantation amount when using hydrogen ions of eV is 10 17 to
10 18 cm -2 , substrate temperature of 250 ℃ or more 400 ℃
Below. In this temperature range, hydrogen rapidly diffuses in the polycrystalline silicon, so that the defect compensation in the crystal grain boundaries over the entire polycrystalline silicon substrate or the thin film is performed to some extent.
【００２６】ここで水素の導入では、完全に補償されな
い接合部８及びその周辺にある結晶粒界中の欠陥は、例
えば図３−ｂに示すように、予め弗素によって補償され
ているため、水素のみを導入する場合よりも効率よく、
特に接合部８及びその周辺にある結晶粒界中の欠陥が補
償される。Here, when hydrogen is introduced, the defects in the crystal grain boundaries at the junction 8 and its periphery that are not completely compensated are previously compensated by fluorine, as shown in FIG. More efficient than just deploying
In particular, defects in the grain boundaries at the junction 8 and its periphery are compensated.
【００２７】なお、注入時の温度範囲としては、２００
℃未満では水素が結晶粒界を拡散しないとともに結晶粒
界中の欠陥の補償が効率よく行えないこと、また水素は
５００℃を越えると脱離することから、２５０℃以上４
００℃以下が好ましい。The temperature range during injection is 200
When the temperature is lower than ℃, hydrogen does not diffuse through the crystal grain boundary and defects in the crystal grain boundary cannot be compensated efficiently, and when the temperature exceeds 500 ℃, hydrogen is desorbed.
It is preferably 00 ° C or lower.
【００２８】注入時の基板温度は、基板もしくは基板台
をヒーター等で加熱すること、あるいは注入するイオン
の電流密度を１ｍＡ／ｃｍ2程度とし基板に対する注入
と加熱を同時に行うこと等によって制御する。例えば３
ｋｅＶの水素イオン照射では、イオン電流密度を１ｍＡ
／ｃｍ2とすると、イオンの照射によって基板の温度は
３００℃程度に上昇するため、この注入条件では、ヒー
ター等による多結晶シリコン基板９の加熱の必要がな
い。本実施例では加熱しながら水素イオン注入を行うこ
とによって、結晶粒界に水素を導入しているが、水素，
弗化水素などの水素を含んだ気体の雰囲気中で熱処理す
ることや、プラズマＣＶＤ法で形成したシリコン窒化膜
等の、水素を含んだ薄膜を形成した後に熱処理すること
によって、水素を多結晶シリコン基板９の結晶粒界に導
入させる方法を用いてもよい。これら場合でも熱処理の
温度として、２５０℃以上５００℃以下の温度範囲が好
ましい。水素を含んだ気体の雰囲気中で熱処理する場合
に、高周波電力等を印加して気体を放電励起させても良
い。The substrate temperature at the time of implantation is controlled by heating the substrate or the substrate base with a heater or the like, or by setting the current density of the implanted ions to about 1 mA / cm 2 and simultaneously performing the implantation and the heating on the substrate. Eg 3
In the keV hydrogen ion irradiation, the ion current density is 1 mA.
/ When cm 2 to, to raise to about 300 ° C. The temperature of the substrate by the irradiation of ions, in this implantation condition, there is no need for heating of the polycrystalline silicon substrate 9 by the heater or the like. In this embodiment, hydrogen ions are implanted while heating to introduce hydrogen into the crystal grain boundaries.
By performing heat treatment in an atmosphere of a gas containing hydrogen such as hydrogen fluoride or by forming a thin film containing hydrogen such as a silicon nitride film formed by a plasma CVD method and then performing heat treatment, hydrogen is converted into polycrystalline silicon. You may use the method of introduce | transducing into the crystal grain boundary of the board | substrate 9. Even in these cases, the temperature range of the heat treatment is preferably 250 ° C. or higher and 500 ° C. or lower. When the heat treatment is performed in a gas atmosphere containing hydrogen, high-frequency power or the like may be applied to discharge-excite the gas.
【００２９】以上の様にして弗素及び水素を導入するこ
とで、結晶粒界中の欠陥を効率よく補償するとともに、
特に、例えば図３−ｄに示すように、接合部８及びその
周辺にある結晶粒界中の欠陥を十分に補償することによ
り、接合特性の極めて優れた多結晶シリコン素子を提供
できる。By introducing fluorine and hydrogen as described above, defects in crystal grain boundaries can be efficiently compensated, and
In particular, as shown in FIG. 3D, for example, by sufficiently compensating for defects in the crystal grain boundaries at the junction 8 and its periphery, it is possible to provide a polycrystalline silicon element having extremely excellent junction characteristics.
【００３０】なお、素子の構造・種類によって、石英基
板等の別種の基板上に形成した多結晶シリコン薄膜を用
いても、同様の効果を得ることができる。The same effect can be obtained by using a polycrystalline silicon thin film formed on another type of substrate such as a quartz substrate depending on the structure and type of the element.
【００３１】図４に従来技術及び本発明によって作製し
た多結晶シリコン素子の電流電圧特性を示す。図４に
は、ｐ型多結晶シリコン基板の片側にＰを気相から拡散
させて形成した多結晶シリコン素子（ｐｎダイオード）
に対して、処理を行わないもの（従来技術：点線），水
素の導入のみを行ったもの（従来技術：一点鎖線），本
発明により弗素及び水素の導入を行ったもの（本発明：
実線）について示している。FIG. 4 shows current-voltage characteristics of the polycrystalline silicon device manufactured by the conventional technique and the present invention. FIG. 4 shows a polycrystalline silicon element (pn diode) formed by diffusing P from the vapor phase on one side of a p-type polycrystalline silicon substrate.
On the other hand, no treatment (prior art: dotted line), only hydrogen introduced (prior art: one-dot chain line), and fluorine and hydrogen introduced by the present invention (present invention:
Solid line).
【００３２】図４から明らかな様に、本発明によって、
特に接合部及びその周辺にある結晶粒界中の欠陥が効率
よく補償されることにより、リーク電流の少ない接合特
性の優れたダイオードが形成されている。As is apparent from FIG. 4, according to the present invention,
In particular, by efficiently compensating for defects in the crystal grain boundaries at and around the junction, a diode with less leakage current and excellent junction characteristics is formed.
【００３３】[0033]
【発明の効果】本発明は、多結晶シリコンからなる基板
あるいは薄膜の何れか一方に弗素を導入する、または、
多結晶シリコンからなる基板あるいは薄膜の何れか一方
に弗素及び水素を基板あるいは薄膜の何れかの中に導入
させる製造法であるため、熱的に安定な結晶粒界中の欠
陥の補償や、結晶粒界中の欠陥の補償を効率よく行うこ
とができるとともに、素子の特性に大きな影響をもたら
す接合部及びその周辺の様な限定された領域にある結晶
粒界中の欠陥を補償することができることにより、特性
の優れた多結晶シリコン半導体素子を提供することがで
きる。The present invention introduces fluorine into either a substrate made of polycrystalline silicon or a thin film, or
Since this is a manufacturing method in which fluorine and hydrogen are introduced into either the substrate or the thin film made of polycrystalline silicon into either the substrate or the thin film, compensation for defects in thermally stable crystal grain boundaries, The defect in the grain boundary can be efficiently compensated, and the defect in the crystal grain boundary in a limited region such as the junction and its periphery, which greatly affects the characteristics of the device, can be compensated. As a result, a polycrystalline silicon semiconductor device having excellent characteristics can be provided.
【００３４】本発明によって、例えば多結晶シリコン太
陽電池においては、接合特性を改善することが可能とな
り、光電変換効率を上げることができるなど、効果は極
めて大きい。According to the present invention, for example, in a polycrystalline silicon solar cell, the junction characteristics can be improved and the photoelectric conversion efficiency can be increased, which is extremely effective.
【図１】ａは、本発明に係る半導体素子の製造方法に係
る１実施例の工程概略図で、ｎ型ド−パントを形成した
断面図 ｂは、本発明に係る半導体素子の製造方法に係る１実施
例の工程概略図で、弗素イオン照射工程図 ｃは、本発明に係る半導体素子の製造方法に係る１実施
例の工程概略図で、弗素注入層形成後の断面図 ｄは、本発明に係る半導体素子の製造方法に係る１実施
例の工程概略図で、熱処理終了後の断面図1A is a process schematic view of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 1B is a cross-sectional view showing an n-type dopant formed. FIG. 1B is a view showing a method for manufacturing a semiconductor device according to the present invention. FIG. 3 is a process schematic view of one embodiment of the present invention, and a fluorine ion irradiation process drawing c is a process schematic view of one embodiment of the method for manufacturing a semiconductor device according to the present invention. FIG. FIG. 3 is a process schematic view of a first embodiment of a method for manufacturing a semiconductor device according to the present invention, which is a cross-sectional view after heat treatment
【図２】本発明に係る半導体素子に係る１実施例及び、
単結晶シリコンにおける深さ方向の弗素濃度分布図FIG. 2 is a diagram illustrating one example of a semiconductor device according to the present invention,
Depth direction fluorine concentration distribution map in single crystal silicon
【図３】ａは、本発明に係る半導体素子の製造方法に係
る１実施例の工程概略図で、弗素イオン照射工程図 ｂは、本発明に係る半導体素子の製造方法に係る１実施
例の工程概略図で、熱処理で結晶粒界の欠陥を補償する
工程図 ｃは、本発明に係る半導体素子の製造方法に係る１実施
例の工程概略図で、水素イオン照射工程図 ｄは、本発明に係る半導体素子の製造方法に係る１実施
例の工程概略図で、多結晶シリコン素子の要部断面図FIG. 3A is a process schematic diagram of one embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 3B is a fluorine ion irradiation process diagram b) of one embodiment of a method for manufacturing a semiconductor device according to the present invention. In the process schematic diagram, a process diagram for compensating for crystal grain boundary defects by heat treatment is a process schematic diagram of one embodiment of a method for manufacturing a semiconductor device according to the present invention, and a hydrogen ion irradiation process diagram d is the present invention. FIG. 3 is a process schematic view of a first embodiment of a method for manufacturing a semiconductor device according to the present invention, which is a cross-sectional view of an essential part of a polycrystalline silicon device
【図４】本発明及び従来技術に係る半導体素子の電流−
電圧特性図FIG. 4 shows the current of a semiconductor device according to the present invention and the prior art;
Voltage characteristic diagram
１ 結晶粒界 ２ 多結晶シリコン基板 ３ ドーピング層 ４ 接合部 ５ 弗素を含んだイオン ６ 弗素注入層 ７ 弗素により補償された粒界 ８ 接合部 ９ 多結晶シリコン基板 １０ 弗素を含んだイオン １１ 弗素注入層 １２ 結晶粒界 １３ 弗素により補償された結晶粒界 １４ 水素を含んだイオン １５ 水素導入層 １６ 弗素及び水素により補償された結晶粒界 1 Crystal Grain Boundary 2 Polycrystalline Silicon Substrate 3 Doping Layer 4 Junction 5 Ion Containing Fluorine 6 Fluorine Injection Layer 7 Fluorine Compensated Grain Boundary 8 Junction 9 Polycrystalline Silicon Substrate 10 Fluorine Ion 11 Fluorine Implantation Layer 12 Crystal grain boundary 13 Crystal grain boundary compensated by fluorine 14 Ion containing hydrogen 15 Hydrogen introduction layer 16 Crystal grain boundary compensated by fluorine and hydrogen
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/265 Ａ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 21/265 A
Claims (10)
の少なくとも何れか一方に、弗素を導入させることを特
徴とする半導体素子の製造方法。1. A method of manufacturing a semiconductor device, wherein fluorine is introduced into at least one of a substrate and a thin film made of polycrystalline silicon.
の少なくとも何れか一方に、弗素及び水素を導入させる
ことを特徴とする半導体素子の製造方法。2. A method of manufacturing a semiconductor device, wherein fluorine and hydrogen are introduced into at least one of a substrate and a thin film made of polycrystalline silicon.
し、前記イオンの照射時或いは照射後の少なくとも何れ
か一方に、基板あるいは薄膜を５００℃以上１２００℃
以下の温度に加熱することを特徴とする、請求項１また
は２何れかに記載の半導体素子の製造方法。3. The introduction of fluorine is carried out by irradiating ions containing fluorine, and at least one of the substrate and the thin film is irradiated at a temperature of 500 ° C. or more and 1200 ° C. during or after irradiation of the ions.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed at the following temperature.
で、多結晶シリコンからなる基板あるいは薄膜を５００
℃以上１２００℃以下の温度に加熱することによろこと
を特徴とする、請求項１または２何れかに記載の半導体
素子の製造方法。4. Fluorine is introduced into a substrate or thin film made of polycrystalline silicon in a gas atmosphere containing fluorine by 500 times.
The method for producing a semiconductor element according to claim 1, wherein the heating is performed at a temperature of not less than ℃ and not more than 1200 ℃.
る基板あるいは薄膜の何れかの上に形成し、前記基板あ
るいは前記多結晶シリコンからなる薄膜の何れかを、５
００℃以上１２００℃以下の温度に加熱することを特徴
とする、請求項１または２何れかに記載の半導体素子の
製造方法。5. A thin film containing fluorine is formed on either a substrate or a thin film made of polycrystalline silicon, and either the substrate or the thin film made of polycrystalline silicon is
The method for manufacturing a semiconductor element according to claim 1, wherein the heating is performed at a temperature of 00 ° C. or more and 1200 ° C. or less.
板あるいは薄膜の少なくとも何れか一方を、弗素を含む
雰囲気中で形成することを特徴とする、請求項１または
２何れかに記載の半導体素子の製造方法。6. The semiconductor according to claim 1, wherein the introduction of fluorine forms at least one of a substrate and a thin film made of polycrystalline silicon in an atmosphere containing fluorine. Device manufacturing method.
板あるいは薄膜の少なくとも何れか一方に、水素を含む
イオンを照射し、前記イオンの照射時或いは照射後に、
基板あるいは薄膜を６００℃以下の温度に加熱すること
を特徴とする、請求項２記載の半導体素子の製造方法。7. The introduction of hydrogen comprises irradiating at least one of a substrate made of polycrystalline silicon and a thin film with ions containing hydrogen, and during or after the irradiation of the ions.
The method of manufacturing a semiconductor device according to claim 2, wherein the substrate or the thin film is heated to a temperature of 600 ° C. or lower.
で、多結晶シリコンからなる基板あるいは薄膜の何れか
を、６００℃以下の温度に加熱することを特徴とする、
請求項２記載の半導体素子の製造方法。8. Introduction of hydrogen heats either a substrate or a thin film made of polycrystalline silicon to a temperature of 600 ° C. or lower in a gas atmosphere containing hydrogen.
The method for manufacturing a semiconductor device according to claim 2.
基板あるいは薄膜の何れか一方の上に形成し、前記基板
あるいは薄膜を６００℃以下の温度に加熱することを特
徴とする、請求項２記載の半導体素子の製造方法。9. A thin film containing hydrogen is formed on one of a substrate and a thin film made of polycrystalline silicon, and the substrate or the thin film is heated to a temperature of 600 ° C. or lower. A method for manufacturing the semiconductor device described above.
程を含むことを特徴とする、請求項６または８何れかに
記載の半導体素子の製造方法。10. The method of manufacturing a semiconductor device according to claim 6, wherein the introduction of hydrogen includes a step of exciting a gas by electric discharge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5290517A JPH07142754A (en) | 1993-11-19 | 1993-11-19 | Manufacture of polycrystal silicon element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5290517A JPH07142754A (en) | 1993-11-19 | 1993-11-19 | Manufacture of polycrystal silicon element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07142754A true JPH07142754A (en) | 1995-06-02 |
Family
ID=17757054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5290517A Pending JPH07142754A (en) | 1993-11-19 | 1993-11-19 | Manufacture of polycrystal silicon element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07142754A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030016052A (en) * | 2001-08-20 | 2003-02-26 | 삼성전자주식회사 | Method for fabricating thin film transistor substrate |
| JP2012507871A (en) * | 2008-10-31 | 2012-03-29 | バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド | Improve dark current and reduce defects in image sensors and photovoltaic junctions |
-
1993
- 1993-11-19 JP JP5290517A patent/JPH07142754A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030016052A (en) * | 2001-08-20 | 2003-02-26 | 삼성전자주식회사 | Method for fabricating thin film transistor substrate |
| JP2012507871A (en) * | 2008-10-31 | 2012-03-29 | バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド | Improve dark current and reduce defects in image sensors and photovoltaic junctions |
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