JPH07106769A - Manufacture of multilayered substrate for mounting electronic component - Google Patents
Manufacture of multilayered substrate for mounting electronic componentInfo
- Publication number
- JPH07106769A JPH07106769A JP5277680A JP27768093A JPH07106769A JP H07106769 A JPH07106769 A JP H07106769A JP 5277680 A JP5277680 A JP 5277680A JP 27768093 A JP27768093 A JP 27768093A JP H07106769 A JPH07106769 A JP H07106769A
- Authority
- JP
- Japan
- Prior art keywords
- film
- plating film
- laminated body
- wiring pattern
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は，多段の電子部品搭載用
基板に関し，配線パターンの表面に無電解めっき法によ
りＮｉ／Ａｕめっき膜を施す，電子部品搭載用多層基板
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-stage electronic component mounting substrate, and more particularly to a method for manufacturing an electronic component mounting multilayer substrate in which a surface of a wiring pattern is coated with a Ni / Au plating film by an electroless plating method.
【０００２】[0002]
【従来技術】従来，電子部品搭載用基板としては，図２
９に示すごとく，複数の絶縁基板９１，９２，９３を積
層してなる積層体９を有すると共に，電子部品搭載部９
０の周囲にボンディングパッド５３を設けてなる電子部
品搭載用多層基板がある。また，上記電子部品搭載用多
層基板は，積層体９を貫通するスルーホール９９と，該
スルーホール９９のパッド５２，５４と，積層体９の表
裏両面に設けられた配線パターン５１，５５と，積層体
９の内部に設けられた配線パターン５６とを有してい
る。2. Description of the Related Art Conventionally, as a board for mounting electronic parts, there has been used a board shown in FIG.
As shown in FIG. 9, the electronic component mounting portion 9 has a laminated body 9 formed by laminating a plurality of insulating substrates 91, 92, 93.
There is a multilayer substrate for mounting electronic components in which a bonding pad 53 is provided around 0. The multilayer board for mounting electronic components has through holes 99 penetrating the laminated body 9, pads 52 and 54 of the through holes 99, and wiring patterns 51 and 55 provided on both front and back surfaces of the laminated body 9. The wiring pattern 56 is provided inside the laminated body 9.
【０００３】上記配線パターン５１，５５，５６，ボン
ディングパッド５３，及びパッド５２，５４は，銅箔１
１よりなる。上記配線パターン５１，５５，及びパッド
５２，５４の表面は銅めっき膜２１及びＮｉ／Ａｕめっ
き膜４１により被覆されている。ボンディングパッド５
３は，Ｎｉ／Ａｕめっき膜４１により被覆されている。
上記スルーホール９９の壁面は，銅めっき膜２１及びＮ
ｉ／Ａｕめっき膜４１により被覆されている。上記Ｎｉ
／Ａｕめっき膜４１は，その内部に形成された配線パタ
ーンの腐食を防止する。The wiring patterns 51, 55, 56, the bonding pad 53, and the pads 52, 54 are made of copper foil 1.
It consists of 1. The surfaces of the wiring patterns 51, 55 and the pads 52, 54 are covered with the copper plating film 21 and the Ni / Au plating film 41. Bonding pad 5
3 is covered with a Ni / Au plating film 41.
The wall surface of the through hole 99 has the copper plating film 21 and N
It is covered with the i / Au plating film 41. Ni above
The / Au plated film 41 prevents corrosion of the wiring pattern formed inside.
【０００４】上記電子部品搭載部９０は，絶縁基板９１
〜９３の搭載穴９１１，９２１，９３１よりなる。上記
絶縁基板９１〜９３は，エポキシ系又はアクリル系等の
ソルダーレジスト６及び接着材７により接着されてい
る。配線パターン５１，５５及びパッド５２，５４を除
く部分の積層体９の表面は，エポキシ系又はアクリル系
等のソルダーレジスト６により被覆されている。The electronic component mounting portion 90 has an insulating substrate 91.
To 93 mounting holes 911, 921, 931. The insulating substrates 91 to 93 are adhered by an epoxy-based or acrylic-based solder resist 6 and an adhesive material 7. The surface of the laminated body 9 except for the wiring patterns 51, 55 and the pads 52, 54 is covered with a solder resist 6 of epoxy type or acrylic type.
【０００５】次に，上記従来の電子部品搭載用多層基板
の製造方法について説明する。まず，図２０に示すごと
く，表裏両面に銅箔１１を貼着した絶縁基板９１，９
２，９３を準備し，銅箔１１の不要部を除去して配線パ
ターン５６を形成する。次いで，絶縁基板９３の裏側
面，絶縁基板９２の両面，及び絶縁基板９１の表側面を
エポキシ系又はアクリル系等のソルダーレジスト６によ
り被覆する。次いで，この絶縁基板９２には搭載穴９２
１を穿設する。絶縁基板９１には，その表側面にのみ開
口した搭載穴９１１を穿設する。また，絶縁基板９３に
は，その裏側面にのみ開口した凹部９３２を穿設する。Next, a method of manufacturing the above-mentioned conventional multilayer board for mounting electronic parts will be described. First, as shown in FIG. 20, insulating substrates 91 and 9 in which copper foils 11 are adhered on both front and back surfaces.
2, 93 are prepared, and unnecessary portions of the copper foil 11 are removed to form the wiring pattern 56. Next, the back surface of the insulating substrate 93, both surfaces of the insulating substrate 92, and the front surface of the insulating substrate 91 are covered with a solder resist 6 of epoxy type or acrylic type. Then, the mounting hole 92 is formed in the insulating substrate 92.
1 is drilled. The insulating substrate 91 is provided with a mounting hole 911 opened only on its front side surface. Further, the insulating substrate 93 is provided with a recess 932 which is opened only on the back side surface thereof.
【０００６】次に，図２１に示すごとく，接着層７を介
して上記絶縁基板９１〜９３を積層し，積層体９を得
る。次いで，該積層体９にスルーホール９９を穿設す
る。次いで，該スルーホール９９の壁面を含めて，積層
体９の全表面に，銅めっき膜２１を形成する。Next, as shown in FIG. 21, the insulating substrates 91 to 93 are laminated through the adhesive layer 7 to obtain a laminated body 9. Then, through holes 99 are formed in the laminated body 9. Next, the copper plating film 21 is formed on the entire surface of the laminated body 9 including the wall surface of the through hole 99.
【０００７】次に，図２２に示すごとく，積層体９の表
側面に，銅箔１１及び銅めっき膜２１の不要部分を除去
して，配線パターン５１及びパッド５２を形成する。次
に，図２３に示すごとく，積層体９の表側面にエポキシ
系又はアクリル系等のソルダーレジスト６を形成する。
次に，絶縁基板９３の凹部９３２の底部９３４を，その
周囲（点線部分）を切断することにより除去し，図２４
に示すごとく，上記凹部９３２と同位置に搭載穴９３１
を形成する。Next, as shown in FIG. 22, unnecessary portions of the copper foil 11 and the copper plating film 21 are removed on the front surface of the laminated body 9 to form wiring patterns 51 and pads 52. Next, as shown in FIG. 23, an epoxy-based or acrylic-based solder resist 6 is formed on the front surface of the laminate 9.
Next, the bottom portion 934 of the concave portion 932 of the insulating substrate 93 is removed by cutting the periphery (dotted line portion) thereof, as shown in FIG.
, The mounting hole 931 is provided at the same position as the concave portion 932.
To form.
【０００８】次に，図２５に示すごとく，積層体９の裏
側面のパターン未形成部に，耐Ｎｉ／Ａｕめっき用のド
ライフィルム３１を貼着する。次に，図２６に示すごと
く，積層体９の表側面に形成された配線パターン５１，
パッド５２，スルーホール９９の内壁，及び積層体９の
裏側面を，Ｎｉ／Ａｕめっき膜４１により被覆する。こ
のとき，上記ドライフィルム３１の表面には，Ｎｉ／Ａ
ｕめっき膜は形成されない。Next, as shown in FIG. 25, a dry film 31 for Ni / Au plating resistance is attached to the unpatterned portion of the back surface of the laminate 9. Next, as shown in FIG. 26, the wiring patterns 51, which are formed on the front surface of the laminate 9,
The pad 52, the inner wall of the through hole 99, and the back surface of the laminated body 9 are covered with the Ni / Au plating film 41. At this time, on the surface of the dry film 31, Ni / A
The u plating film is not formed.
【０００９】上記Ｎｉ／Ａｕめっき膜４１を形成するに
当たって，積層体９の表面に上記のパターンと接続する
リード部を形成する。そして，銅箔１１及び銅めっき膜
２１からなるパターンに，上記リード部を介して通電
し，その表面に電解めっき法により，Ｎｉ／Ａｕめっき
膜４１を形成させる。このとき，ドライフィルム３１を
被覆した部分の銅めっき膜２１の表面には，上記Ｎｉ／
Ａｕめっき膜４１は形成されない。In forming the Ni / Au plated film 41, a lead portion connected to the above pattern is formed on the surface of the laminate 9. Then, the pattern consisting of the copper foil 11 and the copper plating film 21 is energized through the lead portion, and the Ni / Au plating film 41 is formed on the surface thereof by the electrolytic plating method. At this time, on the surface of the copper plating film 21 covered with the dry film 31, the above Ni /
The Au plating film 41 is not formed.
【００１０】次に，図２７に示すごとく，上記ドライフ
ィルム３１を除去する。次に，図２８に示すごとく，銅
めっき膜２１におけるＮｉ／Ａｕめっき膜４１により覆
われていない部分を，エッチングにより除去する。次
に，図２９に示すごとく，積層体９の表面におけるパタ
ーンが形成されていない部分に，エポキシ系又はアクリ
ル系等のソルダーレジスト６を形成する。これにより，
上記電子部品搭載用多層基板が得られる。Next, as shown in FIG. 27, the dry film 31 is removed. Next, as shown in FIG. 28, the portion of the copper plating film 21 not covered with the Ni / Au plating film 41 is removed by etching. Next, as shown in FIG. 29, an epoxy-based or acrylic-based solder resist 6 is formed on the surface of the laminate 9 where the pattern is not formed. By this,
The above-mentioned multilayer board for mounting electronic components can be obtained.
【００１１】[0011]
【解決しようとする課題】しかしながら，上記電子部品
搭載用多層基板においては，図２９，図３０に示すごと
く，配線パターン５１，５５及びパッド５２，５４を構
成する銅箔１１及び銅めっき膜２１は，その最上表面は
Ｎｉ／Ａｕめっき膜４１によって被覆されているが，そ
の端部においては露出している。そのため，この銅層
が，腐食するおそれがある。However, in the above-mentioned electronic component mounting multilayer substrate, as shown in FIGS. 29 and 30, the copper foil 11 and the copper plating film 21 forming the wiring patterns 51 and 55 and the pads 52 and 54 are The uppermost surface thereof is covered with the Ni / Au plating film 41, but is exposed at the end portion. Therefore, this copper layer may be corroded.
【００１２】また，絶縁基板９１〜９３は，めっきリー
ドがとれない。そのため，上記Ｎｉ／Ａｕめっき膜４１
を形成するに当たって，パターンと接続するリード部を
形成する等，複雑な工程が必要となる。そのため，製造
工程が多くなり期間を要する。そして，いわゆるリード
タイムが長くなり，多大な費用がかかる。本発明はかか
る従来の問題点に鑑み，耐腐食性に優れたパターンを容
易に形成することができる，電子部品搭載用多層基板の
製造方法を提供しようとするものである。In addition, the insulating substrates 91 to 93 cannot take plating leads. Therefore, the Ni / Au plated film 41
In forming the wiring, a complicated process such as forming a lead portion connected to the pattern is required. Therefore, the number of manufacturing processes increases and it takes a long time. Then, the so-called lead time becomes long, and it costs a lot of money. In view of the above conventional problems, the present invention aims to provide a method of manufacturing a multilayer substrate for mounting electronic components, which can easily form a pattern having excellent corrosion resistance.
【００１３】[0013]
【課題の解決手段】本発明は，（ａ）複数の絶縁基板
に，配線パターンと電子部品搭載用の搭載穴とを形成
し，（ｂ）上記配線パターンの露出部表面に，無電解め
っき法により第１Ｎｉ／Ａｕめっき膜を施し，（ｃ）上
記複数の絶縁基板を積層し，積層体を得た後，（ｄ）該
積層体にスルーホールを穿設し，（ｅ）上記第１Ｎｉ／
Ａｕめっき膜の表面及び上記スルーホールの内壁を含め
た上記積層体の全表面に，銅めっき膜を形成し，（ｆ）
上記銅めっき膜における配線パターンを被覆していない
部分をエッチングにより除去し，（ｇ）上記第１Ｎｉ／
Ａｕめっき膜又は／及び銅めっき膜の露出表面に，無電
解めっき法により第２Ｎｉ／Ａｕめっき膜を施すことを
特徴とする電子部品搭載用多層基板の製造方法にある。According to the present invention, (a) a wiring pattern and a mounting hole for mounting an electronic component are formed on a plurality of insulating substrates, and (b) an electroless plating method is applied to an exposed surface of the wiring pattern. The first Ni / Au plating film is applied by (c) and the plurality of insulating substrates are laminated to obtain a laminated body, (d) through holes are formed in the laminated body, and (e) the first Ni / Au
Forming a copper plating film on the entire surface of the laminate including the surface of the Au plating film and the inner wall of the through hole; (f)
A portion of the copper plating film that does not cover the wiring pattern is removed by etching, and (g) the first Ni /
A method for manufacturing a multilayer substrate for mounting electronic components is characterized by applying a second Ni / Au plating film to the exposed surface of the Au plating film and / or the copper plating film by an electroless plating method.
【００１４】本発明において最も注目すべきことは，配
線パターン，及び該配線パターンを覆う銅めっき膜の全
表面を第２Ｎｉ／Ａｕめっき膜により被覆することであ
る。上記第１，及び第２Ｎｉ／Ａｕめっき膜は，無電解
めっき法により形成される。上記無電解めっき法は，積
層体をＮｉとＡｕとを含むめっき液に浸漬することによ
り，その表面に化学還元反応で金属を析出させる方法で
ある。上記めっき液には，Ｎｉ源として硫酸ニッケル
が，Ａｕ源としてシアン化金カリウムが，Ｎｉの還元剤
として次亜リン酸ナトリウムが溶解している。また，上
記Ｎｉ／Ａｕめっき膜は，Ｎｉめっき液に浸漬した後，
Ａｕめっき液に浸漬することによっても形成できる。What is most noticeable in the present invention is that the wiring pattern and the entire surface of the copper plating film covering the wiring pattern are covered with the second Ni / Au plating film. The first and second Ni / Au plated films are formed by an electroless plating method. The electroless plating method is a method in which a metal is deposited on the surface of the laminate by a chemical reduction reaction by immersing the laminate in a plating solution containing Ni and Au. In the plating solution, nickel sulfate as a Ni source, potassium cyanide potassium as an Au source, and sodium hypophosphite as a reducing agent for Ni are dissolved. The Ni / Au plating film is immersed in a Ni plating solution,
It can also be formed by immersing in an Au plating solution.
【００１５】上記銅めっき膜は，例えば，硫酸銅めっき
のようなプリント配線基板で使用されるめっきの方法に
より形成される。上記配線パターンは，銅，ニッケル，
金等の導電材より形成される。上記配線パターンとして
は，積層体の内部に位置する内層パターン，又は積層体
の外部に位置する外層パターンがある。The copper plating film is formed by a plating method used for a printed wiring board, such as copper sulfate plating. The wiring pattern is copper, nickel,
It is formed of a conductive material such as gold. The wiring pattern may be an inner layer pattern located inside the laminated body or an outer layer pattern located outside the laminated body.
【００１６】上記配線パターンの露出部とは，積層体を
構成したときに，該積層体の表面に位置する配線パター
ンの部位をいう。この露出部としては，例えば，上記搭
載穴の周縁に形成された内層パターンの延設部等があ
る。該延設部は，ボンディングパッド等である。上記第
１Ｎｉ／Ａｕめっき膜又は／及び銅めっき膜の露出表面
とは，積層体の表面に形成された配線パターンを覆う上
記第１Ｎｉ／Ａｕめっき膜又は／及び銅めっき膜をい
う。上記絶縁基板としては，ガラス・エポキシ基板，ガ
ラス・ポリイミド基板，ガラスビスマレイミドトリアジ
ン基板等を用いる。上記複数枚の絶縁基板は，プリプレ
グ等の接着材により接着され，積層体を形成する。The exposed portion of the wiring pattern means a portion of the wiring pattern located on the surface of the laminated body when the laminated body is formed. The exposed portion is, for example, an extended portion of the inner layer pattern formed on the peripheral edge of the mounting hole. The extended portion is a bonding pad or the like. The exposed surface of the first Ni / Au plated film or / and the copper plated film means the first Ni / Au plated film or / and the copper plated film which covers the wiring pattern formed on the surface of the laminate. A glass / epoxy substrate, a glass / polyimide substrate, a glass bismaleimide triazine substrate, or the like is used as the insulating substrate. The plurality of insulating substrates are bonded together with an adhesive material such as prepreg to form a laminated body.
【００１７】[0017]
【作用及び効果】本発明においては，配線パターン，及
び該配線パターンを覆う銅めっき膜の全表面を第２Ｎｉ
／Ａｕめっき膜により被覆している。そのため，配線パ
ターン及び銅めっき膜が外気と接触することがない。ま
た，Ｎｉ／Ａｕめっき膜は，耐腐食性に優れている。従
って，耐腐食性に優れた配線パターンを形成することが
できる。In the present invention, the wiring pattern and the entire surface of the copper plating film covering the wiring pattern are covered with the second Ni layer.
/ Au plating film. Therefore, the wiring pattern and the copper plating film do not come into contact with the outside air. Further, the Ni / Au plating film has excellent corrosion resistance. Therefore, a wiring pattern having excellent corrosion resistance can be formed.
【００１８】また，上記第１及び第２Ｎｉ／Ａｕめっき
膜は，ともに無電解めっき法により形成されるため，パ
ターンに電流を導くためのリード部を設ける必要がな
い。そのため，容易に配線パターンの表面にＮｉ／Ａｕ
めっき膜を形成することができる。本発明によれば，耐
腐食性に優れたパターンを容易に形成することができ
る，電子部品搭載用多層基板の製造方法を提供すること
ができる。Further, since the first and second Ni / Au plated films are both formed by the electroless plating method, it is not necessary to provide the lead portion for guiding the current to the pattern. Therefore, Ni / Au can be easily formed on the surface of the wiring pattern.
A plating film can be formed. According to the present invention, it is possible to provide a method of manufacturing a multilayer substrate for mounting electronic components, which allows a pattern having excellent corrosion resistance to be easily formed.
【００１９】[0019]
【実施例】実施例１ 本発明の実施例について，図１〜図７を用いて説明す
る。本例にかかる電子部品搭載用多層基板９７は，図１
に示すごとく，複数の絶縁基板９１，９２，９３を積層
した積層体９を有すると共に，電子部品搭載部９０の周
囲にボンディングパッド５３を設けてなる。EXAMPLE 1 An example of the present invention will be described with reference to FIGS. The electronic component mounting multilayer substrate 97 according to this example is shown in FIG.
As shown in FIG. 7, the laminated body 9 is formed by laminating a plurality of insulating substrates 91, 92, 93, and the bonding pad 53 is provided around the electronic component mounting portion 90.
【００２０】また，上記電子部品搭載用多層基板は，積
層体９を貫通するスルーホール９９と，該スルーホール
９９のパッド５２，５４と，配線パターン５１，５５，
５６とを有している。配線パターン５１，５５，パッド
５２，５４は，積層体９の表裏両面に設けられた外層パ
ターンである。配線パターン５６は，積層体９の内部に
設けられた内層パターンである。ボンディングパッド５
３は，内層パターンとしての配線パターン５６の延設部
である。Further, the above-mentioned multilayer substrate for mounting electronic parts has through holes 99 penetrating the laminated body 9, pads 52 and 54 of the through holes 99, wiring patterns 51 and 55,
56 and. The wiring patterns 51, 55 and the pads 52, 54 are outer layer patterns provided on both front and back surfaces of the laminated body 9. The wiring pattern 56 is an inner layer pattern provided inside the laminated body 9. Bonding pad 5
Reference numeral 3 denotes an extended portion of the wiring pattern 56 as an inner layer pattern.
【００２１】配線パターン５１，５５，５６，パッド５
２，５４，及びボンディングパッド５３は，銅箔１より
なる。上記配線パターン５１，５５，及びパッド５２，
５４は，銅めっき膜３及び第２Ｎｉ／Ａｕめっき膜４に
より被覆されている。ボンディングパッド５３は，，第
１及び第２Ｎｉ／Ａｕめっき膜２，４により被覆されて
いる。スルーホール９９の壁面は，銅めっき膜３及び第
２Ｎｉ／Ａｕめっき膜４により被覆されている。Wiring patterns 51, 55, 56 and pad 5
2, 54 and the bonding pad 53 are made of the copper foil 1. The wiring patterns 51, 55 and the pads 52,
54 is covered with the copper plating film 3 and the second Ni / Au plating film 4. The bonding pad 53 is covered with the first and second Ni / Au plating films 2 and 4. The wall surface of the through hole 99 is covered with the copper plating film 3 and the second Ni / Au plating film 4.
【００２２】上記電子部品搭載部９０は，絶縁基板９
１，９２，９３の搭載穴９１０，９２０，９３０よりな
る。搭載穴９１０は，凹形状で，上面側が開口してい
る。搭載穴９２０，９３０は，絶縁基板９２，９３を貫
通している。絶縁基板９１〜９３は，エポキシ系又はア
クリル系等のソルダーレジスト６及び接着材７により接
着されている。積層体９の表面は，エポキシ系又はアク
リル系等のソルダーレジスト６により被覆されている。The electronic component mounting portion 90 includes the insulating substrate 9
1, 92, 93 mounting holes 910, 920, 930. The mounting hole 910 has a concave shape and is open on the upper surface side. The mounting holes 920 and 930 penetrate the insulating substrates 92 and 93. The insulating substrates 91 to 93 are adhered by an epoxy-based or acrylic-based solder resist 6 and an adhesive material 7. The surface of the laminated body 9 is covered with a solder resist 6 of epoxy type or acrylic type.
【００２３】次に，上記電子部品搭載用多層基板の製造
方法について説明する。まず，図２に示すごとく，表裏
両面に銅箔１を貼着した絶縁基板９１，９２，９３を準
備する。次いで，銅箔１の不要部を除去して内層パター
ンとしての配線パターン５６を形成する。次いで，図
２，図３に示すごとく，配線パターンの延設部としての
ボンディングパッド５３の表面を，第１Ｎｉ／Ａｕめっ
き膜２により被覆する。次に，積層体の内部に位置する
絶縁基板９１〜９３の表面をエポキシ系又はアクリル系
等のソルダーレジスト６により被覆する。Next, a method for manufacturing the above-mentioned electronic component mounting multilayer substrate will be described. First, as shown in FIG. 2, insulating substrates 91, 92, 93 having copper foils 1 attached to both front and back surfaces are prepared. Then, unnecessary portions of the copper foil 1 are removed to form a wiring pattern 56 as an inner layer pattern. Next, as shown in FIGS. 2 and 3, the surface of the bonding pad 53 as the extended portion of the wiring pattern is covered with the first Ni / Au plating film 2. Next, the surfaces of the insulating substrates 91 to 93 located inside the laminated body are covered with an epoxy-based or acrylic-based solder resist 6.
【００２４】次に，絶縁基板９１〜９３に搭載穴９１０
〜９３０を穿設する。搭載穴９１０は，上側が開口した
凹形状にザグリ加工する。搭載穴９２０，９３０は，絶
縁基板９２，９３を貫通する貫通穴に穿設する。このと
き，搭載穴９２０は，搭載穴９３０よりも小さい口径と
する。Next, mounting holes 910 are formed in the insulating substrates 91-93.
Drill ~ 930. The mounting hole 910 is counterbored into a concave shape having an open upper side. The mounting holes 920 and 930 are formed in through holes that penetrate the insulating substrates 92 and 93. At this time, the mounting hole 920 has a smaller diameter than the mounting hole 930.
【００２５】次に，図４に示すごとく，接着層７を介し
て上記絶縁基板９１〜９３を積層し，積層体９を得る。
次いで，該積層体９にスルーホール９９を穿設する。次
に，図５に示すごとく，スルーホール９９の壁面を含め
て，積層体９の全表面を，銅めっき膜３により被覆す
る。次に，図６に示すごとく，銅箔１及び銅めっき膜３
の不要部分を除去して，積層体９の表裏両面に，配線パ
ターン５１，５５，及びパッド５２，５４を形成する。Next, as shown in FIG. 4, the insulating substrates 91 to 93 are laminated via the adhesive layer 7 to obtain a laminated body 9.
Then, through holes 99 are formed in the laminated body 9. Next, as shown in FIG. 5, the entire surface of the laminate 9 including the wall surface of the through hole 99 is covered with the copper plating film 3. Next, as shown in FIG. 6, the copper foil 1 and the copper plating film 3
The unnecessary portions of are removed to form wiring patterns 51, 55 and pads 52, 54 on both front and back surfaces of the laminated body 9.
【００２６】次に，図７に示すごとく，積層体９の表裏
両面にエポキシ系又はアクリル系等のソルダーレジスト
６を形成する。次に，上記第１Ｎｉ／Ａｕめっき膜２又
は銅めっき膜３の表面を第２Ｎｉ／Ａｕめっき膜４によ
り被覆する。これにより，図１に示した，上記電子部品
搭載用多層基板９７が得られる。Next, as shown in FIG. 7, an epoxy-based or acrylic-based solder resist 6 is formed on both front and back surfaces of the laminate 9. Next, the surface of the first Ni / Au plated film 2 or the copper plated film 3 is covered with the second Ni / Au plated film 4. As a result, the electronic component mounting multilayer substrate 97 shown in FIG. 1 is obtained.
【００２７】次に，本例の作用効果について説明する。
本例においては，図７に示すごとく，配線パターン５
１，５５，パッド５２，５４の銅箔１及び銅めっき膜
３，ボンディングパッド５３の銅箔１及び第１Ｎｉ／Ａ
ｕめっき膜２，並びにスルーホール９９の内壁を覆う銅
めっき膜３の全表面を，第２Ｎｉ／Ａｕめっき膜４によ
り被覆している。そのため，上記銅箔１，銅めっき膜３
が外気と接触することがない。また，第１及び第２Ｎｉ
／Ａｕめっき膜２，４は，耐腐食性に優れている。Next, the function and effect of this example will be described.
In this example, as shown in FIG.
1, 55, the copper foil 1 of the pads 52, 54 and the copper plating film 3, the copper foil 1 of the bonding pad 53 and the first Ni / A
The entire surface of the u-plated film 2 and the copper-plated film 3 covering the inner wall of the through hole 99 is covered with the second Ni / Au plated film 4. Therefore, the above copper foil 1, copper plating film 3
Does not come into contact with the outside air. Also, the first and second Ni
The / Au plated films 2 and 4 have excellent corrosion resistance.
【００２８】また，積層体９から露出するボンディング
パッド５３は，予め第１Ｎｉ／Ａｕめっき膜２により被
覆され，その後更にその表面が第２Ｎｉ／Ａｕめっき膜
４により被覆される。そのため，外気と接触しやすい上
記ボンディングパッド５３は，更に厚く上記Ｎｉ／Ａｕ
めっき膜２，４により被覆されることになる。従って，
耐腐食性に優れた配線パターンを形成することができ
る。また，上記Ｎｉ／Ａｕめっき膜２，４は，ともに無
電解めっき法により形成されるため，パターンに電流を
導くためのリード部を設ける必要がない。そのため，容
易に配線パターンの表面にＮｉ／Ａｕめっき膜を形成す
ることができる。The bonding pad 53 exposed from the laminated body 9 is coated with the first Ni / Au plating film 2 in advance, and then the surface thereof is further coated with the second Ni / Au plating film 4. Therefore, the bonding pad 53, which is easily contacted with the outside air, is thicker than the Ni / Au layer.
It will be covered with the plating films 2 and 4. Therefore,
A wiring pattern having excellent corrosion resistance can be formed. Further, since the Ni / Au plated films 2 and 4 are both formed by the electroless plating method, it is not necessary to provide a lead portion for guiding a current to the pattern. Therefore, the Ni / Au plating film can be easily formed on the surface of the wiring pattern.
【００２９】実施例２ 本例にかかる電子部品搭載用多層基板は，図８に示すご
とく，２枚の絶縁基板９４，９５を積層してなる積層体
９である。絶縁基板９４，９５の間には，内層パターン
としての配線パターン５６が形成されている。該配線パ
ターン５６の延設部には，ボンディングパッド５３が形
成されている。積層体９の外表面には，外層パターンと
しての配線パターン５１，５５及びパッド５２，５４が
形成されている。絶縁基板９４，９５には，搭載穴９４
０，９５０が穿設されており，前者は上面側にだけ開口
しており，後者は絶縁基板９５を貫通している。Example 2 The electronic component mounting multilayer substrate according to this example is a laminated body 9 in which two insulating substrates 94 and 95 are laminated as shown in FIG. A wiring pattern 56 as an inner layer pattern is formed between the insulating substrates 94 and 95. A bonding pad 53 is formed on the extended portion of the wiring pattern 56. On the outer surface of the laminated body 9, wiring patterns 51 and 55 and pads 52 and 54 as outer layer patterns are formed. Mounting holes 94 are provided in the insulating substrates 94 and 95.
0 and 950 are provided, the former is opened only on the upper surface side, and the latter penetrates the insulating substrate 95.
【００３０】次に，上記電子部品搭載用多層基板９７の
製造方法について説明する。まず，図９に示すごとく，
絶縁基板９４，９５に，内層パターンとしての配線パタ
ーン５６及びボンディングパッド５３を形成する。次い
で，内層パターンの延設部としてのボンディングパッド
５３の表面を，第１Ｎｉ／Ａｕめっき膜２により被覆す
る。次に，積層体の内部に位置する絶縁基板９４，９５
の表面をエポキシ系又はアクリル系等のソルダーレジス
ト６により被覆する。Next, a method of manufacturing the above-mentioned electronic component mounting multilayer substrate 97 will be described. First, as shown in FIG.
A wiring pattern 56 as an inner layer pattern and a bonding pad 53 are formed on the insulating substrates 94 and 95. Next, the surface of the bonding pad 53 as the extended portion of the inner layer pattern is covered with the first Ni / Au plating film 2. Next, the insulating substrates 94 and 95 located inside the laminated body
The surface of is coated with a solder resist 6 of epoxy type or acrylic type.
【００３１】次に，絶縁基板９４，９５に搭載穴９４０
及び凹部９５１を穿設する。搭載穴９４０は上側が開口
した凹形状に，凹部９５１は下側が開口した凹形状とす
る。上記凹部９５１の上側には蓋部９５２が設けられて
いる。このとき，搭載穴９４０は，凹部９５１よりも小
さい口径とする。Next, mounting holes 940 are formed in the insulating substrates 94 and 95.
And a recess 951 is formed. The mounting hole 940 has a concave shape with the upper side opened, and the concave section 951 has a concave shape with the lower side opened. A lid 952 is provided on the upper side of the recess 951. At this time, the mounting hole 940 has a smaller diameter than the recess 951.
【００３２】次に，図１０に示すごとく，接着層７を介
して上記絶縁基板９４，９５を積層し，積層体９を得
る。次いで，該積層体９にスルーホール９９を穿設す
る。次いで，図１１に示すごとく，スルーホール９９の
壁面を含めた，積層体９の全表面を，銅めっき膜３によ
り被覆する。Next, as shown in FIG. 10, the insulating substrates 94 and 95 are laminated via the adhesive layer 7 to obtain a laminated body 9. Then, through holes 99 are formed in the laminated body 9. Next, as shown in FIG. 11, the entire surface of the laminate 9 including the wall surfaces of the through holes 99 is covered with the copper plating film 3.
【００３３】次に，積層体９の表面に配線パターンと同
形状のパターンフィルムを載置し，この状態で積層体９
をエッチング溶液中に浸漬する。これにより，図１２に
示すごとく，銅箔１及び銅めっき膜３の不要部分を除去
して，積層体９の表裏両面に，配線パターン５１，５５
及びパッド５２，５４を形成する。次いで，積層体９の
表裏両面にエポキシ系又はアクリル系等のソルダーレジ
スト６を形成する。Next, a pattern film having the same shape as the wiring pattern is placed on the surface of the laminated body 9 and, in this state, the laminated body 9 is formed.
Is immersed in the etching solution. As a result, as shown in FIG. 12, unnecessary portions of the copper foil 1 and the copper plating film 3 are removed, and the wiring patterns 51, 55 are formed on both front and back surfaces of the laminate 9.
And pads 52 and 54 are formed. Next, the epoxy-based or acrylic-based solder resist 6 is formed on both front and back surfaces of the laminate 9.
【００３４】次に，図１３に示すごとく，上記積層体９
を無電解溶液中に浸漬し，銅めっき膜３の表面が第２Ｎ
ｉ／Ａｕめっき膜４により被覆される。このとき，上記
エポキシ系又はアクリル系等のソルダーレジスト６の表
面には，第２Ｎｉ／Ａｕめっき膜４が形成されない。こ
れは，銅系の材質にのみ付着するパラジウム系の触媒を
使用した無電解めっき法により，上記第２Ｎｉ／Ａｕめ
っき膜４を形成しているためである。Next, as shown in FIG.
Is immersed in an electroless solution, and the surface of the copper plating film 3 is the second N
It is covered with the i / Au plating film 4. At this time, the second Ni / Au plated film 4 is not formed on the surface of the epoxy-based or acrylic-based solder resist 6. This is because the second Ni / Au plating film 4 is formed by an electroless plating method using a palladium catalyst that adheres only to copper materials.
【００３５】次に，絶縁基板９５の凹部９５１の底部９
５２を，その周囲（点線部分）を切断することにより除
去し，図８に示すごとく，上記凹部９５１と同位置に搭
載穴９５０を形成する。これにより，図８に示す電子部
品搭載用多層基板９７が得られる。Next, the bottom 9 of the recess 951 of the insulating substrate 95
52 is removed by cutting the periphery (dotted line portion), and a mounting hole 950 is formed at the same position as the recess 951 as shown in FIG. As a result, the electronic component mounting multilayer substrate 97 shown in FIG. 8 is obtained.
【００３６】本例においては，図１１〜図１３に示すご
とく，積層体９の表面に配線パターン５１，５５及びパ
ッド５２，５４を形成し，その表面を第２Ｎｉ／Ａｕめ
っき膜４により被覆するとき，電子部品搭載部９０の内
部がエッチング液や無電解溶液と接触しない。そのた
め，上記電子部品搭載部９０の内部に形成されているボ
ンディングパッド５３に損傷を与えることなく，本例の
電子部品搭載用多層基板を作製することができる。In this example, as shown in FIGS. 11 to 13, wiring patterns 51, 55 and pads 52, 54 are formed on the surface of the laminate 9, and the surfaces are covered with the second Ni / Au plating film 4. At this time, the inside of the electronic component mounting portion 90 does not come into contact with the etching solution or the electroless solution. Therefore, the multilayer board for mounting electronic components of this example can be manufactured without damaging the bonding pads 53 formed inside the electronic component mounting portion 90.
【００３７】また，図１１に示すごとく，積層体９の表
面に銅めっき膜３を施す際に，電子部品搭載部９０内に
は銅めっき膜３が形成されない。そのため，電子部品搭
載部９０内の銅めっき膜３をエッチング処理により除去
する手間を省略することができる。その他は，実施例１
と同様の効果を得ることができる。Further, as shown in FIG. 11, when the copper plating film 3 is applied to the surface of the laminate 9, the copper plating film 3 is not formed in the electronic component mounting portion 90. Therefore, the labor of removing the copper plating film 3 in the electronic component mounting portion 90 by the etching process can be omitted. Others are Example 1
The same effect as can be obtained.
【００３８】実施例３ 本例においては，図１４に示すごとく，電子部品搭載部
９０をマスクフィルム９５３により覆った状態で，積層
体９の表面に銅めっき膜３を施し（図１１参照），次い
でエッチング処理により積層体９の表面に配線パターン
５１，５５及びパッド５２，５４を形成し（図１２参
照），更に続いて銅めっき膜３の表面に無電解めっき法
により，第２Ｎｉ／Ａｕめっき膜４を形成している（図
１３参照）。Embodiment 3 In this embodiment, as shown in FIG. 14, the copper plating film 3 is applied to the surface of the laminate 9 with the electronic component mounting portion 90 covered with the mask film 953 (see FIG. 11). Next, wiring patterns 51, 55 and pads 52, 54 are formed on the surface of the laminate 9 by an etching process (see FIG. 12), and then the surface of the copper plating film 3 is electroless plated to form a second Ni / Au plate. The film 4 is formed (see FIG. 13).
【００３９】上記絶縁基板９５には，予め該絶縁基板９
５を貫通する搭載穴９５０を穿設しておく。上記マスク
フィルム９５３は，搭載穴９５０の口径よりもわずかに
大きい形状をしている。また，マスクフィルム９５３
は，銅めっき膜形成用めっき液，銅めっき膜用エッチン
グ溶液，及びＮｉ／Ａｕめっき膜形成用の無電解溶液に
対し，耐性のあるものである。The insulating substrate 95 is formed in advance on the insulating substrate 9
A mounting hole 950 that penetrates 5 is formed in advance. The mask film 953 has a shape slightly larger than the diameter of the mounting hole 950. Also, the mask film 953
Is resistant to a plating solution for forming a copper plating film, an etching solution for forming a copper plating film, and an electroless solution for forming a Ni / Au plating film.
【００４０】尚，マスクフィルム９５３として，銅めっ
き膜形成用めっき液，銅めっき膜用エッチング溶液にの
み耐性があり，Ｎｉ／Ａｕめっき膜形成用の無電解溶液
に対しては耐性のない材質を用いた場合には，積層体９
を無電解溶液に浸漬する前に，Ｎｉ／Ａｕめっき膜形成
用の無電解溶液に耐性のある材質で形成され，かつ上記
マスクフィルム９５３と同形状のマスクフィルムと取り
替えればよい。その他は実施例２と同様である。本例に
おいても実施例２と同様の効果を得ることができる。As the mask film 953, a material having resistance only to a plating solution for forming a copper plating film and an etching solution for forming a copper plating film and not having resistance to an electroless solution for forming a Ni / Au plating film is used. When used, the laminate 9
Before being immersed in the electroless solution, the mask film formed of a material resistant to the electroless solution for forming the Ni / Au plating film and having the same shape as the mask film 953 may be replaced. Others are the same as those in the second embodiment. Also in this example, the same effect as in Example 2 can be obtained.
【００４１】実施例４ 本例にかかる電子部品搭載用多層基板は，図１５に示す
ごとく，パッド５２，５４は銅箔１により形成されてお
り，該銅箔１は第１Ｎｉ／Ａｕめっき膜２，銅めっき膜
３，及び第２Ｎｉ／Ａｕめっき膜４により被覆されてい
る。また，配線パターン５１，５５は，第１及び第２Ｎ
ｉ／Ａｕめっき膜２，４により被覆されている。積層体
９は，２枚の絶縁基板９４，９５を積層し，接着したも
のである。また，電子部品搭載部９０は，絶縁基板９５
に設けられた搭載穴９５０よりなる。その他の構成は，
実施例１の電子部品搭載用多層基板と同様である。Example 4 As shown in FIG. 15, in the multilayer substrate for mounting electronic components according to this example, the pads 52 and 54 are formed of the copper foil 1, and the copper foil 1 is formed by the first Ni / Au plated film 2 , The copper plating film 3, and the second Ni / Au plating film 4. In addition, the wiring patterns 51 and 55 include the first and second N
It is covered with i / Au plating films 2 and 4. The laminated body 9 is formed by laminating two insulating substrates 94 and 95 and adhering them. In addition, the electronic component mounting portion 90 has an insulating substrate 95.
The mounting hole 950 provided in the. Other configurations are
This is the same as the electronic component mounting multilayer substrate of the first embodiment.
【００４２】次に，上記電子部品搭載用多層基板の製造
方法について説明する。まず，図１６に示すごとく，絶
縁基板９４，９５に，内層パターンとしての配線パター
ン５６及びボンディングパッド５３と，外層パターンと
しての配線パターン５１，５５及びパッド５２，５４を
形成する。次いで，ボンディングパッド５３，配線パタ
ーン５１，５５，及びパッド５２，５４の表面を，第１
Ｎｉ／Ａｕめっき膜２により被覆する。次に，積層体９
の内部に位置する絶縁基板９４，９５の表面をエポキシ
系又はアクリル系等のソルダーレジスト６により被覆す
る。次に，上記絶縁基板９５に搭載穴９５０を穿設す
る。搭載穴９５０は絶縁基板９５を貫通する貫通穴とす
る。Next, a method of manufacturing the above-mentioned electronic component mounting multilayer substrate will be described. First, as shown in FIG. 16, wiring patterns 56 and bonding pads 53 as inner layer patterns and wiring patterns 51 and 55 and pads 52 and 54 as outer layer patterns are formed on insulating substrates 94 and 95. Next, the surfaces of the bonding pad 53, the wiring patterns 51 and 55, and the pads 52 and 54 are
It is covered with the Ni / Au plating film 2. Next, the laminated body 9
The surfaces of the insulating substrates 94 and 95 located inside the substrate are covered with an epoxy-based or acrylic-based solder resist 6. Next, a mounting hole 950 is formed in the insulating substrate 95. The mounting hole 950 is a through hole penetrating the insulating substrate 95.
【００４３】次に，図１７に示すごとく，接着層７を介
して上記絶縁基板９４，９５を積層し，積層体９を得
る。次に，図１８に示すごとく，該積層体９にスルーホ
ール９９を穿設し，次いで，スルーホール９９の壁面を
含む積層体９の全表面を，銅めっき膜３により被覆す
る。Next, as shown in FIG. 17, the insulating substrates 94 and 95 are laminated via the adhesive layer 7 to obtain a laminated body 9. Next, as shown in FIG. 18, through holes 99 are formed in the laminated body 9, and then the entire surface of the laminated body 9 including the wall surfaces of the through holes 99 is covered with the copper plating film 3.
【００４４】次に，図１９に示すごとく，配線パター
ン，スルーホールの内壁，パッド，及びバイアホールの
表面を被覆する銅めっき膜３だけを残し，その他の部分
の銅めっき膜３をエッチングにより除去する。上記エッ
チングは，上記のパターンと同一形状のパターンが形成
されているマスクフィルムを積層体９の表裏両面に載置
し，この状態で，積層体９をエッチング液の中に浸漬す
ることにより行う。エッチング後は，上記マスクフィル
ムは取り除かれる。Next, as shown in FIG. 19, only the copper plating film 3 covering the wiring pattern, the inner wall of the through hole, the pad, and the surface of the via hole is left, and the other parts of the copper plating film 3 are removed by etching. To do. The etching is performed by placing a mask film on which a pattern having the same shape as the above pattern is formed on both front and back surfaces of the laminated body 9 and immersing the laminated body 9 in an etching solution in this state. After etching, the mask film is removed.
【００４５】その後，上記実施例１の図７と同様の方法
により，積層体９の表面にエポキシ系又はアクリル系等
のソルダーレジスト６を形成し，次いで，上記銅めっき
膜３の表面を第２Ｎｉ／Ａｕめっき膜４により被覆す
る。これにより，上記図１５に示した電子部品搭載用多
層基板９７が得られる。Then, a solder resist 6 of epoxy type or acrylic type is formed on the surface of the laminate 9 by the same method as that of FIG. 7 of the first embodiment, and then the surface of the copper plating film 3 is covered with the second Ni. / Au plating film 4. As a result, the electronic component mounting multilayer substrate 97 shown in FIG. 15 is obtained.
【００４６】本例においては，絶縁基板９４，９５を積
層する前に，外層パターンとしての配線パターン及びパ
ッドを形成している。そのため，これらのパターンの表
面は，第１及び第２Ｎｉ／Ａｕめっき膜２，４により更
に厚く被覆されることとなる。従って，耐腐食性に優れ
た外層パターンを形成することができる。その他は，上
記実施例１と同様の効果を得ることができる。In this example, a wiring pattern and a pad as an outer layer pattern are formed before the insulating substrates 94 and 95 are laminated. Therefore, the surfaces of these patterns are covered with the first and second Ni / Au plating films 2 and 4 to be thicker. Therefore, the outer layer pattern having excellent corrosion resistance can be formed. Other than that, it is possible to obtain the same effects as in the first embodiment.
【図１】実施例１の電子部品搭載用多層基板の断面図。FIG. 1 is a cross-sectional view of a multilayer substrate for mounting electronic components according to a first embodiment.
【図２】実施例１における，積層前の，絶縁基板の断面
図。FIG. 2 is a cross-sectional view of an insulating substrate before stacking according to the first embodiment.
【図３】実施例１における，ボンディングパッド付近の
絶縁基板の拡大断面図。FIG. 3 is an enlarged cross-sectional view of an insulating substrate near a bonding pad according to the first embodiment.
【図４】実施例１における，絶縁基板を積層し，スルー
ホールを穿設した積層体の断面図。FIG. 4 is a cross-sectional view of a laminated body in which insulating substrates are laminated and through holes are formed in Example 1;
【図５】実施例１における，積層体の表面に銅めっき膜
を施した積層体の断面図。FIG. 5 is a cross-sectional view of a laminated body in which a copper plating film is applied to the surface of the laminated body in Example 1.
【図６】実施例１における，配線パターン及びパッドを
形成した積層体の断面図。FIG. 6 is a cross-sectional view of a laminated body in which a wiring pattern and pads are formed in Example 1.
【図７】実施例１における，エポキシ系又はアクリル系
等のソルダーレジストを施した積層体の断面図。FIG. 7 is a cross-sectional view of a laminate on which an epoxy-based or acrylic-based solder resist is applied in Example 1.
【図８】実施例２の電子部品搭載用多層基板の断面図。FIG. 8 is a cross-sectional view of a multilayer board for mounting electronic components according to a second embodiment.
【図９】実施例２における，積層前の，絶縁基板の断面
図。FIG. 9 is a cross-sectional view of an insulating substrate before being laminated in Example 2.
【図１０】実施例２における，スルーホールが穿設され
た積層体の断面図。FIG. 10 is a cross-sectional view of a laminated body in which through holes are formed in Example 2.
【図１１】実施例２における，銅めっき膜が形成された
積層体の断面図。FIG. 11 is a cross-sectional view of a laminated body in which a copper plating film is formed in Example 2.
【図１２】実施例２における，配線パターン及びエポキ
シ系又はアクリル系等のソルダーレジストを形成した積
層体の断面図。FIG. 12 is a cross-sectional view of a laminated body in which a wiring pattern and an epoxy-based or acrylic-based solder resist are formed in Example 2.
【図１３】実施例２における，第２Ｎｉ／Ａｕめっき膜
を形成した積層体の断面図。FIG. 13 is a cross-sectional view of a layered body on which a second Ni / Au plated film is formed in Example 2.
【図１４】実施例３における，電子部品搭載部がマスク
フィルムにより覆われた積層体の断面図。FIG. 14 is a cross-sectional view of a laminate in which an electronic component mounting portion is covered with a mask film in Example 3.
【図１５】実施例４の電子部品搭載用多層基板の断面
図。FIG. 15 is a cross-sectional view of a multilayer substrate for mounting electronic components according to a fourth embodiment.
【図１６】実施例４における，積層前の，絶縁基板の断
面図。FIG. 16 is a cross-sectional view of an insulating substrate before being laminated in Example 4.
【図１７】実施例４における，絶縁基板を積層した積層
体の断面図。FIG. 17 is a sectional view of a laminated body in which insulating substrates are laminated in Example 4.
【図１８】実施例４における，積層体の表面に銅めっき
膜を施した積層体の断面図。FIG. 18 is a cross-sectional view of a laminate in which a copper plating film is applied to the surface of the laminate in Example 4.
【図１９】実施例４における，エッチング後の積層体の
断面図。FIG. 19 is a cross-sectional view of a laminated body after being etched in Example 4.
【図２０】従来例における，積層前の絶縁基板の断面
図。FIG. 20 is a cross-sectional view of an insulating substrate before lamination in a conventional example.
【図２１】従来例における，スルーホールを穿設し，銅
めっき膜を施した積層体の断面図。FIG. 21 is a cross-sectional view of a laminate in which a through hole is formed and a copper plating film is applied in a conventional example.
【図２２】従来例における，配線パターン及びパッドを
形成した積層体の断面図。FIG. 22 is a cross-sectional view of a laminated body in which a wiring pattern and pads are formed in a conventional example.
【図２３】従来例における，エポキシ系又はアクリル系
等のソルダーレジストを施した積層体の断面図。FIG. 23 is a cross-sectional view of a laminated body to which a solder resist of epoxy type or acrylic type is applied in the conventional example.
【図２４】従来例における，底部を除去した積層体の断
面図。FIG. 24 is a cross-sectional view of a laminated body with a bottom removed in a conventional example.
【図２５】従来例における，ドライフィルムを施した積
層体の断面図。FIG. 25 is a cross-sectional view of a laminated body provided with a dry film in a conventional example.
【図２６】従来例における，電解Ｎｉ／Ａｕめっき膜を
施した積層体の断面図。FIG. 26 is a cross-sectional view of a laminate having an electrolytic Ni / Au plated film in a conventional example.
【図２７】従来例における，ドライフィルムを除去した
積層体の断面図。FIG. 27 is a cross-sectional view of a laminated body in which a dry film is removed in a conventional example.
【図２８】従来例における，積層体の裏面側に配線パタ
ーン及びパッドを形成した積層体の断面図。FIG. 28 is a cross-sectional view of a laminated body in which a wiring pattern and pads are formed on the back surface side of the laminated body in a conventional example.
【図２９】従来例における，積層体の裏面側にエポキシ
系又はアクリル系等のソルダーレジストを形成した積層
体の断面図。FIG. 29 is a cross-sectional view of a laminate in which an epoxy-based or acrylic-based solder resist is formed on the back surface side of the laminate in the conventional example.
【図３０】従来例の問題点を指摘する説明図。FIG. 30 is an explanatory diagram for pointing out the problems of the conventional example.
１．．．銅箔， ２．．．第１Ｎｉ／Ａｕめっき膜， ３．．．銅めっき膜， ４．．．第２Ｎｉ／Ａｕめっき膜， ５１，５５，５６．．．配線パターン， ５２，５４．．．パッド， ５３．．．ボンディングパッド， ６．．．エポキシ系又はアクリル系等のソルダーレジス
ト， ７．．．接着層， ９．．．積層体， ９０．．．電子部品搭載部， ９１０，９２０，９３０，９４０，９５０．．．搭載
穴， ９１〜９５．．．絶縁基板， ９９．．．スルーホール，1. ． ． Copper foil, 2. ． ． First Ni / Au plated film, 3. ． ． Copper plating film, 4. ． ． Second Ni / Au plated film, 51, 55, 56. ． ． Wiring pattern, 52, 54. ． ． Pad, 53. ． ． Bonding pad, 6. ． ． 6. Epoxy-based or acrylic-based solder resist, ． ． Adhesive layer, 9. ． ． Laminate, 90. ． ． Electronic component mounting portion, 910, 920, 930, 940, 950. ． ． Mounting holes, 91-95. ． ． Insulating substrate, 99. ． ． Through hole,
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/12 Ｈ０５Ｋ 3/24 Ａ 7511−4Ｅ 3/42 Ｂ 7511−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI Technical display location H01L 23/12 H05K 3/24 A 7511-4E 3/42 B 7511-4E
Claims (5)
と電子部品搭載用の搭載穴とを形成し， （ｂ）上記配線パターンの露出部表面に，無電解めっき
法により第１Ｎｉ／Ａｕめっき膜を施し， （ｃ）上記複数の絶縁基板を積層し，積層体を得た後， （ｄ）該積層体にスルーホールを穿設し， （ｅ）上記第１Ｎｉ／Ａｕめっき膜の表面及び上記スル
ーホールの内壁を含めた上記積層体の全表面に，銅めっ
き膜を形成し， （ｆ）上記銅めっき膜における配線パターンを被覆して
いない部分をエッチングにより除去し， （ｇ）上記第１Ｎｉ／Ａｕめっき膜又は／及び銅めっき
膜の露出表面に，無電解めっき法により第２Ｎｉ／Ａｕ
めっき膜を施すことを特徴とする電子部品搭載用多層基
板の製造方法。1. A wiring pattern and a mounting hole for mounting an electronic component are formed on a plurality of insulating substrates, and (b) a first Ni / Au layer is formed on an exposed surface of the wiring pattern by electroless plating. A plating film is applied, (c) a plurality of insulating substrates are laminated to obtain a laminated body, (d) through holes are formed in the laminated body, and (e) a surface of the first Ni / Au plated film. And a copper plating film is formed on the entire surface of the laminated body including the inner wall of the through hole, (f) a portion of the copper plating film which does not cover the wiring pattern is removed by etching, and (g) the above On the exposed surface of the first Ni / Au plating film and / or the copper plating film, a second Ni / Au film is formed by electroless plating.
A method for manufacturing a multilayer substrate for mounting electronic components, which comprises applying a plating film.
は，積層体の内部に位置する内層パターンであることを
特徴とする電子部品搭載用多層基板の製造方法。2. The method for manufacturing a multilayer substrate for mounting electronic components according to claim 1, wherein the wiring pattern is an inner layer pattern located inside the laminate.
は，積層体の外部に位置する外層パターンであることを
特徴とする電子部品搭載用多層基板の製造方法。3. The method of manufacturing a multilayer substrate for mounting electronic components according to claim 1, wherein the wiring pattern is an outer layer pattern located outside the laminated body.
露出部は，上記搭載穴の周縁に形成された内層パターン
の延設部であることを特徴とする電子部品搭載用多層基
板の製造方法。4. The method of manufacturing an electronic component mounting multilayer substrate according to claim 1, wherein the exposed portion of the wiring pattern is an extended portion of an inner layer pattern formed on a peripheral edge of the mounting hole.
延設部は，ボンディングパッドであることを特徴とする
電子部品搭載用多層基板の製造方法。5. The method for manufacturing a multilayer substrate for mounting electronic components according to claim 4, wherein the extended portion of the inner layer pattern is a bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5277680A JPH07106769A (en) | 1993-10-08 | 1993-10-08 | Manufacture of multilayered substrate for mounting electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5277680A JPH07106769A (en) | 1993-10-08 | 1993-10-08 | Manufacture of multilayered substrate for mounting electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07106769A true JPH07106769A (en) | 1995-04-21 |
Family
ID=17586812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5277680A Pending JPH07106769A (en) | 1993-10-08 | 1993-10-08 | Manufacture of multilayered substrate for mounting electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07106769A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999026458A1 (en) * | 1997-11-19 | 1999-05-27 | Ibiden Co., Ltd. | Multilayer printed wiring board and method for manufacturing the same |
| EP1117283A1 (en) * | 1998-09-14 | 2001-07-18 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
| JP2002237682A (en) * | 2001-02-08 | 2002-08-23 | Cmk Corp | Multilayer printed circuit board having component- mounting recess, and its manufacturing method |
| WO2004105454A1 (en) * | 2003-05-23 | 2004-12-02 | Fujitsu Limited | Wiring board manufacturing method |
| KR100782956B1 (en) * | 2005-11-18 | 2007-12-07 | 후지쯔 가부시끼가이샤 | Wiring board manufacturing method |
-
1993
- 1993-10-08 JP JP5277680A patent/JPH07106769A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999026458A1 (en) * | 1997-11-19 | 1999-05-27 | Ibiden Co., Ltd. | Multilayer printed wiring board and method for manufacturing the same |
| US7230188B1 (en) | 1998-09-14 | 2007-06-12 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
| EP1117283A4 (en) * | 1998-09-14 | 2004-06-23 | Ibiden Co Ltd | Printed wiring board and its manufacturing method |
| EP1667507A1 (en) * | 1998-09-14 | 2006-06-07 | Ibiden Co., Ltd. | A multilayer printed circuit board and a process for manufacturing the same |
| EP1117283A1 (en) * | 1998-09-14 | 2001-07-18 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
| US7691189B2 (en) | 1998-09-14 | 2010-04-06 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
| US7827680B2 (en) | 1998-09-14 | 2010-11-09 | Ibiden Co., Ltd. | Electroplating process of electroplating an elecrically conductive sustrate |
| US8065794B2 (en) | 1998-09-14 | 2011-11-29 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
| JP2002237682A (en) * | 2001-02-08 | 2002-08-23 | Cmk Corp | Multilayer printed circuit board having component- mounting recess, and its manufacturing method |
| WO2004105454A1 (en) * | 2003-05-23 | 2004-12-02 | Fujitsu Limited | Wiring board manufacturing method |
| US7377030B2 (en) | 2003-05-23 | 2008-05-27 | Fujitsu Limited | Wiring board manufacturing method |
| US7935891B2 (en) | 2003-05-23 | 2011-05-03 | Fujitsu Limited | Wiring board manufacturing method |
| KR100782956B1 (en) * | 2005-11-18 | 2007-12-07 | 후지쯔 가부시끼가이샤 | Wiring board manufacturing method |
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