JPH0669774A - Input signal disconnection detection system - Google Patents
Input signal disconnection detection systemInfo
- Publication number
- JPH0669774A JPH0669774A JP4222371A JP22237192A JPH0669774A JP H0669774 A JPH0669774 A JP H0669774A JP 4222371 A JP4222371 A JP 4222371A JP 22237192 A JP22237192 A JP 22237192A JP H0669774 A JPH0669774 A JP H0669774A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input
- pulse
- digital signal
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は入力信号断検出方式に関
し、特に伝送回線において信号誤りを少なくするためス
クランブルやＣＭＩコード変換等の信号変換を施したデ
ジタル信号を受信する伝送端局装置の入力断検出方式に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal disconnection detection system, and more particularly to an input of a transmission terminal station device for receiving a digital signal subjected to signal conversion such as scrambling or CMI code conversion in order to reduce signal errors in a transmission line. Regarding disconnection detection method.
【０００２】[0002]
【従来の技術】従来、この種の入力信号断検出方式は、
デジタル信号を入力して、そのデジタル信号の論理レベ
ル１，０を判別し、この論理レベルに連続して変化がな
い場合、即ち、論理レベル１，０の何れかに固定された
連続する場合は信号断と判定し断信号を出力している。2. Description of the Related Art Conventionally, this type of input signal loss detection method has been
When a digital signal is input and the logic levels 1 and 0 of the digital signal are discriminated, and when there is no continuous change in this logic level, that is, when the logic levels 1 and 0 are fixed and continuous, The signal is judged to be disconnected and a disconnection signal is output.
【０００３】[0003]
【発明が解決しようとする課題】この従来の入力信号断
検出回路では、入力信号のデータの変化を検出している
ため、入力信号の正常の“１”連続あるいは“０”連続
の場合も入力データ無しと判断し、即時に断信号を発出
するために正常時に誤まった断信号を発生してしまうと
いう問題がある。Since the conventional input signal disconnection detection circuit detects a change in the data of the input signal, the input signal is detected even when the input signal is normally "1" continuous or "0" continuous. Since it is determined that there is no data and the disconnection signal is immediately issued, there is a problem that an incorrect disconnection signal is generated in a normal state.
【０００４】[0004]
【課題を解決するための手段】本発明の入力信号断検出
方式は、デジタル信号を入力して、そのデジタル信号の
論理レベル１，０を判別し前記論理レベルに変化がない
場合信号異常を表すＬＯＳ（ｌｏｓｓ ｏｆ Ｓｉｇｎ
ａｌ）信号を出力する信号異常検出回路と、前記ヂジタ
ル信号を入力し常時はゲートを閉じ前記ＬＯＳ信号を入
力した時はゲートを開き前記デジタル信号を通過させる
ゲート回路と、前記ゲート回路の出力信号が論理レベル
１あるいは０に固定され連続した時に所定同期のパルス
信号を発生するＶ−Ｆ変換回路と、前記パルス信号のパ
ルス数をカウントしあらかじめ設定したカウント数に達
した時に入力信号断を表わすＡＬＭ信号を出力するカウ
ンタとを備えている。According to the input signal disconnection detection method of the present invention, a digital signal is input, the logical levels 1 and 0 of the digital signal are discriminated, and when there is no change in the logical level, a signal abnormality is indicated. LOS (loss of Sign)
a) a signal abnormality detection circuit that outputs a signal, a gate circuit that inputs the digital signal and normally closes the gate, opens the gate when the LOS signal is input, and passes the digital signal, and an output signal of the gate circuit Is fixed to the logic level 1 or 0 and generates a pulse signal of a predetermined synchronization when it is continuous, and counts the number of pulses of the pulse signal, and indicates an input signal disconnection when the number reaches a preset number. And a counter that outputs an ALM signal.
【０００５】また、前記カウンタは外部より前記デジタ
ル信号に同期したクロック信号を入力し前記カウント数
の設定を前記クロック信号のパルス数を指定することに
より設定することでも良い。The counter may be set by inputting a clock signal synchronized with the digital signal from the outside and setting the count number by designating the pulse number of the clock signal.
【０００６】[0006]
【実施例】次に本発明の実施例について図面を参照して
説明する。図１は第１の実施例、図２は第２の実施例の
ブロック図である。Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of the first embodiment, and FIG. 2 is a block diagram of the second embodiment.
【０００７】図１において、入力端子１に入力されたデ
ジタル信号は、信号異常検出回路２とゲート回路３とに
入力される。信号異常検出回路２はモノマルチ回路また
は尖頭値検出回路（ピーク値検出回路）が用いられ、入
力デジタル信号に変化（立上がり、立下がり）がなくな
ると異常を表すＬＯＳ（ｌｏｓｓ ｏｆ Ｓｉｇｎａ
ｌ）信号を発出する。ゲート回路３はＬＯＳ信号がない
場合はゲートを閉じ、ＬＯＳ信号が入力されるとゲート
を開いて、入力信号をＶ−Ｆ変換回路４に出力する。In FIG. 1, the digital signal input to the input terminal 1 is input to the signal abnormality detection circuit 2 and the gate circuit 3. As the signal abnormality detection circuit 2, a mono-multi circuit or a peak value detection circuit (peak value detection circuit) is used, and when there is no change (rising or falling) in the input digital signal, LOS (loss of Signa) indicating an abnormality.
l) Issue a signal. The gate circuit 3 closes the gate when there is no LOS signal, opens the gate when the LOS signal is input, and outputs the input signal to the VF conversion circuit 4.
【０００８】Ｖ−Ｆ変換回路４は予め“１”（ここでは
“１”のときに５Ｖと仮定する。）の時ａｋＨｚの周波
数のパルス信号が発生するように設定する。このとき前
記のように入力端子１に“１”が入力されたので、Ｖ−
Ｆ変換回路４はパルス信号をカウンタ５に出力する。カ
ウンタ５は予めａｋＨｚの周期のパルスが例えば１００
ｍｓ以上継続した場合、入力信号断を表わすＡＬＭ信号
を発生するように設定されている。Ｖ−Ｆ変換回路４か
ら入力されたパルス信号はカウンタ５でカウントされ、
パルスが設定値以上継続すると、入力端子１に入力され
たデジタル信号が断と判断し、外部へＡＬＭ信号を出力
する。The V-F conversion circuit 4 is set in advance so that a pulse signal having a frequency of a kHz is generated when it is "1" (here, it is assumed to be 5 V when it is "1"). At this time, since "1" is input to the input terminal 1 as described above, V-
The F conversion circuit 4 outputs the pulse signal to the counter 5. The counter 5 has a pulse with a cycle of a kHz of, for example, 100 in advance.
When it continues for more than ms, it is set to generate an ALM signal indicating an input signal disconnection. The pulse signal input from the VF conversion circuit 4 is counted by the counter 5,
When the pulse continues for the set value or more, it is determined that the digital signal input to the input terminal 1 is broken, and the ALM signal is output to the outside.
【０００９】また、図２において、カウンタ９は、入力
端子１から入力されたデジタル信号に同期したクロック
９は、入力端子１から入力されたデジタル信号に同期し
たクロックを入力し、このクロックに同期した期間、例
えばクロック１００タイムスロット以上、Ｖ−Ｆ変換回
路４からのパルス信号が継続した場合、ＡＬＭ信号を発
生するようにしたもので、カウンタ回路の時間設定をク
ロック同期で行えるようにした第２の実施例を示す。Further, in FIG. 2, the counter 9 receives the clock synchronized with the digital signal input from the input terminal 1 as the clock 9 synchronized with the digital signal input from the input terminal 1, and synchronizes with the clock. The ALM signal is generated when the pulse signal from the V-F conversion circuit 4 continues for a certain period, for example, 100 clockslots or more of the clock, and the time setting of the counter circuit can be performed in synchronization with the clock. 2 shows an example.
【００１０】[0010]
【発明の効果】以上説明したように本発明は、入力信号
が論理レベル１あるいは０を持続した時に信号異常検出
回路２でＬＯＳ信号を検出し、このＬＯＳ信号がカウン
タ４であらかじめ設定された時間だけ持続した時に始め
て入力信号断と判定しＡＬＭ信号を出力しているので、
このカウンタの設定時間を最適値に選定することにより
正常時の連続信号と異常時の連続信号とを判別すること
ができる。このためＡＬＭ信号の発出精度を向上させる
効果がある。As described above, according to the present invention, the LOS signal is detected by the signal abnormality detection circuit 2 when the input signal maintains the logic level 1 or 0, and this LOS signal is set by the counter 4 for a preset time. The input signal is judged to be disconnected and the ALM signal is output for the first time when
By selecting the optimum value for the setting time of this counter, it is possible to distinguish between the continuous signal in the normal state and the continuous signal in the abnormal state. Therefore, there is an effect of improving the accuracy of issuing the ALM signal.
【図１】本発明の第１の実施例のブロック図である。FIG. 1 is a block diagram of a first embodiment of the present invention.
【図２】本発明の第２の実施例のブロック図である。FIG. 2 is a block diagram of a second embodiment of the present invention.
１ 信号入力端子 ２ 信号異常検出回路 ３ ゲート回路 ４ Ｖ−Ｆ（電圧対周波数）変換回路 ５，９ カウンタ ６ ＡＬＭ信号出力端子 ８ クロック入力端子 1 signal input terminal 2 signal abnormality detection circuit 3 gate circuit 4 VF (voltage vs. frequency) conversion circuit 5, 9 counter 6 ALM signal output terminal 8 clock input terminal
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小畑 則夫 宮城県黒川郡大和町吉岡字雷神２番地宮城 日本電気株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Norio Obata No. 2 Raijin, Yoshioka, Yamato-cho, Kurokawa-gun, Miyagi Miyagi NEC Corporation
Claims (2)
信号の論理レベル１，０を判別し前記論理レベルに変化
がない場合信号異常を表すＬＯＳ（ｌｏｓｓｏｆ Ｓｉ
ｇｎａｌ）信号を出力する信号異常検出回路と、前記デ
ジタル信号を入力し常時はゲートを閉じ前記ＬＯＳ信号
を入力した時はゲートを開き前記デジタル信号を通過さ
せるゲート回路と、前記ゲート回路の出力信号が論理レ
ベル１あるいは０に固定され連続した時に所定同期のパ
ルス信号を発生するＶ−Ｆ変換回路と、前記パルス信号
のパルス数をカウントしあらかじめ設定したカウント数
に達した時に入力信号断を表わすＡＬＭ信号を出力する
カウンタとを備えることを特徴とする入力信号断検出方
式。1. A LOS (loss of Si) indicating a signal abnormality when a digital signal is input and the logical levels 1 and 0 of the digital signal are discriminated and there is no change in the logical level.
signal abnormality detection circuit for outputting the digital signal, a gate circuit for inputting the digital signal, normally closing the gate and opening the gate for inputting the LOS signal, and passing the digital signal, and an output signal of the gate circuit Is fixed to the logic level 1 or 0 and generates a pulse signal of a predetermined synchronization when it is continuous, and counts the number of pulses of the pulse signal, and indicates an input signal disconnection when the number reaches a preset number. An input signal disconnection detection method comprising: a counter that outputs an ALM signal.
号に同期したクロック信号を入力し前記カウント数の設
定を前記クロック信号のパルス数を指定することにより
設定されることを特徴とする請求項１記載の入力信号断
検出方式。2. The counter is set by externally inputting a clock signal synchronized with the digital signal and setting the count number by designating a pulse number of the clock signal. Input signal disconnection detection method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22237192A JP3164904B2 (en) | 1992-08-21 | 1992-08-21 | Input signal loss detection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22237192A JP3164904B2 (en) | 1992-08-21 | 1992-08-21 | Input signal loss detection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0669774A true JPH0669774A (en) | 1994-03-11 |
| JP3164904B2 JP3164904B2 (en) | 2001-05-14 |
Family
ID=16781307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22237192A Expired - Fee Related JP3164904B2 (en) | 1992-08-21 | 1992-08-21 | Input signal loss detection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3164904B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007174457A (en) * | 2005-12-26 | 2007-07-05 | Kyocera Corp | Receiver equipment |
| JP2021504985A (en) * | 2017-11-28 | 2021-02-15 | マーベル インターナショナル リミテッド | Ethernet® transceiver with PHY level signal loss detector |
-
1992
- 1992-08-21 JP JP22237192A patent/JP3164904B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007174457A (en) * | 2005-12-26 | 2007-07-05 | Kyocera Corp | Receiver equipment |
| JP2021504985A (en) * | 2017-11-28 | 2021-02-15 | マーベル インターナショナル リミテッド | Ethernet® transceiver with PHY level signal loss detector |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3164904B2 (en) | 2001-05-14 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
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| LAPS | Cancellation because of no payment of annual fees |