JPH055708Y2 - - Google Patents
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- Publication number
- JPH055708Y2 JPH055708Y2 JP1984034056U JP3405684U JPH055708Y2 JP H055708 Y2 JPH055708 Y2 JP H055708Y2 JP 1984034056 U JP1984034056 U JP 1984034056U JP 3405684 U JP3405684 U JP 3405684U JP H055708 Y2 JPH055708 Y2 JP H055708Y2
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- input
- circuit
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000001514 detection method Methods 0.000 claims description 24
- 238000006073 displacement reaction Methods 0.000 claims description 9
- 230000010363 phase shift Effects 0.000 claims description 3
- 230000004069 differentiation Effects 0.000 claims description 2
- 238000007689 inspection Methods 0.000 claims description 2
- 238000007493 shaping process Methods 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 claims 1
- 230000002159 abnormal effect Effects 0.000 description 26
- 239000003990 capacitor Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
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- Maintenance And Management Of Digital Transmission (AREA)
- Dc Digital Transmission (AREA)
Description
【考案の詳細な説明】
（技術分野）
本考案は、パルス信号受信回路において、受信
パルス信号の正常性を判別し、正常信号のみを通
過させ雑音等の影響を受けた異常信号を遮断する
受信パルス信号検査回路に関する。[Detailed description of the invention] (Technical field) The present invention is a pulse signal receiving circuit that determines the normality of a received pulse signal, passes only normal signals, and blocks abnormal signals affected by noise etc. The present invention relates to a pulse signal inspection circuit.
（背景技術）
一般に、パルス信号受信回路においては、伝送
路を通過して減衰したパルス信号を増幅及び波形
等化するという波形整形が行なわれるが、この場
合、正常な受信信号でなく何らかの雑音等の影響
を受けた異常信号が入力されても上記のように増
幅等の処置を受けて受信回路の出力信号を生じ
て、装置の誤動作の原因となることがあつた。こ
のため、従来は、積分器と比較器とから構成され
た平均電圧検出回路により入力信号の平均電圧を
所定の基準電圧と比較して正常信号と異常信号と
を区別する方式、または、遅延回路とＤ形フリツ
プフロツプ回路を主要素とする位相変位検出回路
により入力信号の位相をずらして、正常信号と異
常信号とを区別する方式が使用されていた。(Background Art) Generally, in a pulse signal receiving circuit, waveform shaping is performed to amplify and equalize the waveform of a pulse signal that has passed through a transmission line and has been attenuated. Even if an abnormal signal affected by this is input, it may be subjected to amplification or other treatment as described above to generate an output signal of the receiving circuit, which may cause malfunction of the device. For this reason, conventional methods have been used to distinguish between normal and abnormal signals by comparing the average voltage of the input signal with a predetermined reference voltage using an average voltage detection circuit composed of an integrator and a comparator, or by using a delay circuit. A method was used in which the phase of an input signal is shifted using a phase shift detection circuit whose main elements are a D-type flip-flop circuit and a normal signal is distinguished from an abnormal signal.
しかし、前者のものでは、周波数が低い異常信
号が区別されるに過ぎず、また後者のものでは、
周波数が高い異常信号が区別されるに過ぎないと
いう欠点があつた。 However, the former method only distinguishes abnormal signals with low frequencies, and the latter method only distinguishes abnormal signals with low frequencies.
The drawback was that only abnormal signals with high frequencies could be distinguished.
（考案の課題）
本考案の目的は、平均電圧検出回路の出力と位
相変化検出回路の出力との論理積で判別回路の出
力信号を作成し、該出力信号の内容により受信パ
ルス信号に含まれる異常信号を遮断できる構成と
して、RZ信号のようなパルス信号の所定の周波
数に対して、周波数がかなり高い異常信号及び周
波数がかなり低い異常信号を共に区別し、異常信
号による装置の誤動作を防止することにある。以
下、本考案を実施例により説明する。(Problem for the invention) The purpose of the invention is to create an output signal of the discrimination circuit by ANDing the output of the average voltage detection circuit and the output of the phase change detection circuit, and to determine whether the output signal is included in the received pulse signal depending on the content of the output signal. As a configuration that can block abnormal signals, it distinguishes abnormal signals with a considerably high frequency and abnormal signals with a considerably low frequency with respect to a predetermined frequency of a pulse signal such as an RZ signal, and prevents equipment malfunctions due to abnormal signals. There is a particular thing. The present invention will be explained below with reference to examples.
（考案の構成及び作用） 第１図は、本考案の一実施例を示す。(Structure and operation of the device) FIG. 1 shows an embodiment of the present invention.
判別回路１は、並列接続された位相変位検出回
路１１と平均電圧検出回路１２とアンドゲート１
３とから構成され、該１１，１２の両検出回路の
出力の論理積が判別回路１の出力信号となつてい
る。該出力信号は、共通入力端子INに正常信号
が入力された場合には、論理１のＨ信号となり、
異常信号が入力された場合には、論理ＯのＬ信号
となり、その結果、ゲート回路２が正常信号の
み、通過させて共通出力端子OUTから異常信号
が出力されない構成となつている。 The discrimination circuit 1 includes a phase displacement detection circuit 11, an average voltage detection circuit 12, and an AND gate 1 connected in parallel.
3, and the AND of the outputs of both the detection circuits 11 and 12 serves as the output signal of the discrimination circuit 1. The output signal becomes a logic 1 H signal when a normal signal is input to the common input terminal IN.
When an abnormal signal is input, it becomes an L signal of logic O, and as a result, the gate circuit 2 is configured to allow only the normal signal to pass through and no abnormal signal is output from the common output terminal OUT.
位相変位検出回路１１では、遅延回路１１１と
Ｄ形フリツプフロツプ１１２を入力段に設置し、
その後に、カウンタ１１３、微分回路１１４、比
較器１１５、積分器１１６、比較器１１７が順次
直列に接続されている。遅延回路１１１の入力側
は、共通入力端子INに、出力側はＤ形フリツプ
フロツプ１１２のクロツク入力端子C1に接続さ
れ、また、該フリツプフロツプ１１２のデータ入
力端子D1は、共通入力端子INに接続され、該フ
リツプフロツプ１１２の出力端子Q1はカウンタ
１１３のクロツク入力端子C2に接続されている。
カウンタ１１３は、１ビツト・カウンタであり、
その否定側出力端子2は、微分回路１１４の入
力側に接続されている。微分回路１１４は、コン
デンサC10と抵抗R10とから構成され、カウンタ１
１３の出力が比較器１１５で判定される際にマル
チプルトリガされるのを防いでいる。比較器１１
５の非反転入力には微分回路１１４の出力が、反
転入力端子には、閾値電圧V1が各々接続され、
またその出力は積分器１１６の入力側に接続され
る。積分器１１６は抵抗R11とコンデンサC11とで
構成され、その出力は比較器１１７の反転入力端
子に接続されている。比較器１１７の非反転入力
端子には閾値電圧V2が、反転入力端子には積分
器１１６の出力が各々接続され、またその出力は
アンドゲート１３の第１の入力端子に接続されて
いる。 In the phase displacement detection circuit 11, a delay circuit 111 and a D-type flip-flop 112 are installed at the input stage.
After that, a counter 113, a differentiating circuit 114, a comparator 115, an integrator 116, and a comparator 117 are connected in series. The input side of the delay circuit 111 is connected to the common input terminal IN, the output side is connected to the clock input terminal C1 of the D-type flip-flop 112, and the data input terminal D1 of the flip-flop 112 is connected to the common input terminal IN. The output terminal Q 1 of the flip-flop 112 is connected to the clock input terminal C 2 of the counter 113.
Counter 113 is a 1-bit counter,
The negative output terminal 2 is connected to the input side of the differentiating circuit 114. The differentiating circuit 114 is composed of a capacitor C 10 and a resistor R 10 , and the counter 1
This prevents multiple triggering when the output of 13 is judged by the comparator 115. Comparator 11
The output of the differentiating circuit 114 is connected to the non-inverting input of 5, and the threshold voltage V 1 is connected to the inverting input terminal.
Further, its output is connected to the input side of the integrator 116. Integrator 116 is composed of resistor R 11 and capacitor C 11 , and its output is connected to the inverting input terminal of comparator 117 . The non-inverting input terminal of the comparator 117 is connected to the threshold voltage V 2 , the inverting input terminal is connected to the output of the integrator 116 , and the output thereof is connected to the first input terminal of the AND gate 13 .
平均電圧検出回路１２は、抵抗器R12とコンデ
ンサC12とからなる積分器１２１及び比較器１２
２から構成され、積分器１２１はその入力側が共
通入力端子INに、出力側が比較器１２２の非反
転入力端子に各々接続されている。また、比較器
１２２の反転入力端子には閾値電圧V3が接続さ
れ、その出力はアンドゲート１３の第２の入力端
子に接続されている。また、アンドゲート１３の
出力はゲート回路２の第２の入力端子に接続され
ている。 The average voltage detection circuit 12 includes an integrator 121 consisting of a resistor R 12 and a capacitor C 12 and a comparator 12.
The integrator 121 has its input side connected to the common input terminal IN, and its output side connected to the non-inverting input terminal of the comparator 122. Further, the threshold voltage V 3 is connected to the inverting input terminal of the comparator 122 , and its output is connected to the second input terminal of the AND gate 13 . Further, the output of the AND gate 13 is connected to the second input terminal of the gate circuit 2.
ゲート回路２は、アンドゲート１個から構成さ
れ、その第１の入力端子は遅延回路１１１の出力
に接続され、その出力は、出力端子OUTに接続
されている。 The gate circuit 2 is composed of one AND gate, its first input terminal is connected to the output of the delay circuit 111, and its output is connected to the output terminal OUT.
次に動作について説明する。先ず、共通入力端
子INから第２図ａに示す正常信号が入力した場
合について回路動作を述べる。周期Ｔの正常信号
が位相変位検出回路１１に入力すると、遅延回路
１１１によりτ（但し、τ＜Ｔ／２）だけ時間を
遅らされ（第２図ｂ）、カウンタ１１３のクロツ
ク端子C2に入力する。該位相変位信号（第２図
ｂ）が、クロツク信号源となつて、フリツプフロ
ツプ１１２を動作させ、その出力Q１から第２図
ｃの如き論理１のＨ信号が出力される。該出力信
号は、１ビツト・カウンタ１１３に供給され、そ
の否定側出力2から第２図ｄの如きＨ信号が出
力される。該出力信号は微分回路１１４に入力
し、該微分回路１１４の出力は第２図ｅの如き、
第２図ｄの立上り部分の微分波形となる。該信号
（第２図ｅ）は、比較器１１５に入力して、閾値
電圧V1より高レベルの部分について、比較器１
１５の出力は第２図ｆのようなパルス信号とな
る。該パルス信号は、積分器１１６に入力する
が、積分器１１６の時定数を十分大きくとれば、
該積分器１１６の出力は第２図ｇのような三角波
となる。該三角波は、比較器１１７の反転入力端
子に供給されるが、単発パルスの積分波形である
ため、閾値電圧V2より高い電圧レベルにならず、
該比較器１１７の出力は論理１のＨ信号となる
（第２図ｈ）。 Next, the operation will be explained. First, the circuit operation will be described when the normal signal shown in FIG. 2a is input from the common input terminal IN. When a normal signal with period T is input to the phase displacement detection circuit 11, the time is delayed by τ (however, τ<T/2) by the delay circuit 111 (Fig. 2b), and the signal is output to the clock terminal C2 of the counter 113. input. The phase shift signal (FIG. 2b) serves as a clock signal source to operate the flip-flop 112, and a logic 1 H signal as shown in FIG. 2c is output from its output Q1. This output signal is supplied to a 1-bit counter 113, and an H signal as shown in FIG. 2d is outputted from its negative output 2 . The output signal is input to a differentiating circuit 114, and the output of the differentiating circuit 114 is as shown in FIG.
This is the differential waveform of the rising portion of FIG. 2d. The signal (FIG. 2e) is input to the comparator 115, and the portion of the signal higher than the threshold voltage V1 is input to the comparator 115.
The output of 15 becomes a pulse signal as shown in FIG. 2f. The pulse signal is input to the integrator 116, but if the time constant of the integrator 116 is set sufficiently large,
The output of the integrator 116 becomes a triangular wave as shown in FIG. 2g. The triangular wave is supplied to the inverting input terminal of the comparator 117, but since it is an integral waveform of a single pulse, it does not reach a voltage level higher than the threshold voltage V2 .
The output of the comparator 117 becomes a logic 1 H signal (FIG. 2h).
一方、共通入力端子INから平均電圧検出回路
１２に入力された正常信号は、まず積分器１２１
に入力し、積分された第２図ｉの如き信号とな
る。その後、比較器１２２の非反転入力端子に供
給されるが、連続パルスの積分波形であるため、
反転入力に印加された閾値電圧V3より高い電圧
レベルとなつて、比較器１２２の出力は、論理１
のＨ信号となる（第２図ｊ）。該Ｈ信号は、位相
変位検出回路１１の出力信号（第２図ｈ）ととも
にアンドゲート１３に供給され、該ゲート１３の
出力は論理１のＨ信号となる（第２図ｋ）。さら
に、このＨ信号は、ゲート回路２の一方の入力端
子に供給され、ゲート回路２の一方の入力端子に
入力する遅延回路１１１の出力信号が、第２図ｌ
のように、共通出力端子OUTへ得られることと
なり、共通入力端子INへ入力した信号（第２図
ａ）が、第２図ｌの信号として通過する。 On the other hand, the normal signal input from the common input terminal IN to the average voltage detection circuit 12 is first input to the integrator 121.
The resultant signal is input to and integrated into a signal as shown in FIG. 2 i. After that, it is supplied to the non-inverting input terminal of the comparator 122, but since it is an integral waveform of continuous pulses,
At a voltage level higher than the threshold voltage V3 applied to the inverting input, the output of comparator 122 becomes a logic one.
becomes an H signal (Fig. 2 j). The H signal is supplied to the AND gate 13 together with the output signal of the phase displacement detection circuit 11 (FIG. 2h), and the output of the gate 13 becomes a logic 1 H signal (FIG. 2k). Furthermore, this H signal is supplied to one input terminal of the gate circuit 2, and the output signal of the delay circuit 111 input to one input terminal of the gate circuit 2 is
As shown in FIG. 2, the signal input to the common input terminal IN (FIG. 2a) is passed as the signal shown in FIG. 2L.
次に、正常信号の周波数に比べて高い周波数の
異常信号が、共通入力端子INに入力した場合の
動作を説明する。位相変位検出回路１１に入力さ
れた異常信号（第３図ａ）は、第３図ｂの如く時
間τだけ遅れて遅延回路１１１から出力され、第
３図ａの入力信号とともにＤ形フリツプフロツプ
１１２に入力する。すると、該フリツプフロツプ
１１２の出力は、第３図ｃの如きパルス波形とな
る。このパルス波形をカウンタ回路１１３に入力
して２分周し、第３図ｄの波形が得られる。この
波形を微分回路１１４により微分し、第３図ｅの
波形となつて、比較器１１５の非反転入力に入力
されるが、閾値V1より高い電圧レベルが存在す
るので、比較器１１５の出力は第３図ｆの如きパ
ルス波形となる。これを積分器１１６に入力する
と、繰返しパルスの積分となるので、第３図ｇの
ように閾値V2より高い電圧レベルとなり、次の
比較器１１７の出力は第３図ｈの如き論理０のＬ
信号となる。このようにして、パルス幅がτより
も狭い高周波の異常信号が入力された場合には、
論理０として検出されることになる。 Next, the operation when an abnormal signal having a higher frequency than the normal signal is input to the common input terminal IN will be described. The abnormal signal input to the phase displacement detection circuit 11 (FIG. 3a) is outputted from the delay circuit 111 with a delay of time τ as shown in FIG. input. Then, the output of the flip-flop 112 has a pulse waveform as shown in FIG. 3c. This pulse waveform is input to the counter circuit 113 and frequency-divided by two to obtain the waveform shown in FIG. 3d. This waveform is differentiated by a differentiating circuit 114, resulting in the waveform shown in FIG . has a pulse waveform as shown in FIG. 3(f). When this is input to the integrator 116, it becomes an integral of repeated pulses, so the voltage level becomes higher than the threshold value V2 as shown in Fig. 3g, and the next output of the comparator 117 becomes a logic 0 as shown in Fig. 3h. L
It becomes a signal. In this way, when a high frequency abnormal signal with a pulse width narrower than τ is input,
It will be detected as a logic zero.
一方、共通入力端子INから平均値電圧検出回
路１２に入力した異常信号（第３図ａ）は、積分
器１２１を通過後、第３図ｉの如き閾値V3より
高い電圧レベルの信号となり、比較器１２２の出
力は、第３図ｊの如き論理１のＨ信号となる。従
つて、アンドゲート１３の入力の一方は、第３図
ｈのＬ信号、もう一方は第３図ｊのＨ信号とな
り、該ゲート１３の出力は、第３図ｋの如き論理
０のＬ信号となる。このため、ゲート回路２の出
力も第３図ｌの如きＬ信号となり、異常信号は共
通出力端子OUTへ出力されない。 On the other hand, the abnormal signal input from the common input terminal IN to the average voltage detection circuit 12 (Fig. 3 a) passes through the integrator 121 and becomes a signal with a voltage level higher than the threshold V 3 as shown in Fig. 3 i, The output of the comparator 122 becomes a logic 1 H signal as shown in FIG. 3j. Therefore, one of the inputs of the AND gate 13 becomes the L signal shown in FIG. 3h, and the other becomes the H signal shown in FIG. becomes. Therefore, the output of the gate circuit 2 also becomes an L signal as shown in FIG. 3l, and no abnormal signal is output to the common output terminal OUT.
次に正常信号の周波数に比べて低い周波数の異
常信号が共通入力端子INに入力した場合の動作
を述べると、この場合の第２図ａ〜ｌ及び第３図
ａ〜ｌに対応する波形は第４図ａ〜ｌのようにな
り、共通出力端子OUTから取り出される信号は、
第４図ｌの如きＬ信号となり、異常信号は出力さ
れない。このようにして、例えば正常なクロツク
周期が取れないような低周波の異常信号が入力さ
れた場合には、平均電圧検出回路１２により論理
０として検出することができる。 Next, we will describe the operation when an abnormal signal with a frequency lower than that of the normal signal is input to the common input terminal IN. In this case, the waveforms corresponding to Fig. 2 a to l and Fig. 3 a to l are as follows. The signals taken out from the common output terminal OUT are as shown in Figure 4 a to l.
The L signal as shown in FIG. 4l is obtained, and no abnormal signal is output. In this way, for example, if a low frequency abnormal signal such as a normal clock cycle cannot be obtained is input, it can be detected as a logic 0 by the average voltage detection circuit 12.
以上説明したように、本実施例では、平均電圧
検出回路の出力と位相変位検出回路の出力との論
理積を受信パルス信号の判別結果として、ゲート
回路に供給して、受信した異常信号を遮断すると
いう方法により、所定の周波数帯の信号に関し
て、正常信号と異常信号とを区別できる利点があ
る。 As explained above, in this embodiment, the AND of the output of the average voltage detection circuit and the output of the phase displacement detection circuit is supplied to the gate circuit as the determination result of the received pulse signal to block the received abnormal signal. This method has the advantage of being able to distinguish between normal signals and abnormal signals regarding signals in a predetermined frequency band.
（考案の効果）
本考案は、受信パルス信号の正常性を判別する
回路を有しており、異常信号を受信した場合に
は、該異常信号を遮断できる利点があり、通信装
置の誤動作防止に用いることができる。(Effects of the invention) The present invention has a circuit that determines the normality of the received pulse signal, and has the advantage that when an abnormal signal is received, the abnormal signal can be blocked, which helps prevent malfunction of communication equipment. Can be used.
第１図は本考案の一実施例を示す図、第２図は
第１図の実施例の正常時の動作説明図、第３図及
び第４図は第１図の実施例の異常時の動作説明図
である。
IN……共通入力端子、OUT……出力端子、１
……判別回路、２……ゲート回路、１１……位相
変位検出回路、１２……平均電圧検出回路、１３
……アンドゲート回路、１１１……遅延回路、１
１２……Ｄ形フリツプフロツプ、１１３……１ビ
ツト・カウンタ、１１４……微分回路、１１５，
１１７，１２２……比較器、１１６，１２１……
積分器、V1，V2，V3……閾値電圧、C10，C11，
C12……コンデンサ、R10，R11，R12……抵抗。
Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is an explanatory diagram of the normal operation of the embodiment of Fig. 1, and Figs. 3 and 4 are illustrations of the embodiment of Fig. 1 in abnormal conditions. It is an operation explanatory diagram. IN...Common input terminal, OUT...Output terminal, 1
... Discrimination circuit, 2 ... Gate circuit, 11 ... Phase displacement detection circuit, 12 ... Average voltage detection circuit, 13
...And gate circuit, 111...Delay circuit, 1
12...D-type flip-flop, 113...1-bit counter, 114...differentiation circuit, 115,
117, 122... Comparator, 116, 121...
Integrator, V 1 , V 2 , V 3 ...Threshold voltage, C 10 , C 11 ,
C12 ...Capacitor, R10 , R11 , R12 ...Resistor.
Claims (1)
１１と、 前記受信パルス信号を入力として積分し、その
積分出力が所定の閾値よりも大きいときに論理１
の信号を出力する平均電圧検出回路１２と、 前記位相変位検出回路１１と前記平均電圧検出
回路１２の各出力を入力とするアンドゲート１３
とを備えた受信パルス信号検査回路であつて、 前記位相変位検出回路１２は、前記受信パルス
信号を入力とする遅延回路１１１と、該遅延回路
１１１の出力をクロツク入力としかつ前記受信パ
ルス信号をデータ入力とするフリツプフロツプ１
１２と、該フリツプフロツプ１１２の出力を入力
とする１ビツトカウンタ１１３と、該１ビツトカ
ウンタ１１３の出力を入力とする微分回路１１４
と、該微分回路１１４の出力を整形積分しかつそ
の積分出力が所定の閾値よりも小さいときに論理
１の信号を出力する手段１１５，１１６，１１７
とからなり、 前記アンドゲート１３の出力信号に応じて前記
受信パルス信号を通過又は遮断させることを特徴
とする受信パルス信号検査回路。[Claims for Utility Model Registration] A phase displacement detection circuit 11 which receives a received pulse signal as an input, integrates the received pulse signal as an input, and when the integrated output is larger than a predetermined threshold value, a logic 1 is generated.
an average voltage detection circuit 12 that outputs a signal; and an AND gate 13 that receives each output of the phase displacement detection circuit 11 and the average voltage detection circuit 12 as inputs.
The phase shift detection circuit 12 includes a delay circuit 111 that receives the received pulse signal as an input, and a clock input that uses the output of the delay circuit 111 as a clock input. Flip-flop 1 for data input
12, a 1-bit counter 113 whose input is the output of the flip-flop 112, and a differentiation circuit 114 whose input is the output of the 1-bit counter 113.
and means 115, 116, 117 for shaping and integrating the output of the differentiating circuit 114 and outputting a logic 1 signal when the integrated output is smaller than a predetermined threshold.
A received pulse signal inspection circuit comprising: passing or blocking the received pulse signal according to the output signal of the AND gate 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984034056U JPS60149264U (en) | 1984-03-12 | 1984-03-12 | Received pulse signal inspection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984034056U JPS60149264U (en) | 1984-03-12 | 1984-03-12 | Received pulse signal inspection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60149264U JPS60149264U (en) | 1985-10-03 |
| JPH055708Y2 true JPH055708Y2 (en) | 1993-02-15 |
Family
ID=30537072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984034056U Granted JPS60149264U (en) | 1984-03-12 | 1984-03-12 | Received pulse signal inspection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60149264U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5714618A (en) * | 1980-06-30 | 1982-01-25 | Mitsubishi Gas Chem Co Inc | Resin composition |
-
1984
- 1984-03-12 JP JP1984034056U patent/JPS60149264U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5714618A (en) * | 1980-06-30 | 1982-01-25 | Mitsubishi Gas Chem Co Inc | Resin composition |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60149264U (en) | 1985-10-03 |
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