JPH06232516A - Ceramic wiring board and manufacture thereof - Google Patents
Ceramic wiring board and manufacture thereofInfo
- Publication number
- JPH06232516A JPH06232516A JP1751393A JP1751393A JPH06232516A JP H06232516 A JPH06232516 A JP H06232516A JP 1751393 A JP1751393 A JP 1751393A JP 1751393 A JP1751393 A JP 1751393A JP H06232516 A JPH06232516 A JP H06232516A
- Authority
- JP
- Japan
- Prior art keywords
- alumina
- purity
- wiring
- wiring pattern
- paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、セラミックス基板上に
配線層を設けてなるセラミックス配線基板およびその製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic wiring board having a wiring layer provided on a ceramic substrate and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】電子部品の高密度化が進むにつれて、こ
れまで印刷法等により形成されてきたセラミックス配線
基板は、より配線の微細化と基板の多層化が要求されて
いる。すなわち、従来はセラミックス基板上にＡｇ−Ｐ
ｄ、Ａｕ、Ｃｕ、Ｍｏ、Ｗ等の金属粉ペーストをスクリ
ーン印刷法で印刷し焼成することにより配線を形成して
きた。2. Description of the Related Art As the density of electronic parts has increased, ceramic wiring boards which have been formed by a printing method or the like have been required to have finer wiring and multilayer boards. That is, conventionally, Ag-P is formed on a ceramic substrate.
Wirings have been formed by printing a metal powder paste of d, Au, Cu, Mo, W, or the like by a screen printing method and firing it.
【０００３】しかしながら、上述したセラミックス焼成
基板へのスクリーン印刷による厚膜配線の微細化では、
配線パターンがダレ易く、シャープな配線パターンが出
にくい問題があった。また、配線パターンをシャープに
するため、印刷厚を薄くする方法もとられるが、導通抵
抗を確保しにくい問題があった。さらに、配線パターン
の断面形状はかまぼこ型であり、配線パターン表面の平
滑性が必要な用途には不向きな問題もあった。However, in the miniaturization of thick film wiring by screen printing on the above-mentioned ceramics fired substrate,
There is a problem that the wiring pattern is easily sagged and a sharp wiring pattern is difficult to appear. Further, although a method of reducing the printing thickness can be used in order to sharpen the wiring pattern, there is a problem that it is difficult to secure the conduction resistance. Furthermore, the cross-sectional shape of the wiring pattern is a semi-cylindrical shape, and there is also a problem that it is not suitable for applications requiring smoothness of the surface of the wiring pattern.
【０００４】[0004]
【発明が解決しようとする課題】上述した従来の問題を
解消するため、焼成前のセラミックスグリーンテープ上
にスクリーン印刷による厚膜配線を施し同時焼成するこ
とも考えられ、この方法によると、厚膜配線の印刷ペー
スト中の溶剤をグリーンテープが吸収してパターンのダ
レが出にくいため、１００μm ピッチの配線が可能とな
った。しかしながら、セラミックス基板の焼成時の収縮
のバラツキにより、パターンの配線ピッチも±０．３％
〜１．０％程度もバラツキ、パターンのピッチ精度が出
にくい問題があった。In order to solve the above-mentioned problems of the prior art, it is conceivable to provide thick film wiring by screen printing on the ceramic green tape before firing and simultaneously fire it. Since the green tape absorbs the solvent in the wiring printing paste and the pattern does not easily sag, wiring with a pitch of 100 μm is possible. However, the pattern wiring pitch is ± 0.3% due to variations in shrinkage during firing of the ceramic substrate.
There was a problem that the dispersion was about 1.0%, and it was difficult to obtain the pattern pitch accuracy.
【０００５】本発明の目的は上述した課題を解消して、
寸法精度が良好で表面が平坦で、かつシャープな配線パ
ターンを得ることができるセラミックス配線基板および
その製造方法を提供しようとするものである。The object of the present invention is to solve the above problems,
It is an object of the present invention to provide a ceramics wiring board having good dimensional accuracy, a flat surface, and a sharp wiring pattern, and a method for manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】本発明のセラミックス配
線基板は、アルミナ基板と、このアルミナ基板上に設け
た、必要に応じて所定の位置に導通ビアを有する高純度
易焼結性アルミナ層と、この高純度易焼結性アルミナ層
上に設けた、配線パターンと高純度易焼結性アルミナと
からなる配線層とを有することを特徴とするものであ
る。A ceramic wiring board of the present invention comprises an alumina substrate and a high-purity easily sinterable alumina layer provided on the alumina substrate and having conductive vias at predetermined positions as needed. The present invention is characterized by having a wiring pattern and a wiring layer made of high-purity easy-sinterable alumina, which is provided on the high-purity easy-sinterable alumina layer.
【０００７】また、本発明のセラミックス配線基板の製
造方法は、アルミナ焼成基板を準備し、このアルミナ焼
成基板の表面に、このアルミナ焼成基板の原料の平均粒
子径よりも小さい平均粒子径を有する高純度易焼結性ア
ルミナのペーストを塗布し、塗布したペーストが乾燥し
た後表面研磨を行い、表面研磨を行った面に導体ペース
トをスクリーン印刷して配線パターンを印刷形成し、さ
らにこの基板上に高純度易焼結性アルミナのペーストを
塗布し、塗布したペーストが乾燥した後表面研磨を行
い、焼成することを特徴とするものである。Further, in the method for manufacturing a ceramics wiring board of the present invention, an alumina fired substrate is prepared, and the surface of the alumina fired substrate has a high average particle diameter smaller than the average particle diameter of the raw material of the alumina fired substrate. Applying a paste of pure easy-sintering alumina, after the applied paste is dried, the surface is polished, the conductor paste is screen-printed on the surface that has been polished to form a wiring pattern, and further on this substrate. It is characterized in that a paste of high-purity easily sinterable alumina is applied, and after the applied paste is dried, surface polishing is performed and firing is performed.
【０００８】[0008]
【作用】上述した構成のうち、まずセラミックス配線基
板に関する発明においては、高純度易焼結性アルミナか
らなる層の上に、メタライズからなる配線パターンを設
けるだけでなく、配線パターン間を高純度易焼結性アル
ミナで埋めているため、寸法精度が良好でシャープな配
線パターンを得ることができる。また、セラミックス配
線基板の製造方法に関する発明においては、アルミナ焼
成基板上に所定の粒度の高純度易焼結性アルミナのペー
ストを塗布し、その後配線パターンを形成する導体ペー
ストおよび高純度易焼結性アルミナのペーストを塗布
し、乾燥後研磨した後同時焼成しているため、表面が平
坦で寸法精度が良好でシャープな配線パターンを得るこ
とができる。In the invention relating to the ceramics wiring substrate among the above-mentioned constitutions, first, not only the wiring pattern made of metallization is provided on the layer made of high-purity and easy-sinterable alumina, but also the wiring pattern between the wiring patterns is made high in purity. Since it is filled with sinterable alumina, a dimensional accuracy is good and a sharp wiring pattern can be obtained. Further, in the invention relating to the method for manufacturing a ceramics wiring substrate, a conductor paste for forming a wiring pattern after applying a paste of high-purity easy-sinterable alumina of a predetermined grain size on an alumina fired substrate and a high-purity easy-sinterability substrate Since the alumina paste is applied, dried, polished, and then co-fired, it is possible to obtain a sharp wiring pattern having a flat surface and good dimensional accuracy.
【０００９】ここで、高純度易焼結性アルミナとは、好
ましい性質の一例として、純度９９．９％以上、アルミ
ナの平均粒子径が０．２μm 以下、焼結温度が１３５０
℃以下のアルミナ粉末のことをいう。なお、アルミナ焼
成基板上に直接塗布する高純度易焼結性アルミナペース
トの塗布厚は、焼結後の塗布厚が３〜３０μm であると
好ましい。厚みが３μm 未満であると、焼成基板の焼結
助剤と高純度易焼結性アルミナが焼成中に溶融して良好
な表面状態が得られないことがあるとともに、厚みが３
０μm を超えると、高純度易焼結性アルミナの焼結する
ときの収縮が著しくなり、焼結後クラックが発生するた
めである。Here, the high-purity easily sinterable alumina is, as an example of preferable properties, a purity of 99.9% or more, an average particle diameter of alumina of 0.2 μm or less, and a sintering temperature of 1350.
Alumina powder having a temperature of ℃ or less. The coating thickness of the high-purity easily sinterable alumina paste applied directly onto the alumina fired substrate is preferably 3 to 30 μm after the sintering. If the thickness is less than 3 μm, the sintering aid of the firing substrate and the high-purity easy-sintering alumina may be melted during firing, and a good surface condition may not be obtained.
If it exceeds 0 μm, shrinkage of the high-purity easily sinterable alumina during sintering becomes remarkable, and cracks occur after sintering.
【００１０】また、アルミナ焼成基板の配線パターンを
形成すべき表面を焼成基板よりも微粒の高純度易焼結性
アルミナ層としたのは、ポアがなく良好な表面粗さを有
するセラミック基板を得ることにより、その上にスクリ
ーン印刷法でも従来より微細な導体配線パターンを得る
ことができるようにするためである。The surface of the alumina fired substrate on which the wiring pattern is to be formed is a finer and more highly pure and easily sinterable alumina layer than the fired substrate, and a ceramic substrate having no pores and having a good surface roughness is obtained. By doing so, it is possible to obtain a finer conductor wiring pattern than the conventional one by the screen printing method.
【００１１】[0011]
【実施例】図１および図２はそれぞれ本発明のセラミッ
クス配線基板の断面を示す図であり、図１は基板にビア
がない場合を、図２は基板にビアが有る場合をそれぞれ
示している。図１および図２において、１はアルミナか
らなる焼成セラミックス基板、２は焼成セラミックス基
板１中に存在するビア、３は焼成セラミックス基板１上
に設けた高純度易焼結性アルミナ層、４は高純度易焼結
性アルミナ層３内のビア２に対応する位置に設けたパッ
ド部、５は高純度易焼結性アルミナ層３上に設けた微細
な配線パターン、６は配線パターン５の間に設けた高純
度易焼結性アルミナ、７は高純度易焼結性アルミナ６内
にパッド部４に対応する位置に設けたパッド部であり、
配線パターン５および高純度易焼結性アルミナ６とが配
線層８を形成している。1 and 2 are cross-sectional views of a ceramic wiring board according to the present invention. FIG. 1 shows a case where there is no via in the board, and FIG. 2 shows a case where there is a via in the board. . In FIGS. 1 and 2, 1 is a sintered ceramic substrate made of alumina, 2 is a via existing in the sintered ceramic substrate 1, 3 is a high-purity easily sinterable alumina layer provided on the sintered ceramic substrate 1, and 4 is a high Pad portions 5 provided at positions corresponding to the vias 2 in the high purity easy sinterable alumina layer 3 are fine wiring patterns provided on the high purity easy sinterable alumina layer 3, and 6 are between the wiring patterns 5. The provided high-purity easy-sinterable alumina, 7 is a pad portion provided in the high-purity easy-sinterable alumina 6 at a position corresponding to the pad portion 4,
The wiring pattern 5 and the high-purity easily sinterable alumina 6 form the wiring layer 8.
【００１２】図１および図２に示す構造の本発明のセラ
ミックス配線基板では、高純度易焼結性アルミナ層３の
上に配線パターン５を設けているため微細配線を形成で
き、さらに配線パターン５の間を高純度易焼結性アルミ
ナ６で埋めているため、同時焼成時に配線パターンのゆ
がみやダレをなくすことができ、寸法精度が良好でシャ
ープな配線パターンを形成することができる。In the ceramic wiring board of the present invention having the structure shown in FIGS. 1 and 2, fine wiring can be formed because the wiring pattern 5 is provided on the high-purity and easily-sinterable alumina layer 3, and further the wiring pattern 5 can be formed. Since the high-purity and easily-sinterable alumina 6 is filled in the gap, distortion and sag of the wiring pattern can be eliminated at the time of simultaneous firing, and a sharp wiring pattern with good dimensional accuracy can be formed.
【００１３】図３は本発明のセラミックス配線基板の製
造方法の一例を工程順に示す図であり、図１に示す基板
にビアがない場合の製造方法を示す。まず、図３（ａ）
に示すように、アルミナ粉体に３〜１０重量％の焼結助
剤を加えて混合後、ドクターブレード法等の方法により
成形する。ここで、焼結助剤としては通常のMgO 、CaO
、SiO2、TiO2、ZrO2等が用いられている。次に、成形
体を焼成してセラミックス基板１を得る。FIG. 3 is a diagram showing an example of a method of manufacturing the ceramic wiring board of the present invention in the order of steps, and shows the manufacturing method when the board shown in FIG. 1 has no vias. First, FIG. 3 (a)
As shown in (3), 3 to 10% by weight of the sintering aid is added to the alumina powder, mixed, and then molded by a method such as a doctor blade method. Here, as the sintering aid, usual MgO, CaO
, SiO 2 , TiO 2 , ZrO 2 and the like are used. Next, the molded body is fired to obtain the ceramic substrate 1.
【００１４】次に、図３（ｂ）に示すように、得られた
焼成セラミックス基板１の表面に高純度易焼結性アルミ
ナからなるペースト１１を塗布して高純度易焼結性アル
ミナ層３を形成する。このペーストは、焼成セラミック
ス基板１の原料の平均粒子径よりも小さい平均粒子径を
有する高純度易焼結性アルミナ粉体と有機バインダー、
有機溶媒とを混合して作製し、塗布法に適した粘度に調
整される。塗布方法は、印刷、カレンダーロール、スプ
レー、静電塗装、ディップ、ナイフコータ等のできるだ
け塗布後の平滑性が良い方法を選択すると好ましい。次
に、高純度易焼結性アルミナペーストを塗布した面を乾
燥後、乾燥した面を表面研磨して平滑にする。なお、表
面の平滑度が塗布で十分であれば、乾燥後の表面研磨工
程を省略することもできる。Next, as shown in FIG. 3 (b), a paste 11 made of high-purity easy-sinterable alumina is applied to the surface of the obtained fired ceramics substrate 1 to obtain a high-purity easy-sinterable alumina layer 3. To form. This paste is a high-purity easily sinterable alumina powder having an average particle size smaller than the average particle size of the raw material of the fired ceramics substrate 1, and an organic binder,
It is prepared by mixing with an organic solvent and adjusted to a viscosity suitable for the coating method. As a coating method, it is preferable to select a method such as printing, calendar roll, spraying, electrostatic coating, dipping, and knife coater, which has as smooth a smoothness as possible after coating. Next, after drying the surface coated with the high-purity easy-sinterable alumina paste, the dried surface is polished to be smooth. If the surface smoothness is sufficient for coating, the surface polishing step after drying can be omitted.
【００１５】次に、図３（ｃ）に示すように、乾燥した
だけの生の状態の高純度易焼結性アルミナ層３の研磨面
に、W 、Mo金属粉からなる導体ペースト１２を配線パタ
ーンに従ってスクリーン印刷した後、図３（ｄ）に示す
ように高純度易焼結性アルミナからなるペースト１３を
塗布し、さらに、図３（ｅ）に示すように乾燥後研磨し
て、配線パターン５および高純度易焼結性アルミナ６と
からなる配線層８を形成する。このとき、配線パターン
をスクリーン印刷直後に一旦焼成することもできる。ま
た、印刷する配線パターンの厚さは焼成セラミックス基
板１の反り分より厚くしておくと好ましい。さらに、導
体ペーストの硬度が高純度易焼結性アルミナペーストの
硬度より低い場合は、配線層のうち配線パターンの高さ
を高純度易焼結性アルミナの高さより低くすることがで
き、その後配線パターンにリード等を半田付けする際半
田の流れ防止を達成することができる。Next, as shown in FIG. 3 (c), a conductor paste 12 made of W and Mo metal powders is wired on the polished surface of the high-purity and easily-sinterable alumina layer 3 which is just dried. After screen-printing according to the pattern, a paste 13 made of high-purity easy-sinterable alumina is applied as shown in FIG. 3D, and further dried and polished as shown in FIG. 5 and the high-purity easily-sinterable alumina 6 are formed into the wiring layer 8. At this time, the wiring pattern can be fired once immediately after screen printing. The thickness of the printed wiring pattern is preferably thicker than the warpage of the fired ceramics substrate 1. Further, when the hardness of the conductor paste is lower than the hardness of the high-purity easy-sinterable alumina paste, the height of the wiring pattern in the wiring layer can be made lower than that of the high-purity easy-sinterable alumina, and then the wiring is It is possible to prevent solder flow when soldering leads or the like to the pattern.
【００１６】最後に、配線パターン５と高純度易焼結性
アルミナ６とからなる配線層８を設けた基板を、好まし
くは１２００〜１３００℃の温度で焼成して、本発明の
セラミックス配線基板を得ている。この場合、導体ペー
ストの焼成収縮が高純度易焼結性ペーストの焼成収縮よ
り大きいと、前述した場合と同様に配線層のうち配線パ
ターンの高さを高純度易焼結性アルミナの高さより低く
することができ、半田流れを防止することができる。な
お、焼成後、配線パターン５上に、Niめっき、Ni/Au め
っき、Ni/Pb-Sn（半田）めっきを施すこともでき、その
方法は電気めっきでも無電界めっきでもよい。Finally, the substrate provided with the wiring layer 5 consisting of the wiring pattern 5 and the high-purity easily sinterable alumina 6 is preferably fired at a temperature of 1200 to 1300 ° C. to obtain the ceramic wiring substrate of the present invention. It has gained. In this case, if the firing shrinkage of the conductor paste is larger than the firing shrinkage of the high-purity easy-sinterable paste, the height of the wiring pattern in the wiring layer is lower than the height of the high-purity easy-sinterable alumina as in the case described above. It is possible to prevent solder flow. After firing, the wiring pattern 5 may be plated with Ni, Ni / Au, or Ni / Pb-Sn (solder), which may be electroplating or electroless plating.
【００１７】図４は本発明のセラミックス配線基板の製
造方法の他の例を工程順に示す図であり、図２に示す基
板にビアがある場合の製造方法を示す。まず、図３に示
す例と同様にして、図４（ａ）に示すように、内部の所
定位置にビア２を設けたセラミックス焼成体１を準備す
る。次に、図４（ｂ）に示すように、ビア２に対応する
位置に、W 、Mo等からなる導体ペースト１４を印刷して
パッド部４を形成した後、一旦焼成する。場合によっ
て、このパッド部４の焼成は省略することができる。FIG. 4 is a diagram showing another example of the method of manufacturing the ceramic wiring board of the present invention in the order of steps, showing the method of manufacturing when the substrate shown in FIG. 2 has vias. First, similarly to the example shown in FIG. 3, as shown in FIG. 4A, a ceramic fired body 1 having vias 2 provided at predetermined internal positions is prepared. Next, as shown in FIG. 4B, a conductive paste 14 made of W, Mo or the like is printed at the position corresponding to the via 2 to form the pad portion 4, and then the pad portion 4 is fired once. Depending on the case, the firing of the pad portion 4 can be omitted.
【００１８】次に、図３に示す例と同様にして、図４
（ｃ）に示すように、高純度易焼結性アルミナペースト
１１を塗布し、乾燥後研磨して、図４（ｄ）に示すよう
にパッド部４を露出させた高純度易焼結性アルミナ層３
を形成する。次に、図４（ｅ）に示すように導体ペース
ト１２を印刷することにより配線パターン５とパッド部
７を形成し、さらに図４（ｆ）に示すように高純度易焼
結性アルミナペースト１３を塗布し、乾燥後研磨して、
図４（ｇ）に示すように配線パターン５、パッド部７お
よび高純度易焼結性アルミナ６からなる配線層８を形成
した後、図３に示した例と同様に焼成して、本発明のセ
ラミックス配線基板を得ている。なお、これまでの実施
例では、１組の高純度易焼結性アルミナ層と、この高純
度易焼結性アルミナ層上に設けた、配線パターンと高純
度易焼結性アルミナ層とからなる配線層を有する例を示
したが、これに限らずこのくり返しが２以上あっても良
いことは言うまでもない。Next, in the same manner as the example shown in FIG.
As shown in (c), a high-purity easy-sinterable alumina paste 11 is applied, dried and then polished to expose the pad portion 4 as shown in FIG. 4 (d). Layer 3
To form. Next, as shown in FIG. 4 (e), the conductive paste 12 is printed to form the wiring pattern 5 and the pad portion 7, and further, as shown in FIG. 4 (f), the high-purity easily sinterable alumina paste 13 is formed. Is applied, dried and then polished,
As shown in FIG. 4 (g), after forming the wiring pattern 5, the pad portion 7 and the wiring layer 8 made of the high-purity easily sinterable alumina 6, the same as in the example shown in FIG. Has obtained a ceramic wiring board. It should be noted that in the above-described examples, a set of a high-purity easy-sinterable alumina layer and a wiring pattern and a high-purity easy-sinterable alumina layer provided on the high-purity easy-sinterable alumina layer are provided. Although an example having a wiring layer is shown, it is needless to say that the number of repetitions is not limited to this and may be two or more.
【００１９】以下、実際に配線パターンの寸法精度、シ
ャープネス、厚さおよび平坦性について測定した結果に
ついて説明する。配線パターンの寸法精度 配線パターンの寸法精度を求めるため、本発明の製造方
法に従って、線幅５０μm 、線間隔５０μm で合計１０
０本の平行直線パターンからなる配線パターンを形成
し、１００本のトータルピッチである１０ｍｍに対する
ズレ量を測定したところ、３０個のセラミックス配線基
板において１０ｍｍ±４μm と非常に構成度のピッチ精
度を得ることができた。The results obtained by actually measuring the dimensional accuracy, sharpness, thickness and flatness of the wiring pattern will be described below. Dimensional accuracy of wiring pattern In order to obtain the dimensional accuracy of the wiring pattern, a total of 10 lines with a line width of 50 μm and a line interval of 50 μm are used according to the manufacturing method of the present invention.
A wiring pattern consisting of 0 parallel linear patterns was formed, and the amount of deviation from the total pitch of 100 lines of 10 mm was measured. As a result, a pitch accuracy of 10 mm ± 4 μm was obtained for 30 ceramic wiring boards, which was a very high degree of composition. I was able to.
【００２０】配線パターンのシャープネス 配線パターンのシャープネスを求めるため、本発明の製
造方法に従ったものと、焼成基板上に配線パターンをス
クリーン印刷しただけの比較例とにおいて、線間５０μ
m で線幅５０、７５、１００μm の平行な配線パターン
を形成し、配線パターンを走査型電子顕微鏡（ＳＥＭ）
で観察し、線幅の標準偏差値としてｎ＝３０のバラツキ
を求めた。結果を表１に示す。表１の結果から、本発明
例のものが比較例のものと比較して線幅のバラツキが小
さく、配線パターンのシャープネスが良好であることが
わかった。To obtain the sharpness of the wiring pattern, in order to obtain the sharpness of the wiring pattern, the line spacing is 50 μm between the one according to the manufacturing method of the present invention and the comparative example in which the wiring pattern is merely screen-printed on the fired substrate.
Form parallel wiring patterns with line widths of 50, 75, and 100 μm in m and scan the wiring patterns with a scanning electron microscope (SEM).
And the variation of n = 30 was obtained as the standard deviation value of the line width. The results are shown in Table 1. From the results shown in Table 1, it was found that the example of the present invention has a smaller variation in the line width and the sharpness of the wiring pattern is better than that of the comparative example.
【００２１】[0021]
【表１】 [Table 1]
【００２２】配線パターンの厚さ 配線パターンの厚さを求めるため、本発明の製造方法に
従った製造工程中、印刷乾燥後の配線パターンの厚さと
生研磨・焼成後の配線パターンの厚さとを測定したとこ
ろ、印刷乾燥後の配線パターンの厚さは１３μm で、研
磨・焼成後の配線パターンの厚さは５μm で、いずれも
良好な値を示していた。 Thickness of Wiring Pattern In order to obtain the thickness of the wiring pattern, during the manufacturing process according to the manufacturing method of the present invention, the thickness of the wiring pattern after printing and drying and the thickness of the wiring pattern after raw polishing / baking are calculated. As a result of measurement, the thickness of the wiring pattern after printing and drying was 13 μm, and the thickness of the wiring pattern after polishing / baking was 5 μm, which were all good values.
【００２３】配線パターンの平坦性 配線パターンの平坦性を求めるため、図５（ａ）に示す
本発明に従った配線パターンと、図５（ｂ）に示す高純
度易焼結性アルミナ層上に厚膜印刷しただけの比較例の
配線パターンとに対し、厚さ方向の高低差のバラツキを
求めたところ、本発明のものでは高低差は最大１．２μ
m で３μm 以内の高低差に全線幅域が存在するのに対
し、比較例のものでは３μm 以内の高低差の部分は全線
幅域の２２％にしか存在しなかった。[0023] To determine the flatness of the flatness wiring pattern of the wiring pattern, the wiring pattern in accordance with the present invention shown in FIG. 5 (a), high purity sinterability alumina layer shown in FIG. 5 (b) When the variation in height difference in the thickness direction was obtained with respect to the wiring pattern of the comparative example which was only printed with a thick film, the height difference of the present invention was 1.2 μ at maximum.
In the height difference within 3 μm in m, the entire line width region exists, whereas in the comparative example, the height difference within 3 μm exists only in 22% of the entire line width region.
【００２４】[0024]
【発明の効果】以上の説明から明らかなように、本発明
によれば、高純度易焼結性アルミナからなる層の上に、
メタライズからなる配線パターンを設けるだけでなく、
配線パターン間を高純度易焼結性アルミナで埋めている
ため、寸法精度が良好でシャープな配線パターンを得る
ことができ、また、アルミナ焼成基板上に所定の粒度の
高純度易焼結性アルミナのペーストを塗布し、その後配
線パターンを形成する導体ペーストおよび高純度易焼結
性アルミナのペーストを塗布し、乾燥後研磨した後同時
焼成しているため、表面が平坦で寸法精度が良好でシャ
ープな配線パターンを得ることができる。As is apparent from the above description, according to the present invention, a layer made of high-purity and easy-sintering alumina is formed,
Not only providing a wiring pattern consisting of metallization,
Since the space between the wiring patterns is filled with high-purity easy-sintering alumina, it is possible to obtain a sharp wiring pattern with good dimensional accuracy. Moreover, a high-purity easy-sintering alumina of a predetermined grain size can be obtained on the alumina fired substrate. Is applied, then the conductor paste for forming the wiring pattern and the high-purity easy-sinterable alumina paste are applied, dried, polished, and then co-fired, so the surface is flat and the dimensional accuracy is good and sharp. It is possible to obtain various wiring patterns.
【図１】本発明のセラミックス配線基板の断面の一例を
示す図である。FIG. 1 is a diagram showing an example of a cross section of a ceramics wiring board of the present invention.
【図２】本発明のセラミックス配線基板の断面の他の例
を示す図である。FIG. 2 is a diagram showing another example of a cross section of the ceramic wiring board of the present invention.
【図３】本発明のセラミックス配線基板の製造方法の一
例を工程順に示す図である。FIG. 3 is a diagram showing an example of a method of manufacturing a ceramics wiring board according to the present invention in the order of steps.
【図４】本発明のセラミックス配線基板の製造方法の他
の例を工程順に示す図である。FIG. 4 is a diagram showing another example of the method for manufacturing a ceramic wiring board of the present invention in the order of steps.
【図５】本発明例および比較例の配線パターンの平坦性
を説明するための図である。FIG. 5 is a diagram for explaining the flatness of the wiring patterns of the example of the present invention and the comparative example.
１ 焼成セラミックス基板 ２ ビア ３ 高純度易焼結性アルミナ層 ４、７ パッド部 ５ 配線パターン ６ 高純度易焼結性アルミナ ８ 配線層 １１、１３ 高純度易焼結性アルミナペースト １２ 導体ペースト 1 Firing Ceramics Substrate 2 Via 3 High Purity Easy Sintering Alumina Layer 4, 7 Pad Part 5 Wiring Pattern 6 High Purity Easy Sintering Alumina 8 Wiring Layer 11, 13 High Purity Easy Sintering Alumina Paste 12 Conductor Paste
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/46 Ｈ 6921−4Ｅ (72)発明者 伊藤 重幸 山梨県都留市鹿留329番地の２─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Reference number within the agency FI Technical indication location H05K 3/46 H 6921-4E (72) Inventor Shigeyuki Ito 2 329, Kadome, Tsuru City, Yamanashi Prefecture
Claims (4)
設けた、必要に応じて所定の位置に導通ビアを有する高
純度易焼結性アルミナ層と、この高純度易焼結性アルミ
ナ層上に設けた、配線パターンと高純度易焼結性アルミ
ナとからなる配線層とを有することを特徴とするセラミ
ックス配線基板。1. An alumina substrate, a high-purity easy-sinterable alumina layer provided on the alumina substrate and having conductive vias at predetermined positions as necessary, and on the high-purity easy-sinterable alumina layer. A ceramics wiring board having a wiring pattern and a wiring layer made of high-purity and easily-sinterable alumina.
度易焼結性アルミナ層上に設けた、配線パターンと高純
度易焼結性アルミナとからなる配線層とのくり返しを２
以上有する請求項１記載のセラミックス配線基板。2. A high-purity easy-sinterable alumina layer and a wiring layer formed on the high-purity easy-sinterable alumina layer, the wiring pattern being composed of the high-purity easy-sinterable alumina, are repeated 2 times.
The ceramic wiring board according to claim 1 having the above.
ナ焼成基板の表面に、このアルミナ焼成基板の原料の平
均粒子径よりも小さい平均粒子径を有する高純度易焼結
性アルミナのペーストを塗布し、塗布したペーストが乾
燥した後表面研磨を行い、表面研磨を行った面に導体ペ
ーストをスクリーン印刷して配線パターンを印刷形成
し、さらにこの基板上に高純度易焼結性アルミナのペー
ストを塗布し、塗布したペーストが乾燥した後表面研磨
を行い、焼成することを特徴とするセラミックス配線基
板の製造方法。3. An alumina calcined substrate is prepared, and a high-purity easily sinterable alumina paste having an average particle size smaller than the average particle size of the raw material of the alumina calcined substrate is applied to the surface of the alumina calcined substrate. After the applied paste is dried, the surface is polished, the conductive paste is screen-printed on the surface to form a wiring pattern, and the high-purity easily sinterable alumina paste is applied on this substrate. Then, after the applied paste is dried, surface polishing is performed and firing is performed, and a method for manufacturing a ceramics wiring board.
場合、アルミナ焼成基板の表面に高純度易焼結性アルミ
ナのペーストを塗布する前に、内層ビア上に導体ペース
トを印刷しパッド部を形成し、必要に応じて焼成する請
求項３記載のセラミックス配線基板の製造方法。4. When the alumina fired substrate has inner layer vias, a conductor paste is printed on the inner layer vias to form a pad portion before the paste of high-purity easy-sinterable alumina is applied to the surface of the alumina fired substrate. The method for manufacturing a ceramics wiring board according to claim 3, wherein the firing is performed as necessary.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1751393A JPH06232516A (en) | 1993-02-04 | 1993-02-04 | Ceramic wiring board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1751393A JPH06232516A (en) | 1993-02-04 | 1993-02-04 | Ceramic wiring board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06232516A true JPH06232516A (en) | 1994-08-19 |
Family
ID=11946056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1751393A Pending JPH06232516A (en) | 1993-02-04 | 1993-02-04 | Ceramic wiring board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06232516A (en) |
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|---|---|---|---|---|
| JPH11284345A (en) * | 1998-03-31 | 1999-10-15 | Kyocera Corp | Ceramic multi-layer wiring board |
| JP2002353626A (en) * | 2001-05-28 | 2002-12-06 | Kyocera Corp | Multilayer wiring board and method of manufacturing the same |
| JP2003101228A (en) * | 2001-09-27 | 2003-04-04 | Kyocera Corp | Method for manufacturing ceramic laminate |
| JP2004063811A (en) * | 2002-07-29 | 2004-02-26 | Kyocera Corp | Wiring substrate and its manufacturing method |
| JP2005086056A (en) * | 2003-09-10 | 2005-03-31 | Tdk Corp | Lamination chip forming member and method for manufacturing lamination chip electronic component |
| JP2005277385A (en) * | 2004-02-27 | 2005-10-06 | Tdk Corp | Laminate chip inductor forming member and method of manufacturing laminate chip inductor comonent |
| JP2005285836A (en) * | 2004-03-26 | 2005-10-13 | Matsushita Electric Works Ltd | Ceramics substrate for mounting photoelectric conversion element and its production process |
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| JPWO2013161133A1 (en) * | 2012-04-27 | 2015-12-21 | パナソニックＩｐマネジメント株式会社 | Ceramic substrate composite and method for producing ceramic substrate composite |
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-
1993
- 1993-02-04 JP JP1751393A patent/JPH06232516A/en active Pending
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|---|---|---|---|---|
| JPH11284345A (en) * | 1998-03-31 | 1999-10-15 | Kyocera Corp | Ceramic multi-layer wiring board |
| JP2002353626A (en) * | 2001-05-28 | 2002-12-06 | Kyocera Corp | Multilayer wiring board and method of manufacturing the same |
| JP4693284B2 (en) * | 2001-05-28 | 2011-06-01 | 京セラ株式会社 | Multilayer wiring board and manufacturing method thereof |
| JP2003101228A (en) * | 2001-09-27 | 2003-04-04 | Kyocera Corp | Method for manufacturing ceramic laminate |
| JP2004063811A (en) * | 2002-07-29 | 2004-02-26 | Kyocera Corp | Wiring substrate and its manufacturing method |
| JP2005086056A (en) * | 2003-09-10 | 2005-03-31 | Tdk Corp | Lamination chip forming member and method for manufacturing lamination chip electronic component |
| JP2005277385A (en) * | 2004-02-27 | 2005-10-06 | Tdk Corp | Laminate chip inductor forming member and method of manufacturing laminate chip inductor comonent |
| JP2005285836A (en) * | 2004-03-26 | 2005-10-13 | Matsushita Electric Works Ltd | Ceramics substrate for mounting photoelectric conversion element and its production process |
| JP2010263237A (en) * | 2007-04-30 | 2010-11-18 | Samsung Electro-Mechanics Co Ltd | Carrier member for transmitting circuit, coreless printed circuit board using the same, and method of manufacturing the same |
| JP2013062546A (en) * | 2007-04-30 | 2013-04-04 | Samsung Electro-Mechanics Co Ltd | Carrier member for transmitting circuit, coreless printed circuit board using the same, and method of manufacturing the same |
| JP2009283973A (en) * | 2009-08-17 | 2009-12-03 | Panasonic Electric Works Co Ltd | Ceramics substrate for mounting photoelectric conversion element and production method therefor |
| JP2012142318A (en) * | 2010-12-28 | 2012-07-26 | Mitsuboshi Belting Ltd | Manufacturing method of pattern substrate |
| US20140022699A1 (en) * | 2011-03-28 | 2014-01-23 | Murata Manufacturing Co., Ltd. | Glass ceramic substrate and method for producing the same |
| US9466425B2 (en) * | 2011-03-28 | 2016-10-11 | Murata Manufacturing Co., Ltd. | Glass ceramic substrate and method for producing the same |
| JPWO2013161133A1 (en) * | 2012-04-27 | 2015-12-21 | パナソニックＩｐマネジメント株式会社 | Ceramic substrate composite and method for producing ceramic substrate composite |
| JP2016184647A (en) * | 2015-03-26 | 2016-10-20 | 住友ベークライト株式会社 | Method of manufacturing organic resin substrate, organic resin substrate, and semiconductor device |
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