JPH0611527A - Pulse phase difference detecting circuit - Google Patents
Pulse phase difference detecting circuitInfo
- Publication number
- JPH0611527A JPH0611527A JP4190051A JP19005192A JPH0611527A JP H0611527 A JPH0611527 A JP H0611527A JP 4190051 A JP4190051 A JP 4190051A JP 19005192 A JP19005192 A JP 19005192A JP H0611527 A JPH0611527 A JP H0611527A
- Authority
- JP
- Japan
- Prior art keywords
- delay
- gate
- pulse
- circuit
- phase difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Measurement Of Unknown Time Intervals (AREA)
- Measuring Phase Differences (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はパルス位相差検出回路に
関し、特に所定の遅延時間を有する信号遅延回路を複数
接続してパルス位相差を高い分解能でしかも広い範囲で
正確に検出する検出回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse phase difference detection circuit, and more particularly to a detection circuit for accurately detecting a pulse phase difference with a high resolution and in a wide range by connecting a plurality of signal delay circuits having a predetermined delay time. .
【０００２】[0002]
【従来の技術】２つのパルスの位相差を検出すること
は、圧力等の物理量を正確に知り、あるいはレーザの反
射光から対象物までの距離を正確に知る等の各種測定回
路に有用である。2. Description of the Related Art Detecting the phase difference between two pulses is useful for various measuring circuits such as accurately knowing a physical quantity such as pressure, or accurately knowing the distance from the reflected light of a laser to an object. .
【０００３】かかるパルス位相差検出回路として、例え
ば特開昭６０−２５３９９４号公報では、一定の遅れ時
間を有する信号遅延回路としての遅延ゲートを多数直列
接続して、２つの入力パルスの位相差に応じて異なる位
置の遅延ゲートから出力される信号をエンコードし、位
相差信号を得ている。As such a pulse phase difference detection circuit, for example, in Japanese Unexamined Patent Publication No. 60-253994, a large number of delay gates as signal delay circuits having a constant delay time are connected in series to obtain a phase difference between two input pulses. Accordingly, the signals output from the delay gates at different positions are encoded to obtain the phase difference signal.
【０００４】ところで、上記位相差検出回路で、広い範
囲の位相差を精度を落とすことなく検出しようとする
と、検出分解能は各遅延ゲートの遅延時間で決まるか
ら、多数の遅延ゲートを設ける必要があり、半導体チッ
プ上にコンパクトに形成することが困難となる。By the way, if the phase difference detection circuit tries to detect a wide range of phase differences without degrading the accuracy, the detection resolution is determined by the delay time of each delay gate, so that it is necessary to provide a large number of delay gates. However, it becomes difficult to form it compactly on a semiconductor chip.
【０００５】そこでこれを解決するために、特開平３−
２２０８１４号公報には、複数の遅延ゲートを直列接続
するとともに後段遅延ゲートと初段遅延ゲートを接続し
てリング状とし、入力する先行パルスを周回せしめ、後
続パルスが入力した時の先行パルスの周回位置と周回数
より両パルス間の位相差を検出するものが示されてお
り、かかる構成によれば、ゲート数を大幅に増加せしめ
ることなく、広範囲の位相差を精度良く検出することが
できる。Therefore, in order to solve this, Japanese Patent Laid-Open No.
JP-A-220814 discloses that a plurality of delay gates are connected in series, a rear stage delay gate and a first stage delay gate are connected to form a ring shape, and a preceding pulse to be input is circulated, and a circulation position of the preceding pulse when a subsequent pulse is inputted. It is shown that the phase difference between both pulses is detected based on the number of turns and the number of turns. According to this configuration, a wide range of phase differences can be accurately detected without significantly increasing the number of gates.
【０００６】[0006]
【発明が解決しようとする課題】遅延ゲートをリング状
に接続した上記検出回路は上記の如く優れた特性を発揮
するものであるが、遅延ゲートをリング状に接続した場
合には、各遅延ゲートの遅延時間をすべて等しくするた
めに各遅延ゲートを円形に配置して接続しなければなら
ず、半導体チップの大型化を招くことになる。そこで、
遅延ゲートを直線状に複数直列接続した遅延ブロックを
多数設けて、これらを並列に折り返して環状とすること
が考えられる。The above-mentioned detection circuit in which delay gates are connected in a ring shape exhibits excellent characteristics as described above, but when the delay gates are connected in a ring shape, each delay gate is In order to make all the delay times equal, the delay gates must be arranged in a circle and connected, which leads to an increase in the size of the semiconductor chip. Therefore,
It is conceivable to provide a large number of delay blocks in which a plurality of delay gates are linearly connected in series and fold these in parallel to form a ring.
【０００７】かかる場合、単一の遅延ブロックの終段の
遅延ゲートと初段の遅延ゲートを結ぶ接続線の配線長、
あるいは複数の遅延ブロックの終段の遅延ゲートから次
段の遅延ブロックの初段の遅延ゲートに至る間の配線長
が、遅延ブロック内の各遅延ゲート間の配線長に比して
長くなり、この部分の遅延時間が変化するため実際のパ
ルス位相差と検出信号の間に線形性が失われるおそれが
ある。In this case, the wiring length of the connecting line connecting the delay gate at the final stage and the delay gate at the first stage of a single delay block,
Alternatively, the wiring length from the delay gate at the final stage of the plurality of delay blocks to the delay gate at the first stage of the delay block at the next stage becomes longer than the wiring length between the delay gates in the delay block. There is a possibility that the linearity may be lost between the actual pulse phase difference and the detection signal because the delay time changes.
【０００８】本発明はかかる課題を解決するもので、信
号遅延回路の遅延時間のバラツキを防止して、パルス位
相差との間に良好な線形性を確保したパルス位相差検出
回路を提供することを目的とする。The present invention solves the above problem, and provides a pulse phase difference detection circuit which prevents variations in the delay time of a signal delay circuit and ensures good linearity with the pulse phase difference. With the goal.
【０００９】[0009]
【課題を解決するための手段】本発明の構成を説明する
と、所定の遅延時間を有する信号遅延回路を複数直線状
に直列接続した少なくとも一つの遅延ブロックを設け、
これら遅延ブロックを並列に折り返して、各遅延ブロッ
クの終段の信号遅延回路を次段の遅延ブロックの初段の
信号遅延回路に接続するとともに、最終段の遅延ブロッ
クの終段の信号遅延回路を最初段の遅延ブロックの初段
の信号遅延回路に接続して環状遅延パルス発生回路を構
成し、該回路に入力する先行パルスを回路内で周回せし
めて、後続パルスが入力した時点での、先行パルスの周
回位置と周回数より両パルス間の位相差を検出するパル
ス位相差検出回路であって、上記各遅延ブロックの少な
くとも終段の信号遅延回路の電流駆動能力を、残る信号
遅延回路の電流駆動能力に比して大きく設定したもので
ある。To explain the structure of the present invention, at least one delay block in which a plurality of signal delay circuits having a predetermined delay time are connected in series in a straight line is provided.
These delay blocks are folded back in parallel, the signal delay circuit at the final stage of each delay block is connected to the signal delay circuit at the first stage of the delay block at the next stage, and the signal delay circuit at the final stage of the delay block at the final stage is first performed. By connecting the signal delay circuit of the first stage of the delay block of the stage to form the annular delay pulse generation circuit, the preceding pulse input to the circuit is circulated in the circuit, and the preceding pulse at the time when the subsequent pulse is input. A pulse phase difference detection circuit for detecting a phase difference between both pulses based on the circulation position and the number of revolutions, wherein the current drive capability of at least the final stage signal delay circuit of each delay block is equal to the current drive capability of the remaining signal delay circuit. It is set larger than.
【００１０】[0010]
【作用】上記構成において、終段の信号遅延回路と初段
の信号遅延回路との間の接続線の長さが、遅延ブロック
内の各信号遅延回路間の接続線に比して長いと、接続線
の相対的に大きな配線容量および抵抗により、周回する
先行パルスの遅延時間がこの部分のみで長くなって、実
際のパルス位相差と検出信号との間の線形性が失われ
る。ここにおいて、本発明では、接続線に出力する終段
の信号遅延回路の電流駆動能力を大きくしてあるから、
大きな配線容量等を有する接続線に対して遅延時間の増
大を防止することができ、パルス位相差と検出信号間の
線形性が確保される。In the above structure, if the connection line between the final stage signal delay circuit and the initial stage signal delay circuit is longer than the connection line between the signal delay circuits in the delay block, the connection is established. Due to the relatively large wiring capacitance and resistance of the line, the delay time of the preceding pulse that circulates becomes long only in this portion, and the linearity between the actual pulse phase difference and the detection signal is lost. Here, in the present invention, since the current drive capability of the final stage signal delay circuit outputting to the connection line is increased,
It is possible to prevent an increase in delay time with respect to a connection line having a large wiring capacity and the like, and ensure linearity between the pulse phase difference and the detection signal.
【００１１】[0011]
【実施例１】パルス位相差検出回路の構成を図１に示
す。図において、検出回路は２つの遅延ブロック１Ａ，
１Ｂを有し、各遅延ブロック１Ａ，１Ｂはパルスセレク
タ１５を挟んで並列し、それぞれ反対方向へ直線状に多
数の信号遅延回路たる遅延ゲート１１，１２ａ，１２ｂ
を直列接続して構成されている。First Embodiment FIG. 1 shows the configuration of a pulse phase difference detection circuit. In the figure, the detection circuit includes two delay blocks 1A,
1B, each delay block 1A, 1B is arranged in parallel with a pulse selector 15 in between, and delay gates 11, 12a, 12b, which are a large number of signal delay circuits linearly in opposite directions, respectively.
Are connected in series.
【００１２】本実施例では、これら遅延ゲート１１，１
２ａ，１２ｂは図２に示す如き、ＰＭＯＳ１１１とＮＭ
ＯＳ１１２を直列接続して、共通のゲートを入力端、共
通のドレインを出力端としたＣＭＯＳインバータで構成
され、遅延時間はほぼ一定の数ナノ秒で、遅延ブロック
１Ａで３１個、遅延ブロック１Ｂで３２個がそれぞれ設
けてある。In this embodiment, these delay gates 11 and 1 are
2a and 12b are PMOS 111 and NM as shown in FIG.
It is composed of CMOS inverters in which OS112s are connected in series and a common gate is an input end and a common drain is an output end, and the delay time is approximately constant nanoseconds. 31 delay blocks 1A and delay blocks 1B 32 pieces are provided respectively.
【００１３】各遅延ゲート１１，１２ａ，１２ｂの出力
端はパルスセレクタ１５にも接続され、また、遅延ブロ
ック１Ａの終段の遅延ゲート１２ａは接続線１３により
遅延ブロック１Ｂの初段の遅延ゲート１１に、遅延ブロ
ック１Ｂの終段の遅延ゲート１２ｂは，接続線１４によ
りＯＲゲート１８およびＮＡＮＤゲート１９を経て遅延
ブロック１Ａの初段の遅延ゲート１１にそれぞれ接続さ
れて、環状の遅延パルス発生回路１を構成している。The output terminals of the delay gates 11, 12a and 12b are also connected to a pulse selector 15, and the delay gate 12a at the final stage of the delay block 1A is connected to the delay gate 11 at the first stage of the delay block 1B by a connection line 13. The delay gate 12b at the final stage of the delay block 1B is connected to the delay gate 11 at the first stage of the delay block 1A via a connection line 14 via an OR gate 18 and a NAND gate 19, respectively, and forms a circular delay pulse generation circuit 1. is doing.
【００１４】先行パルスＰA が上記ＯＲゲート１８に入
力すると、該パルスＰA は各遅延ゲート１１，１２ａ，
１２ｂの遅れ時間を伴って順次伝播し、遅延パルス発生
回路１内を周回する。この周回時に各遅延ゲート１１，
１２ａ，１２ｂを通過する毎にその一部は遅延パルスと
して上記パルスセレクタ１５に入力する。パルスセレク
タ１５は、相前後する遅延ゲート１１，１２ａ，１２ｂ
からの遅延パルスを入力する所定数のＥＸＯＲゲートを
有しており、後続パルスＰB が入力した時点で、各遅延
パルスの状態が内蔵フリップフロップに記憶されて、先
行パルスＰA が到達している遅延ゲート１１，１２ａ，
１２ｂに対応するＥＸＯＲゲートよりセレクト信号が出
力される。When the preceding pulse PA is input to the OR gate 18, the pulse PA is applied to each delay gate 11, 12a,
It propagates sequentially with a delay time of 12b and circulates in the delay pulse generating circuit 1. Each delay gate 11,
Every time it passes through 12a and 12b, a part thereof is input to the pulse selector 15 as a delay pulse. The pulse selector 15 includes delay gates 11, 12a, 12b which are arranged one behind the other.
It has a predetermined number of EXOR gates for inputting the delay pulse from, and when the subsequent pulse PB is input, the state of each delay pulse is stored in the built-in flip-flop, and the delay that the preceding pulse PA has reached Gates 11 and 12a,
A select signal is output from the EXOR gate corresponding to 12b.
【００１５】エンコーダ１６は、上記セレクト信号を発
したＥＸＯＲゲートの順番に対応した２進符号出力を発
する。一方、遅延パルス発生回路１を先行パルスＰA が
周回する回数はカウンタ１７により積算され、２進符号
として出力される。しかして、先行パルスＰA が入力し
てから後続パルスＰB が入力するまでの位相差（時間
差）が、エンコーダ１６およびカウンタ１７の出力より
知られる。なお、遅延パルス発生回路１のリセットは
「０」レベルのリセットパルスＰC によって行う。The encoder 16 issues a binary code output corresponding to the order of the EXOR gates which issued the select signal. On the other hand, the number of times the preceding pulse PA circulates in the delay pulse generating circuit 1 is integrated by the counter 17 and output as a binary code. Therefore, the phase difference (time difference) from the input of the preceding pulse PA to the input of the subsequent pulse PB is known from the outputs of the encoder 16 and the counter 17. The delay pulse generation circuit 1 is reset by the reset pulse PC of "0" level.
【００１６】かかる遅延パルス発生回路１を半導体チッ
プ上に形成した場合のマスク図を図３に示す。図は遅延
ブロック１Ａの終段部と遅延ブロック１Ｂの初段部を示
し、各遅延ゲート１１、１２ａは、共通のポリシリコン
膜１１３をゲートとし、Ｐ+拡散層１１４からなるソー
ス、ドレインを有するＰＭＯＳ１１１と、Ｎ+ 拡散層１
１５からなるソース、ドレインを有するＮＭＯＳ１１２
とよりなるＣＭＯＳインバータにて構成されている。FIG. 3 shows a mask diagram when the delay pulse generating circuit 1 is formed on a semiconductor chip. The figure shows the final stage of the delay block 1A and the initial stage of the delay block 1B. The delay gates 11 and 12a have a common polysilicon film 113 as a gate, and a PMOS 111 having a source and a drain made of a P + diffusion layer 114. And N + diffusion layer 1
NMOS 112 having source / drain 15
And a CMOS inverter.
【００１７】各遅延ゲート１１，１２ａのＰＭＯＳ１１
１およびＮＭＯＳ１１２の各ドレインは、Ａｌ等の金属
配線１１６で次段の遅延ゲート１１のゲート１１３に接
続されている。このうち、遅延ブロック１Ａの終段の遅
延ゲート１２ａから延出する金属配線１１６は、比較的
長い接続線１３となって遅延ブロック１Ｂの初段の遅延
ゲート１１に接続されており、この部分で配線容量およ
び抵抗が大きくなっている。なお、図中、１１８は電源
用の金属配線、１１９はアース用の金属配線である。Ｐ
+ 拡散層１１４、Ｎ+ 拡散層１１５以外の拡散層（例え
ばＰウエル、Ｎウエル）は省略している。The PMOS 11 of each delay gate 11, 12a
The drains of 1 and the NMOS 112 are connected to the gate 113 of the delay gate 11 at the next stage by a metal wiring 116 such as Al. Of these, the metal wiring 116 extending from the final stage delay gate 12a of the delay block 1A becomes a relatively long connection line 13 and is connected to the first stage delay gate 11 of the delay block 1B. Increased capacity and resistance. In the figure, reference numeral 118 is a metal wire for power supply, and 119 is a metal wire for ground. P
Diffusion layers other than the + diffusion layer 114 and the N + diffusion layer 115 (for example, P well and N well) are omitted.
【００１８】ここで、遅延ゲート１２ａのＰＭＯＳ１１
１のゲート１１３に注目すると、そのゲート長はＬであ
り、ゲート幅はＷ２としてあって、ゲート長は他の遅延
ゲート１１と等しいが、ゲート幅Ｗ２は他の遅延ゲート
１１のゲート幅Ｗ１のほぼ２倍としてある。これはＮＭ
ＯＳ１１２のゲート１１３についても同様である。この
結果、遅延ゲート１２ａの電流駆動能力は他の遅延ゲー
ト１１の２倍となっている。もちろん、必要な電流駆動
能力を得ることができれば２倍に限られるものではな
い。Here, the PMOS 11 of the delay gate 12a
Focusing on the gate 113 of No. 1, the gate length is L, the gate width is W2, and the gate length is equal to that of the other delay gate 11, but the gate width W2 is equal to the gate width W1 of the other delay gate 11. It is almost doubled. This is NM
The same applies to the gate 113 of the OS 112. As a result, the current driving capability of the delay gate 12a is twice that of the other delay gates 11. Of course, the number is not limited to two as long as the required current driving capability can be obtained.
【００１９】かかる構造により、配線容量等の大きい接
続線１３が出力端に接続されていても、遅延ゲート１２
ａより遅延ブロック１Ｂの初段遅延ゲート１１へ至る間
のパルス伝達遅れは、他の遅延ゲート１１間と同程度に
小さくなる。なお、遅延ブロック１Ｂの終段の遅延ゲー
ト１２ｂ（図１参照）も上記遅延ゲート１２ａと同一構
造となっている。With this structure, even if the connection line 13 having a large wiring capacitance is connected to the output terminal, the delay gate 12
The pulse transmission delay from a to the first stage delay gate 11 of the delay block 1B is as small as between the other delay gates 11. The delay gate 12b (see FIG. 1) at the final stage of the delay block 1B has the same structure as the delay gate 12a.
【００２０】この効果を図４に示し、各遅延ゲート１１
の遅延時間が一定であるため、パルス位相差と検出デジ
タル出力との間の線形性が良く保たれている。これに対
して、図５に示す従来の検出装置では、各遅延ブロック
の終段の遅延ゲートで接続線の配線容量等により遅延時
間が長くなるため、図のＡ矢印、Ｂ矢印で示す部分でパ
ルス位相差と検出デジタル出力との間の線形性が失われ
ている。This effect is shown in FIG. 4, in which each delay gate 11
Since the delay time is constant, the linearity between the pulse phase difference and the detected digital output is well maintained. On the other hand, in the conventional detection device shown in FIG. 5, the delay time becomes long due to the wiring capacitance of the connecting line in the delay gate at the final stage of each delay block. The linearity between the pulse phase difference and the detected digital output is lost.
【００２１】[0021]
【実施例２】上記実施例では、各遅延ブロック１Ａ，１
Ｂにおける終段の遅延ゲート１２ａ，１２ｂのＣＭＯＳ
を構成するゲート幅を、他の遅延ゲート１１のゲート幅
に比して大きくしたが、これは直前段の遅延ゲート１１
から見ると負荷容量が大きくなることになる。そこで、
図６に示す如く、終段の直前段の遅延ゲート１１を構成
するＰＭＯＳ１１１のゲート幅Ｗ４を、終段の遅延ゲー
ト１２ａのゲート幅Ｗ５よりは小さいが、残る他の遅延
ゲート１１のゲート幅Ｗ３よりも大きくして電流駆動能
力を上げる。ＮＭＯＳ１１２のゲート幅についても同様
である。これにより、終段のゲート容量が大きくなった
ことによる遅延時間の増大が抑えられ、検出出力の線形
性をさらに改善することができる。Second Embodiment In the above embodiment, each delay block 1A, 1
CMOS of the final stage delay gates 12a and 12b in B
The gate width of the delay gate 11 is made larger than that of the other delay gates 11.
From the perspective, the load capacity will increase. Therefore,
As shown in FIG. 6, the gate width W4 of the PMOS 111 constituting the delay gate 11 of the immediately preceding final stage is smaller than the gate width W5 of the delay gate 12a of the final stage, but the gate width W3 of the remaining delay gates 11 is reduced. To increase the current drive capacity. The same applies to the gate width of the NMOS 112. As a result, it is possible to suppress an increase in delay time due to an increase in the gate capacitance in the final stage, and it is possible to further improve the linearity of the detection output.
【００２２】なお、上記各実施例において、ゲート幅を
大きくするのに代えて、ゲート長を短くしても同様の効
果が得られる。In each of the above embodiments, the same effect can be obtained by shortening the gate length instead of increasing the gate width.
【００２３】また、各遅延ブロックの終段およびこれの
直前段のみでなく、さらに数段前から漸次ゲート幅を大
きくし、あるいはゲート長を短くするようにしても良
い。Further, the gate width may be gradually increased or the gate length may be shortened not only in the final stage of each delay block and the stage immediately before it but also several stages before.
【００２４】遅延ブロックは上記各実施例における如き
２つには限られず、必要に応じて１つあるいは３つ以上
設けることができる。The number of delay blocks is not limited to two as in each of the above embodiments, and one or three or more delay blocks can be provided as required.
【００２５】[0025]
【発明の効果】以上の如く、本発明によれば、広い測定
範囲を有し、検出出力の線形性に優れたパルス位相差検
出回路を半導体チップ上にコンパクトに形成することが
できる。As described above, according to the present invention, a pulse phase difference detection circuit having a wide measurement range and excellent detection output linearity can be compactly formed on a semiconductor chip.
【図面の簡単な説明】[Brief description of drawings]
【図１】パルス位相差検出回路のブロック回路図であ
る。FIG. 1 is a block circuit diagram of a pulse phase difference detection circuit.
【図２】遅延ゲートの回路図である。FIG. 2 is a circuit diagram of a delay gate.
【図３】遅延パルス発生回路の部分マスク図である。FIG. 3 is a partial mask diagram of a delay pulse generation circuit.
【図４】本発明回路の出力特性図である。FIG. 4 is an output characteristic diagram of the circuit of the present invention.
【図５】従来回路の出力特性図である。FIG. 5 is an output characteristic diagram of a conventional circuit.
【図６】遅延パルス発生回路の他の例を示す部分マスク
図である。FIG. 6 is a partial mask diagram showing another example of the delay pulse generating circuit.
１ 遅延パルス発生回路 １Ａ，１Ｂ 遅延ブロック １１，１２ａ，１２ｂ 遅延ゲート（信号遅延回路） １３，１４ 接続線 1 Delay pulse generation circuit 1A, 1B Delay block 11, 12a, 12b Delay gate (signal delay circuit) 13, 14 Connection line
Claims (1)
複数直線状に直列接続した少なくとも１つの遅延ブロッ
クを設け、これら遅延ブロックを並列に折り返して、各
遅延ブロックの終段の信号遅延回路を次段の遅延ブロッ
クの初段の信号遅延回路に接続するとともに、最終段の
遅延ブロックの終段の信号遅延回路を最初段の遅延ブロ
ックの初段の信号遅延回路に接続して環状遅延パルス発
生回路を構成し、該回路に入力する先行パルスを回路内
で周回せしめて、後続パルスが入力した時点での、先行
パルスの周回位置と周回数より両パルス間の位相差を検
出するパルス位相差検出回路であって、上記各遅延ブロ
ックの少なくとも終段の信号遅延回路の電流駆動能力
を、残る信号遅延回路の電流駆動能力に比して大きく設
定したことを特徴とするパルス位相差検出回路。1. At least one delay block in which a plurality of signal delay circuits having a predetermined delay time are linearly connected in series is provided, and these delay blocks are folded back in parallel to form a signal delay circuit at the final stage of each delay block. Connect the signal delay circuit of the first stage of the delay block of the next stage and the signal delay circuit of the last stage of the delay block of the last stage to the signal delay circuit of the first stage of the delay block of the first stage to form a circular delay pulse generation circuit. A pulse phase difference detection circuit configured to rotate a preceding pulse input to the circuit in the circuit and detect a phase difference between the two pulses based on the winding position and the number of turns of the preceding pulse at the time when the subsequent pulse is input. The current drive capability of at least the final stage signal delay circuit of each delay block is set to be larger than the current drive capability of the remaining signal delay circuits. Pulse phase difference detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4190051A JP2988130B2 (en) | 1992-06-24 | 1992-06-24 | Pulse phase difference detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4190051A JP2988130B2 (en) | 1992-06-24 | 1992-06-24 | Pulse phase difference detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0611527A true JPH0611527A (en) | 1994-01-21 |
| JP2988130B2 JP2988130B2 (en) | 1999-12-06 |
Family
ID=16251530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4190051A Expired - Lifetime JP2988130B2 (en) | 1992-06-24 | 1992-06-24 | Pulse phase difference detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2988130B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH104353A (en) * | 1996-06-17 | 1998-01-06 | Denso Corp | A/d converter |
| JP2006003310A (en) * | 2004-06-21 | 2006-01-05 | Tokyo Gas Co Ltd | Ultrasonic flowmeter |
| JP2007322235A (en) * | 2006-05-31 | 2007-12-13 | Denso Corp | Clocking circuit |
| WO2008156289A3 (en) * | 2007-06-18 | 2009-02-26 | Atlab Inc | Delay time measurement circuit and method |
| JP2013051720A (en) * | 2008-09-19 | 2013-03-14 | Atlab Inc | Sensor |
-
1992
- 1992-06-24 JP JP4190051A patent/JP2988130B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH104353A (en) * | 1996-06-17 | 1998-01-06 | Denso Corp | A/d converter |
| JP2006003310A (en) * | 2004-06-21 | 2006-01-05 | Tokyo Gas Co Ltd | Ultrasonic flowmeter |
| JP2007322235A (en) * | 2006-05-31 | 2007-12-13 | Denso Corp | Clocking circuit |
| WO2008156289A3 (en) * | 2007-06-18 | 2009-02-26 | Atlab Inc | Delay time measurement circuit and method |
| KR100921815B1 (en) * | 2007-06-18 | 2009-10-16 | 주식회사 애트랩 | Delay time measurement circuit and method |
| JP2010529476A (en) * | 2007-06-18 | 2010-08-26 | エーティーラブ・インコーポレーテッド | Delay time measuring circuit and delay time measuring method |
| JP2013051720A (en) * | 2008-09-19 | 2013-03-14 | Atlab Inc | Sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2988130B2 (en) | 1999-12-06 |
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