JPH0547010B2 - - Google Patents
Info
- Publication number
- JPH0547010B2 JPH0547010B2 JP60292852A JP29285285A JPH0547010B2 JP H0547010 B2 JPH0547010 B2 JP H0547010B2 JP 60292852 A JP60292852 A JP 60292852A JP 29285285 A JP29285285 A JP 29285285A JP H0547010 B2 JPH0547010 B2 JP H0547010B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- output
- amplifier
- peak
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003287 optical effect Effects 0.000 claims description 23
- 238000001514 detection method Methods 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000000630 rising effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/695—Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
- Optical Communication System (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はデイジタル光受信回路に係り、特に任
意パターンを伝送する回路において、パルス幅の
歪を抑圧する回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital optical receiving circuit, and particularly to an improvement of a circuit that suppresses pulse width distortion in a circuit that transmits an arbitrary pattern.
［従来の技術］
第４図に従来の光受信回路の一例を示す。任意
のパターンを伝送するため各ブロツク間は直流結
合されている。[Prior Art] FIG. 4 shows an example of a conventional optical receiving circuit. Each block is DC-coupled to transmit an arbitrary pattern.
受光素子１に入力した光信号は、電流に変換さ
れ、前置・主増幅器２に入力して所定の振幅まで
増幅される。ピーク検出回路３ではそのコンデン
サ４によつて増幅器出力のピーク電圧を保持し、
保持したピーク電圧は抵抗５，６から成る分圧回
路７により一定比に分圧される。この比率は50％
とするのが一般的である。分圧回路７の基準電圧
を発生する基準電圧発生回路８は、光信号のない
ときの増幅器２の出力と等しい電圧を発生するも
ので、増幅器２と全く同一の回路構成により実現
できる。即ち、受光素子が無いため常に光信号が
ない場合の電圧を発生できるのである。 The optical signal input to the light receiving element 1 is converted into a current, input to the front/main amplifier 2, and amplified to a predetermined amplitude. In the peak detection circuit 3, the peak voltage of the amplifier output is held by the capacitor 4,
The held peak voltage is divided into constant ratios by a voltage dividing circuit 7 made up of resistors 5 and 6. This ratio is 50%
It is common to do so. The reference voltage generating circuit 8 that generates the reference voltage of the voltage dividing circuit 7 generates a voltage equal to the output of the amplifier 2 when there is no optical signal, and can be realized by the same circuit configuration as the amplifier 2. That is, since there is no light receiving element, a voltage can always be generated when there is no optical signal.
分圧回路７は信号のピークレベルと無信号時の
電圧の中間点に相当する電圧を発生するため、信
号の中間点を基準として比較回路９は信号“１”、
“０”に識別できる。これは、比較回路９のしき
い値を常に信号の中心とすることができるからで
ある。 Since the voltage divider circuit 7 generates a voltage corresponding to the midpoint between the peak level of the signal and the voltage when there is no signal, the comparator circuit 9 outputs a signal "1", using the midpoint of the signal as a reference.
It can be identified as “0”. This is because the threshold value of the comparator circuit 9 can always be set at the center of the signal.
このように構成された光受信回路は構成が簡単
であるため、10Mb／ｓ程度までの伝送には一般
的に使用されている。 Since the optical receiving circuit configured in this manner has a simple configuration, it is generally used for transmission up to about 10 Mb/s.
［発明が解決しようとする問題点］
しかし、上述した従来の光受信回路では、ピー
ク検出回路３のホールド時間は有限であるため、
長時間光信号の無しの状態が続いた後の動作に問
題があつた。[Problems to be Solved by the Invention] However, in the conventional optical receiving circuit described above, the hold time of the peak detection circuit 3 is finite;
There was a problem with the operation after a long period of no optical signal.
これを第５図の各部の応答波形により説明す
る。図中、のａ，ｂは第４図中の記号と対応した
各部の波形を示す。 This will be explained using the response waveforms of each part in FIG. In the figure, a and b indicate waveforms of each part corresponding to the symbols in FIG. 4.
まず、時刻t2までの間は、光信号がない状態が
続いたため、ピーク検出回路３は機能せず、しき
い電圧ｂは低下してしまつている。このとき本来
ならば、しきい電圧ｂは信号ａと全く同電位（回
路のオフセツトを考えない場合）になるはずであ
る。しかし、こうすると回路の熱雑音のため比較
回路９出力にランダムなパルス列を発生するとい
う問題があるため、同図に示すように、適宜の手
段により微小電圧ΔVのオフセツトｃを故意に設
定し、比較器出力を“０”とする工夫をしてい
る。次に、時刻t0に光信号が入力するとピーク検
出回路３が働き、その結果しきい電圧ｂが上昇
し、信号ピーク値の1/2の電圧に設定される。こ
のようにすると、時刻t3以降では信号レベルの中
心にしきい値が設定されるので出力パルスは歪の
ないパルスとなる。 First, until time t2 , there continues to be a state where there is no optical signal, so the peak detection circuit 3 does not function, and the threshold voltage b has decreased. At this time, originally, the threshold voltage b should be at exactly the same potential as the signal a (if the offset of the circuit is not considered). However, if this is done, there is a problem that a random pulse train will be generated in the output of the comparator circuit 9 due to the thermal noise of the circuit, so as shown in the figure, the offset c of the minute voltage ΔV is intentionally set by appropriate means. The comparator output is set to "0". Next, when an optical signal is input at time t 0 , the peak detection circuit 3 operates, and as a result, the threshold voltage b increases and is set to 1/2 of the signal peak value. In this way, after time t3 , the threshold value is set at the center of the signal level, so the output pulse becomes a distortion-free pulse.
しかし、図から容易に分かるように、最初の信
号パルスａでは、そのパルスの立上り部が本来時
刻t2で立上るべきところを、しきい電圧ｂの立上
りよりも速い時刻t1で立上つてしまうため、｜t2
−t1｜のパルス幅歪を生じることになる。これ
は、ピーク検出回路３の時間遅れのために生じる
問題であり、本質的に避けられない問題であつ
た。 However, as can be easily seen from the figure, in the first signal pulse a, the rising edge of the pulse, which should originally rise at time t 2 , rises at time t 1 , which is earlier than the rise of the threshold voltage b. To put away, ｜t 2
This results in a pulse width distortion of −t 1 |. This is a problem caused by the time delay of the peak detection circuit 3, and is essentially an unavoidable problem.
このように従来技術の問題は、比較回路９のし
きい電圧ｂの立上りが遅いため生じ、この遅延は
ホールドするため避けられないことである。した
がつて、単純に考えると、信号ａを遅延させれば
解決できるように思われる。しかし現実には、例
えばピーク検出回路３の立上り時間は50〜100ns
程度必要とするが、アナログ信号をこれだけの時
間遅延させるのは困難であるという問題があり、
実現はできなかつた。 As described above, the problem of the prior art arises because the threshold voltage b of the comparator circuit 9 rises slowly, and this delay is unavoidable because it is held. Therefore, from a simple perspective, it seems that the problem can be solved by delaying the signal a. However, in reality, for example, the rise time of peak detection circuit 3 is 50 to 100 ns.
However, the problem is that it is difficult to delay analog signals by this amount of time.
It could not be realized.
［発明の目的］
本発明の目的は前記した従来技術の問題点を解
消し、パルス幅に歪を生じることのない光受信回
路を提供することである。[Object of the Invention] An object of the present invention is to solve the problems of the prior art described above and to provide an optical receiving circuit that does not cause distortion in pulse width.
［発明の概要］
上記目的に沿う本発明は、増幅器出力を分圧し
て得られる増幅分圧電圧と、増幅器出力のピーク
レベルをホールドするピーク検出回路出力を分圧
して得られるピーク分圧電圧とのうちから、高い
方の電圧を選択して得られる電圧を比較回路のし
きい電圧とするとともに、増幅器の出力と比較回
路の入力との間に遅延回路を挿入したものであ
る。[Summary of the Invention] In accordance with the above object, the present invention provides an amplified divided voltage obtained by dividing the amplifier output, and a peak divided voltage obtained by dividing the output of a peak detection circuit that holds the peak level of the amplifier output. The voltage obtained by selecting the higher voltage among them is used as the threshold voltage of the comparator circuit, and a delay circuit is inserted between the output of the amplifier and the input of the comparator circuit.
これにより、比較回路のしきい電圧の立上り時
間を速くするとともに、信号を遅延させ、信号入
力以前にしきい値を所定の電圧に設定するように
したものである。 This speeds up the rise time of the threshold voltage of the comparison circuit, delays the signal, and sets the threshold to a predetermined voltage before the signal is input.
［実施例］
本発明の実施例を第１図〜第３図に基づいて説
明すれば以下の通りである。[Example] An example of the present invention will be described below based on FIGS. 1 to 3.
第１図は本発明の直流結合型デイジタル光受信
回路例を示す。第２図は第１図の各部の応答波形
図である。なお、図中、第４図に示した従来例と
同一機能を有する部分には同一符号を付してその
詳細な説明を省略する。 FIG. 1 shows an example of a DC-coupled digital optical receiving circuit according to the present invention. FIG. 2 is a response waveform diagram of each part in FIG. 1. In the figure, parts having the same functions as those of the conventional example shown in FIG. 4 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.
ピーク検出回路３、コンデンサ４及び分圧回路
７の働きは従来と同様であり、波形ｂに示すよう
に信号振幅Vpの1/2のピーク分圧電圧をホールド
する（第２図イ）。増幅器２と基準電圧発生回路
８間に接続された、抵抗１０，１１から成る分圧
回路１２は、信号ａをそのまま1/2に分圧して増
幅分圧電圧を得るもので、ｄに示す波形となる
（第２図ロ）。すなわち、増幅分圧電圧ｄのピーク
レベルは、分圧回路７の出力であるピーク分圧電
圧ｂと等しくなる。基準電圧発生回路８に接続さ
れたオフセツト電圧発生回路１３は、既述したよ
うに光信号が無い場合に比較器９の出力を確実に
“０”とするための微小電圧ΔVを発生する回路
である。 The functions of the peak detection circuit 3, capacitor 4, and voltage dividing circuit 7 are the same as those of the conventional circuit, and hold a peak divided voltage of 1/2 of the signal amplitude Vp as shown in waveform b (FIG. 2A). A voltage dividing circuit 12, which is connected between the amplifier 2 and the reference voltage generating circuit 8 and is made up of resistors 10 and 11, divides the signal a by half as it is to obtain an amplified divided voltage, and has the waveform shown in d. (Figure 2 B). That is, the peak level of the amplified divided voltage d becomes equal to the peak divided voltage b that is the output of the voltage dividing circuit 7. The offset voltage generation circuit 13 connected to the reference voltage generation circuit 8 is a circuit that generates a minute voltage ΔV to ensure that the output of the comparator 9 is "0" when there is no optical signal, as described above. be.
電圧選択回路１５は、その入力に加えられる上
記増幅分圧電圧ｄ、ピーク分圧電圧ｂおよび必要
ならばオフセツト電圧発生回路１３の出力電圧ｃ
の３つの電圧から常に最も高い電圧を選択する機
能を有する。選択回路出力は、その波形ｅに示す
ように立上りが信号ａ入力とほぼ同一時間であ
り、また立下りは示していないが、ピークホール
ド立下り時間に等しく、しかも光信号入力が無い
場合には、微小電圧Δvだけオフセツトを持つよ
うな電圧を発生する（第２図ハ）。即ち、電圧選
択回路１５は、時刻t0までの時間はオフセツト電
圧発生回路１３の出力電圧ｃ、時刻t0〜t1の区間
は信号ａを分圧した増幅分圧電圧ｄ、時刻t1以降
は安定期に入つたピーク分圧電圧ｂを出力する。 The voltage selection circuit 15 selects the amplified divided voltage d, peak divided voltage b, and, if necessary, the output voltage c of the offset voltage generation circuit 13, which is applied to its input.
It has the function of always selecting the highest voltage from the three voltages. As shown in the waveform e, the selection circuit output has a rising time that is almost the same as the signal a input, and although the falling time is not shown, it is equal to the peak hold falling time, and when there is no optical signal input. , generates a voltage offset by a minute voltage Δv (Fig. 2C). That is, the voltage selection circuit 15 uses the output voltage c of the offset voltage generation circuit 13 for the time up to time t0 , the amplified divided voltage d obtained by dividing the signal a during the period from time t0 to t1 , and the amplified divided voltage d obtained by dividing the signal a from time t1 onwards. outputs a peak divided voltage b that has entered a stable period.
上記選択回路１５は、例えば、第３図に示すよ
うにエミツタを共通とする３つのトランジスタ
Q1，Q2，Q3のベースに各々の電圧ｂ，ｄ，ｃを
入力し、定電流源I0によつて、一定の電流を流す
構成のエミツタを出力とする回路によつて実現で
きる。この回路はトランジスタQ1，Q2，Q3のエ
ミツタを共通とするので、ベース電位の高いトラ
ンジスタに電流が流れ、他のトランジスタの電流
が減少する。したがつて、電流が流れるトランジ
スタのエミツタには、ベース電位からVBE低下し
た電圧が得られる。その結果、３つの電圧の中で
常に最高電位からVBEだけ低下した電圧が出力ｅ
として得られる。 The selection circuit 15 includes, for example, three transistors having a common emitter as shown in FIG.
This can be realized by inputting voltages b, d, and c to the bases of Q 1 , Q 2 , and Q 3 , and using a constant current source I 0 to output the emitter configured to flow a constant current. . In this circuit, transistors Q 1 , Q 2 , and Q 3 have a common emitter, so current flows to the transistor with a high base potential, and current in the other transistors decreases. Therefore, a voltage lower than the base potential by V BE is obtained at the emitter of the transistor through which current flows. As a result, among the three voltages, the voltage that is always lower than the highest potential by V BE is the output e.
obtained as.
ところで、このようにして得られた選択回路出
力をしきい電位ｅとして比較回路９の一方の入力
に加えるのであるが、このしきい電位ｅをそのま
ま信号ａと比較したのでは問題がある。共に立上
り時点が同じであるため、立上り時間の遅いしき
い電圧ｅが信号入力以降に設定されてしまうから
である。このため、増幅器２の出力を遅延回路１
６、例えば遅延線等によつて一定時間遅延させた
信号ｆを比較回路９の他方の入力に加える。この
遅延時間は、信号ａの立上り時間よりも小さくて
良いため、50〜100nsというピーク検出回路３の
立上り時間に相当するような大きな値を必要とし
ない。 Incidentally, the selection circuit output obtained in this manner is applied as the threshold potential e to one input of the comparator circuit 9, but there is a problem if this threshold potential e is directly compared with the signal a. This is because the rise time is the same for both, so the threshold voltage e with a slow rise time is set after the signal is input. Therefore, the output of the amplifier 2 is transferred to the delay circuit 1.
6. Apply the signal f delayed for a certain period of time, for example by a delay line, to the other input of the comparator circuit 9. Since this delay time may be smaller than the rise time of the signal a, it does not require a large value of 50 to 100 ns, which corresponds to the rise time of the peak detection circuit 3.
しきい電圧ｅの立上りは、遅延前の信号ａと一
致するから、第２図ハ中に示すように、遅延信号
ｆの立上りが完了する前にしきい電圧ｅが立上り
を完了するような遅延時間Δtとすればよい。即
ち、遅延時間Δtだけしきい電圧ｅが先に立上る
ことになる。このため、最初の信号パルスの立上
り時点においても信号の中心で識別することが可
能となるので、歪のないパルスを比較器９から出
力することができる。 Since the rise of the threshold voltage e coincides with the signal a before the delay, the delay time is such that the threshold voltage e completes its rise before the rise of the delayed signal f is completed, as shown in Fig. 2C. It may be Δt. That is, the threshold voltage e rises first by the delay time Δt. Therefore, since it is possible to identify the center of the signal even at the time of the first rise of the signal pulse, it is possible to output a distortion-free pulse from the comparator 9.
ただし、これとは別に、最初のパルスの立下り
時点における歪の発生を防止するためには、伝送
するパルスの１ビツト相当の時間でピーク検出回
路３の出力が所定の電圧まで上昇していなければ
ならない。しかし、この点については、第１図中
のホールド用コンデンサ４の値を小さくすること
で解決できる。もつとも、これによりホールド時
間も短くなるが、パルスの立上り部は信号を分圧
した増幅分圧電圧ｄによつて識別するので、この
点についても問題はない。逆に、ホールド用コン
デンサの値が小さくて良いため、例えば、IC化
する際にはコンデンサをIC内に作ることが可能
となり、外付け素子を減らせるという利点が生じ
る。 However, in addition to this, in order to prevent distortion from occurring at the falling edge of the first pulse, the output of the peak detection circuit 3 must rise to a predetermined voltage in a time equivalent to one bit of the transmitted pulse. Must be. However, this point can be solved by reducing the value of the hold capacitor 4 in FIG. 1. Of course, this also shortens the hold time, but since the rising edge of the pulse is identified by the amplified divided voltage d obtained by dividing the signal, there is no problem in this respect either. Conversely, since the value of the hold capacitor can be small, for example, when integrated into an IC, the capacitor can be built inside the IC, which has the advantage of reducing the number of external elements.
このように上記実施例によれば、信号入力以前
にしきい値を所定の電圧に設定できるので、歪の
ないパルス再生が可能となり、全体の回路構成も
直流結合であることから原理的にはDC〜
100Mb／ｓ程度にまで帯域を拡げることができ、
パターン依存性もなくIC化に適する。 In this way, according to the above embodiment, the threshold value can be set to a predetermined voltage before signal input, making it possible to reproduce pulses without distortion.Since the entire circuit configuration is also DC coupled, in principle, DC ~
Bandwidth can be expanded to around 100Mb/s,
No pattern dependence and suitable for IC implementation.
［発明の効果］
以上要するに本発明によれば、光信号がない状
態が続いた後に来る最初の信号パルスの受信時で
あつても、信号のピークレベルを先行して検出
し、しきい電圧を信号の中心に設定することがで
きるので、歪のないパルスを再生することがで
き、したがつて伝送帯域の上限をのばすことがで
きる、という優れた効果を発揮する。[Effects of the Invention] In short, according to the present invention, the peak level of the signal is detected in advance and the threshold voltage is set even when the first signal pulse is received after a continuous period of no optical signal. Since it can be set at the center of the signal, distortion-free pulses can be reproduced, and the upper limit of the transmission band can therefore be extended, which is an excellent effect.
第１図は本発明の一実施例に係る光受信回路の
ブロツク図、第２図は第１図のブロツク各部の応
答波形図、第３図は第１図の電圧選択回路の具体
例を示す回路図、第４図は従来の光受信回路例を
示すブロツク図、第５図は第４図のブロツク各部
の応答波形図である。
図中、１は光電変換する受光素子、２は増幅
器、３はピーク検出回路、７はピーク検出回路の
出力を分圧する分圧回路、８は基準電圧発生回
路、９は比較回路、１２は増幅器の出力を分圧す
る分圧回路、１３はオフセツト電圧発生回路、１
５は電圧選択回路、１６は遅延回路、ａは信号、
ｂはピーク分圧電圧、ｃはオフセツト電圧発生回
路の出力、ｄは増幅分圧電圧、ｅは電圧選択回路
出力、ｆは遅延信号である。
FIG. 1 is a block diagram of an optical receiver circuit according to an embodiment of the present invention, FIG. 2 is a response waveform diagram of each part of the block in FIG. 1, and FIG. 3 is a specific example of the voltage selection circuit in FIG. 1. FIG. 4 is a block diagram showing an example of a conventional optical receiver circuit, and FIG. 5 is a response waveform diagram of each part of the block in FIG. 4. In the figure, 1 is a light receiving element that performs photoelectric conversion, 2 is an amplifier, 3 is a peak detection circuit, 7 is a voltage dividing circuit that divides the output of the peak detection circuit, 8 is a reference voltage generation circuit, 9 is a comparison circuit, and 12 is an amplifier 13 is an offset voltage generation circuit, 1
5 is a voltage selection circuit, 16 is a delay circuit, a is a signal,
b is the peak divided voltage, c is the output of the offset voltage generation circuit, d is the amplified divided voltage, e is the output of the voltage selection circuit, and f is the delay signal.
Claims (1)
力と、この増幅器の出力のピークレベルをホール
ドするピーク検出回路の出力とを、光信号のない
ときの上記増幅器出力と等しい電圧を発生する基
準電圧発生回路の出力電圧を基準にしてそれぞれ
分圧回路により分圧し、この分圧して得られた増
幅分圧電圧とピーク分圧電圧とをこれらから高い
方の電圧を選択する電圧選択回路に加え、この電
圧選択回路出力をしきい電圧として比較回路の一
方の入力に加えると共に、比較回路の他方の入力
に上記増幅器の出力を遅延回路を通して加えるこ
とを特徴とする光受信回路。 ２ 光電変換された光信号を増幅する増幅器の出
力と、この増幅器の出力のピークレベルをホール
ドするピーク検出回路の出力とを、光信号のない
ときの上記増幅器出力と等しい電圧を発生する基
準電圧発生回路の出力電圧を基準にしてそれぞれ
分圧回路により増幅分圧電圧とピーク分圧電圧と
に分圧し、さらに上記基準電圧発生回路の出力電
圧をこれに微小のオフセツト電圧を重畳するオフ
セツト電圧発生回路に加え、このオフセツト電圧
発生回路の出力電圧を上記増幅分圧電圧、ピーク
分圧電圧とともにこれら電圧のうち常に高い電圧
を選択する電圧選択回路に加え、この電圧選択回
路出力をしきい電圧として比較回路の一方の入力
に加えると共に、比較回路の他方の入力に上記増
幅器の出力を遅延回路を通して加えることを特徴
とする光受信回路。[Claims] 1. The output of an amplifier that amplifies a photoelectrically converted optical signal and the output of a peak detection circuit that holds the peak level of the output of this amplifier are equal to the output of the amplifier when there is no optical signal. Using the output voltage of the reference voltage generation circuit that generates the voltage as a reference, each voltage is divided by a voltage dividing circuit, and the higher voltage is selected from the amplified divided voltage and the peak divided voltage obtained by dividing the voltage. An optical receiving circuit characterized in that, in addition to a voltage selection circuit, the output of the voltage selection circuit is applied as a threshold voltage to one input of a comparison circuit, and the output of the amplifier is applied to the other input of the comparison circuit through a delay circuit. . 2. The output of the amplifier that amplifies the photoelectrically converted optical signal and the output of the peak detection circuit that holds the peak level of the output of this amplifier are connected to a reference voltage that generates a voltage equal to the output of the amplifier when there is no optical signal. Offset voltage generation is performed by dividing the output voltage of the generating circuit as a reference into an amplified divided voltage and a peak divided voltage using voltage dividing circuits, and then superimposing a minute offset voltage on the output voltage of the reference voltage generating circuit. In addition to the circuit, the output voltage of this offset voltage generation circuit is added to the voltage selection circuit that always selects the higher voltage among these voltages along with the amplified divided voltage and peak divided voltage, and the output of this voltage selection circuit is used as the threshold voltage. An optical receiving circuit characterized in that the output of the amplifier is applied to one input of a comparison circuit, and the output of the amplifier is applied to the other input of the comparison circuit through a delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60292852A JPS62154928A (en) | 1985-12-27 | 1985-12-27 | Optical reception circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60292852A JPS62154928A (en) | 1985-12-27 | 1985-12-27 | Optical reception circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62154928A JPS62154928A (en) | 1987-07-09 |
| JPH0547010B2 true JPH0547010B2 (en) | 1993-07-15 |
Family
ID=17787200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60292852A Granted JPS62154928A (en) | 1985-12-27 | 1985-12-27 | Optical reception circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62154928A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0775356B2 (en) * | 1991-06-05 | 1995-08-09 | 株式会社東芝 | Optical receiver |
| US6373045B1 (en) * | 1999-06-29 | 2002-04-16 | Infineon Technologies North America Corp. | High speed optocoupler detector |
| US7541845B2 (en) | 2001-08-31 | 2009-06-02 | Samsung Electronics Co., Ltd. | Signal receiver apparatus and method for detecting logic state represented by an input signal and semiconductor integrated circuit device having the same |
| WO2006129349A1 (en) * | 2005-05-31 | 2006-12-07 | Fujitsu Limited | Data receiver apparatus |
| JP5407815B2 (en) * | 2009-12-02 | 2014-02-05 | 株式会社デンソー | Reception processing device and communication device |
-
1985
- 1985-12-27 JP JP60292852A patent/JPS62154928A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62154928A (en) | 1987-07-09 |
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