JPH05326729A - Wiring structural body for semiconductor device and manufacturing method thereof - Google Patents
Wiring structural body for semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH05326729A JPH05326729A JP13043592A JP13043592A JPH05326729A JP H05326729 A JPH05326729 A JP H05326729A JP 13043592 A JP13043592 A JP 13043592A JP 13043592 A JP13043592 A JP 13043592A JP H05326729 A JPH05326729 A JP H05326729A
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- Prior art keywords
- wiring
- wiring structure
- semiconductor device
- organic film
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置用の配線構
造体において、特に、多層配線された配線構造体に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure for a semiconductor device, and more particularly to a wiring structure having multi-layer wiring.
【０００２】[0002]
【従来の技術】半導体装置、特に半導体集積回路におい
ては、高集積化・高速化のため活発な研究開発が進めら
れている。そのためにトランジスタ等の能動素子の微細
化及び高速化と共に、電気信号の伝送及び給電・接地の
為に用いられる配線構造体の微細化・低損失化及び高信
頼化も重要である。2. Description of the Related Art Active research and development is underway for semiconductor devices, particularly semiconductor integrated circuits, in order to achieve higher integration and higher speed. Therefore, it is important to miniaturize and speed up active elements such as transistors, and to miniaturize, reduce loss, and improve reliability of a wiring structure used for transmission of electric signals and feeding / grounding.
【０００３】このような配線構造体は、集積回路の回路
構成が複雑になるに伴い、通常二層以上の導体膜パター
ンを用いて形成される。即ち、先ず第一層の導体膜に所
要のパターニングを施して電極あるいは配線パターンの
第１層を形成し、その上に層間絶縁膜（例えば、二酸化
シリコン，窒化シリコン等）を形成する。次いで第二層
の導体膜を設け、所要のパターニングを施して第二層目
の配線構造体が形成される。Such a wiring structure is usually formed by using conductor film patterns of two or more layers as the circuit structure of the integrated circuit becomes complicated. That is, first, required patterning is applied to the conductor film of the first layer to form a first layer of electrodes or wiring patterns, and an interlayer insulating film (eg, silicon dioxide, silicon nitride, etc.) is formed thereon. Next, a second-layer conductor film is provided, and required patterning is performed to form a second-layer wiring structure.
【０００４】[0004]
【発明が解決しようとする課題】このような従来の配線
構造体においては、多層配線間の交叉領域に生ずる容量
のため、信号の減衰，クロストークが生じていた。これ
に対する対策として、交叉領域の面積を小さくするた
め、配線の幅を小さくし配線容量を減ずる方法が採られ
ている。しかし配線の幅を小さくすることは、一方で配
線抵抗の増加をもたらし、信号用配線においては伝送さ
れる信号の減衰を、給電用配線においては電圧降下を、
接地用配線においては接地電位の変動を生じさせてい
た。また、配線抵抗の増加を避けるため、配線の厚みを
大きくし、高アスペクト比の配線を形成する方法も採ら
れている。しかし高アスペクト比の配線を形成すると、
この上層に形成される配線が大きな段差部を乗り越える
ことになり、この段差部における上層配線の断線、ある
いは電界集中による層間絶縁膜の破壊等が生じていた。In such a conventional wiring structure, signal attenuation and crosstalk occur due to the capacitance generated in the intersection region between the multilayer wirings. As a countermeasure against this, in order to reduce the area of the crossover region, a method of reducing the width of the wiring and reducing the wiring capacitance is adopted. However, reducing the width of the wiring brings about an increase in wiring resistance on the other hand, attenuation of the transmitted signal in the signal wiring and voltage drop in the power feeding wiring.
In the ground wiring, the ground potential fluctuates. Further, in order to avoid an increase in wiring resistance, a method of increasing the thickness of the wiring and forming a wiring with a high aspect ratio is also adopted. However, when wiring with a high aspect ratio is formed,
The wiring formed in the upper layer crosses over a large step portion, and the upper layer wiring is broken in the step portion, or the interlayer insulating film is broken due to electric field concentration.
【０００５】一方、このような配線構造体の製造方法に
おいては、第１層の電極・配線等により、その上に形成
された層間絶縁膜に段差を生じ、第２層の配線パターン
を形成する際に、段差の側面に付着した金属膜の除去が
困難で、第２層の配線パターン間の短絡が生じ易くなっ
ていた。On the other hand, in the method for manufacturing such a wiring structure, a step is formed in the interlayer insulating film formed thereon due to the electrodes and wirings of the first layer to form the wiring pattern of the second layer. At this time, it was difficult to remove the metal film attached to the side surface of the step, and a short circuit between the wiring patterns of the second layer was likely to occur.
【０００６】以上述べた、配線間の短絡及び断線を回避
するため、基体上に生じた凹凸を、バイアススパッタ法
により平坦化する方法や、燐珪酸ガラス等の無機質ある
いはポリイミド等の樹脂膜をコーティングして、これに
高温熱処理を施して、表面を平坦化する方法が従来実施
されている。In order to avoid the above-mentioned short circuit and disconnection between the wirings, the unevenness formed on the substrate is flattened by the bias sputtering method, or an inorganic material such as phosphosilicate glass or a resin film such as polyimide is coated. Then, a method of subjecting this to high temperature heat treatment to flatten the surface has been conventionally practiced.
【０００７】これら既に知られている平坦化方法は、高
温熱処理を伴うため、高温熱処理に比較的耐えうるシリ
コン半導体には容易に適用できるが、ガリウム砒素（Ｇ
ａＡｓ）等の化合物半導体を用いた半導体の製造工程に
おいては、４００℃以上の高温熱処理を長時間施すこと
は、結晶の劣化，電極材の劣化をもたらすため適用困難
である。Since these already known planarization methods involve high temperature heat treatment, they can be easily applied to silicon semiconductors that can withstand high temperature heat treatment, but gallium arsenide (G
In a semiconductor manufacturing process using a compound semiconductor such as aAs), it is difficult to apply high-temperature heat treatment at 400 ° C. or higher for a long time because it causes crystal deterioration and electrode material deterioration.
【０００８】本発明の目的は、上記のような問題点を解
決し、配線容量及び配線抵抗の低減を図れる配線構造
体、および配線間の短絡、凹凸部における断線を回避で
きる極めて簡単なプロセスによる配線構造体の製造方法
を提供することにある。An object of the present invention is to solve the above problems and to provide a wiring structure capable of reducing the wiring capacitance and wiring resistance, and an extremely simple process capable of avoiding short circuit between wirings and disconnection at uneven portions. It is to provide a method for manufacturing a wiring structure.
【０００９】[0009]
【課題を解決するための手段】本発明は、半導体装置の
基板上に形成された２層以上から成る配線構造体におい
て、下層の配線構造体と、この上に設けられた上層の配
線構造体とが交叉する領域における前記下層配線構造体
の側面と対抗する前記上層配線構造体との間に、空隙あ
るいは有機膜支持体が設けられていることを特徴とす
る。According to the present invention, in a wiring structure formed of two or more layers on a substrate of a semiconductor device, a lower wiring structure and an upper wiring structure provided thereon. A void or an organic film support is provided between the side surface of the lower layer wiring structure and the upper layer wiring structure facing the side surface of the lower layer wiring structure in the region where and intersect.
【００１０】また本発明の半導体装置用配線構造体の製
造方法は、凹凸を有する半導体装置の基体の主面上に、
この凹凸を横切る所定の開口パターンを有する有機樹脂
膜を形成する工程と、前記有機樹脂膜を加熱し流動させ
ることにより前記凹凸の側面に選択的に前記有機樹脂膜
を残置することで有機膜支持体を形成する工程と、少な
くとも前記有機膜支持体を含む領域上に配線構造体を形
成する工程とを含むことを特徴とする。The method of manufacturing a wiring structure for a semiconductor device according to the present invention comprises:
A step of forming an organic resin film having a predetermined opening pattern that crosses the unevenness, and heating and flowing the organic resin film to selectively leave the organic resin film on the side surface of the unevenness to support the organic film. The method is characterized by including a step of forming a body and a step of forming a wiring structure on a region including at least the organic film support.
【００１１】また本発明の半導体装置用配線構造体の製
造方法は、凹凸を有する半導体装置の基体の主面上に、
フォトレジストを塗布し、少なくとも平坦面上の前記フ
ォトレジストを露光現像し、前記凹凸の側面のみに前記
フォトレジストを残置させる工程と、前記フォトレジス
トを加熱硬化させることにより有機膜支持体を形成する
工程と、少なくとも前記有機膜支持体を含む領域上に配
線構造体を形成する工程とを含むことを特徴とする。Further, according to the method of manufacturing a wiring structure for a semiconductor device of the present invention, on the main surface of the substrate of the semiconductor device having irregularities,
Forming an organic film support by applying a photoresist, exposing and developing the photoresist on at least a flat surface, and leaving the photoresist only on the side surfaces of the unevenness; and by heat-curing the photoresist. And a step of forming a wiring structure on a region including at least the organic film support.
【００１２】[0012]
【作用】本発明における配線構造体においては、下層の
配線と交叉する領域で段差部の側面と上層の配線とが直
接接することがなく、なだらかなテーパ状となっている
ため、上下層間の配線容量を減少させることが出来ると
ともに、段差部のエッジにおける電界集中も緩和され、
層間絶縁膜の破壊を回避することが出来る。又、その製
造に際しては上層の金属膜のエッチングすべき領域が有
機膜上に形成されているので、基体の段差部の側面に直
接金属膜が付着するのを防いでいる。又、この有機膜は
基体の凹凸を滑らかにしているので、有機膜上の金属膜
の除去が容易である。従って配線間の短絡を防止でき
る。In the wiring structure of the present invention, since the side surface of the step portion and the upper layer wiring are not in direct contact with each other in the region intersecting with the lower layer wiring, the wiring between the upper and lower layers is formed. The capacitance can be reduced, and the electric field concentration at the edge of the step can be alleviated.
It is possible to avoid destruction of the interlayer insulating film. In addition, since the region of the upper metal film to be etched is formed on the organic film in the production thereof, the metal film is prevented from directly adhering to the side surface of the stepped portion of the substrate. Further, since this organic film smoothes the unevenness of the substrate, the metal film on the organic film can be easily removed. Therefore, a short circuit between wirings can be prevented.
【００１３】[0013]
【実施例】以下本発明の実施例について図面を参照しな
がら説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１４】図１に、本発明による半導体装置の配線構
造体を、更に図２（ａ），（ｂ）および（ｃ）に、その
製造方法の第１の実施例を示す。各図面の右側は平面
図、左側には、平面図におけるＡＡ′線断面図を示して
いる。FIG. 1 shows a wiring structure of a semiconductor device according to the present invention, and FIGS. 2A, 2B and 2C show a first embodiment of a manufacturing method thereof. The right side of each drawing shows a plan view, and the left side shows a sectional view taken along the line AA 'in the plan view.
【００１５】先ず、図２（ａ）において、ＧａＡｓ等の
半導体基板１上に第１層配線２、及びＳｉＯ2 等から成
る層間絶縁膜３が形成された基体上に、この基体の凹凸
を横切る所定の開口パターンを有するフォトレジストパ
ターン４を形成する。次いで図２（ｂ）に示すように、
この基体を１００℃〜２００℃程度の高温処理を施すこ
とで、フォトレジストを流動化させ、毛管現象により、
基体の段差部分のみにフォトレジストを選択的に広げる
ことで、有機膜支持体４ｂを形成する。この時、基体上
の段差部の側面は、有機膜支持体４ｂにより滑らかに被
覆される。有機膜支持体４ｂの広がり程度は、フォトレ
ジストパターン４の厚み及び初期の開口幅、更には高温
処理条件により抑制される。次に図２（ｃ）に示すよう
に、少なくとも有機膜支持体４ｂを覆う位置に第２層配
線５を形成する。最後に、フォトレジストパターン４及
び有機膜支持体４ｂを酸素プラズマによるアッシング法
により除去する。以上の工程により図１に示す配線構造
体が完成する。４ａは、有機膜支持体４ｂが除去された
結果できた空隙である。First, as shown in FIG. 2A, the unevenness of the substrate is traversed on the substrate in which the first layer wiring 2 and the interlayer insulating film 3 made of SiO 2 are formed on the semiconductor substrate 1 such as GaAs. A photoresist pattern 4 having a predetermined opening pattern is formed. Then, as shown in FIG.
By subjecting this substrate to a high temperature treatment of about 100 ° C. to 200 ° C., the photoresist is fluidized, and by the capillary phenomenon,
The organic film support 4b is formed by selectively spreading the photoresist only on the stepped portion of the substrate. At this time, the side surface of the stepped portion on the substrate is smoothly covered with the organic film support 4b. The extent of spread of the organic film support 4b is suppressed by the thickness of the photoresist pattern 4, the initial opening width, and the high temperature processing conditions. Next, as shown in FIG. 2C, the second layer wiring 5 is formed at a position that covers at least the organic film support 4b. Finally, the photoresist pattern 4 and the organic film support 4b are removed by an ashing method using oxygen plasma. Through the above steps, the wiring structure shown in FIG. 1 is completed. 4a is a void formed as a result of removing the organic film support 4b.
【００１６】図３に本発明の第２の製造方法の一実施例
を示す。FIG. 3 shows an embodiment of the second manufacturing method of the present invention.
【００１７】先ず、図３（ａ）において、ＧａＡｓ等の
半導体基板１上に第１層配線２、及びＳｉＯ2 等から成
る層間絶縁膜３が形成された基体上に、この基体の凹凸
を覆うフォトレジスト４を塗布する。次いで図３（ｂ）
に示すように、このフォトレジストの平坦部の厚みを感
光するに必要な光量及び時間でもって、フォトレジスト
の全面を露光し、現像する。この時、凹凸の段差部にお
けるフォトレジストは平坦面より厚くなっているので、
部分的に感光せず、残置する。この段差部の側面に残さ
れたフォトレジストを１００℃〜２００℃程度の高温処
理を施すことで、硬化させ有機膜支持体４ｂを形成す
る。次に図３（ｃ）に示すように、少なくとも有機膜支
持体４ｂを覆う位置に第２層配線５を形成する。最後
に、有機膜支持体４ｂを酸素プラズマによるアッシング
法により除去する。以上の工程により図１に示す配線構
造体が完成する。First, in FIG. 3 (a), the unevenness of the substrate is covered on the substrate in which the first layer wiring 2 and the interlayer insulating film 3 made of SiO 2 are formed on the semiconductor substrate 1 such as GaAs. Photoresist 4 is applied. Next, FIG. 3 (b)
As shown in, the entire surface of the photoresist is exposed and developed with the amount of light and the time required to expose the thickness of the flat portion of the photoresist. At this time, since the photoresist in the step portion of the unevenness is thicker than the flat surface,
Partially unexposed and left. By subjecting the photoresist left on the side surface of the step portion to a high temperature treatment of about 100 to 200 ° C., the photoresist is cured to form the organic film support 4b. Next, as shown in FIG. 3C, the second layer wiring 5 is formed at a position that covers at least the organic film support 4b. Finally, the organic film support 4b is removed by an ashing method using oxygen plasma. Through the above steps, the wiring structure shown in FIG. 1 is completed.
【００１８】図２及び図３の製造工程では、有機膜支持
体を最終工程で除去して、第１層配線の側面と第２層配
線間が空隙となる方法を示したが、有機膜支持体をその
まま残置してもよい。この場合、有機膜支持体の誘電率
に対応して第１層・第２層間の配線容量が増加するが、
第２層配線の機械的強度が増加する特徴がある。In the manufacturing process of FIGS. 2 and 3, the method of removing the organic film support in the final step to form a gap between the side surface of the first layer wiring and the second layer wiring is shown. You may leave the body as it is. In this case, the wiring capacitance between the first and second layers increases in accordance with the dielectric constant of the organic film support,
There is a feature that the mechanical strength of the second layer wiring increases.
【００１９】[0019]
【発明の効果】以上説明したように、本発明における配
線構造体は、上層の配線が、下層の配線と交叉する領域
で、下層配線の側面と上層の配線とが直接対向すること
がなく、なだらかなテーパ状となっているため、上下層
間の配線容量を減少させることができるとともに、段差
部のエッヂにおける電界集中も緩和され、層間絶縁膜の
破壊を回避することができる。又、その製造に際して
は、上層の配線となる金属膜のエッチングすべき領域が
有機膜上に形成されているので基体の段差部の側面に直
接金属膜が付着するのを防いでいる。又、この有機膜は
基体の凹凸を滑らかにしているので、有機膜上の金属膜
の除去が容易である。従って配線間の短絡を防止でき
る。As described above, in the wiring structure of the present invention, the side surface of the lower layer wiring and the upper layer wiring do not directly face each other in the region where the upper layer wiring intersects the lower layer wiring, Since the taper has a gentle taper, the wiring capacitance between the upper and lower layers can be reduced, and the electric field concentration at the edge of the step portion can be alleviated to prevent the interlayer insulating film from being destroyed. Further, in the manufacturing thereof, since the region of the metal film to be the upper wiring to be etched is formed on the organic film, the metal film is prevented from directly adhering to the side surface of the stepped portion of the substrate. Further, since this organic film smoothes the unevenness of the substrate, the metal film on the organic film can be easily removed. Therefore, a short circuit between wirings can be prevented.
【００２０】従って、本発明によれば、化合物半導体に
適用不可能な高温処理を用いることなく、配線構造体の
高性能化，高信頼化、及び高歩留化が図れる。Therefore, according to the present invention, high performance, high reliability and high yield of the wiring structure can be achieved without using high temperature treatment which is not applicable to compound semiconductors.
【図１】本発明の半導体用配線構造体の一実施例を示す
断面図である。FIG. 1 is a cross-sectional view showing an embodiment of a wiring structure for a semiconductor of the present invention.
【図２】本発明の半導体用配線構造体の他の製造方法の
一実施例を示す工程断面図である。FIG. 2 is a process cross-sectional view showing an embodiment of another method for manufacturing a semiconductor wiring structure of the present invention.
【図３】本発明の半導体用配線構造体の製造方法の一実
施例を示す工程断面図である。FIG. 3 is a process sectional view showing an example of the method for manufacturing a semiconductor wiring structure of the present invention.
１ 基板 ２ 第１層配線 ３ 層間絶縁膜 ４ フォトレジスト ４ａ 空隙 ４ｂ 有機膜支持体 ５ 第２層配線 1 Substrate 2 First Layer Wiring 3 Interlayer Insulating Film 4 Photoresist 4a Void 4b Organic Film Support 5 Second Layer Wiring
Claims (4)
から成る配線構造体において、 下層の配線構造体と、この上に設けられた上層の配線構
造体とが交叉する領域における前記下層配線構造体の側
面と対抗する前記上層配線構造体との間に、空隙あるい
は有機膜支持体が設けられていることを特徴とする半導
体装置用配線構造体。1. A wiring structure comprising two or more layers formed on a substrate of a semiconductor device, wherein the lower layer in a region where a lower wiring structure and an upper wiring structure provided thereover intersect. A wiring structure for a semiconductor device, characterized in that a space or an organic film support is provided between the side surface of the wiring structure and the upper wiring structure facing the side surface.
に、この凹凸を横切る所定の開口パターンを有する有機
樹脂膜を形成する工程と、 前記有機樹脂膜を加熱し流動させることにより前記凹凸
の側面に選択的に前記有機樹脂膜を残置することで有機
膜支持体を形成する工程と、 少なくとも前記有機膜支持体を含む領域上に配線構造体
を形成する工程とを含むことを特徴とする半導体装置用
配線構造体の製造方法。2. A step of forming an organic resin film having a predetermined opening pattern across the unevenness on the main surface of a base of a semiconductor device having the unevenness, and the unevenness by heating and flowing the organic resin film. A step of forming an organic film support by selectively leaving the organic resin film on a side surface of the substrate, and a step of forming a wiring structure on a region including at least the organic film support. Method for manufacturing wiring structure for semiconductor device.
特徴とする請求項２記載の半導体装置用配線構造体の製
造方法。3. The method for manufacturing a wiring structure for a semiconductor device according to claim 2, wherein the organic resin film is a photoresist.
に、フォトレジストを塗布し、少なくとも平坦面上の前
記フォトレジストを露光現像し、前記凹凸の側面のみに
前記フォトレジストを残置させる工程と、 前記フォトレジストを加熱硬化させることにより有機膜
支持体を形成する工程と、 少なくとも前記有機膜支持体を含む領域上に配線構造体
を形成する工程とを含むことを特徴とする半導体装置用
配線構造体の製造方法。4. A step of coating a photoresist on a main surface of a substrate of a semiconductor device having unevenness, exposing and developing the photoresist on at least a flat surface, and leaving the photoresist left only on the side surface of the unevenness. And a step of forming an organic film support by heating and curing the photoresist, and a step of forming a wiring structure on a region including at least the organic film support. A method for manufacturing a wiring structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4130435A JP3064664B2 (en) | 1992-05-22 | 1992-05-22 | Method of manufacturing wiring structure for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4130435A JP3064664B2 (en) | 1992-05-22 | 1992-05-22 | Method of manufacturing wiring structure for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05326729A true JPH05326729A (en) | 1993-12-10 |
| JP3064664B2 JP3064664B2 (en) | 2000-07-12 |
Family
ID=15034170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4130435A Expired - Fee Related JP3064664B2 (en) | 1992-05-22 | 1992-05-22 | Method of manufacturing wiring structure for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3064664B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6064118A (en) * | 1997-04-18 | 2000-05-16 | Nec Corporation | Multilevel interconnection structure having an air gap between interconnects |
-
1992
- 1992-05-22 JP JP4130435A patent/JP3064664B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6064118A (en) * | 1997-04-18 | 2000-05-16 | Nec Corporation | Multilevel interconnection structure having an air gap between interconnects |
| US6368939B1 (en) * | 1997-04-18 | 2002-04-09 | Nec Corporation | Multilevel interconnection structure having an air gap between interconnects |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3064664B2 (en) | 2000-07-12 |
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