KR100265991B1 - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device Download PDF

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Publication number
KR100265991B1
KR100265991B1 KR1019930026870A KR930026870A KR100265991B1 KR 100265991 B1 KR100265991 B1 KR 100265991B1 KR 1019930026870 A KR1019930026870 A KR 1019930026870A KR 930026870 A KR930026870 A KR 930026870A KR 100265991 B1 KR100265991 B1 KR 100265991B1
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South Korea
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layer
protrusion
conductive layer
metal wiring
wiring layer
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KR1019930026870A
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Korean (ko)
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KR950021414A (en
Inventor
심재광
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides

Abstract

PURPOSE: A method for connecting multi-layer interconnections in a semiconductor device is to prevent deposition defects of interconnection materials, thereby improving a connection characteristic of the interconnections and obtaining a high degree of integration. CONSTITUTION: The first conductive layer is formed on a semiconductor substrate(20). A portion of the first conductive layer is etched to a predetermined thickness to form the first metal interconnection layer(201a) containing a protrusion(201b). An insulating layer(22') is formed on the first metal interconnection layer to cover the protrusion. The insulating layer is etched and planarized until a surface of the protrusion is exposed. The second conductive layer is formed on the planarized insulating layer to cover the protrusion. The conductive layer is etched to form the second metal interconnection layer(202') connected to the protrusion.

Description

반도체 장치의 다층 배선간 연결공정Connecting process between multilayer wirings of semiconductor device

제1도는 종래 기술에 따른 반도체 장치의 다층 배선간 연결공정을 나타낸 것이다.1 is a view illustrating a connection process between multilayer wirings of a semiconductor device according to the prior art.

제2도는 본 발명에 따른 반도체 장치의 다층 배선간 연결공정을 나타낸 것이다.2 is a diagram illustrating a process for connecting multilayer wirings in a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10,20 : 실리콘 기판 11,21,12,22 : 절연막10,20 silicon substrate 11,21,12,22 insulating film

101,102,201,202,102',201a,201b : 금속 a : 두께101,102,201,202,102 ', 201a, 201b: Metal a: Thickness

본 발명은 반도체 소자 제조공정중 다층 배선공정시 이들 배선간의 연결공정에 관한 것으로서, 특히 콘택홀에서의 배선물질의 증착문제를 해결하기 위하여 하층배선 콘택부위에 돌출부를 형성하여 이로부터 상층배선으로 연결하게하는 반도체 장치의 다층 배선간 연결공정에 관한 것이다.The present invention relates to a connection process between these wirings during the multi-layer wiring process of the semiconductor device manufacturing process. In particular, in order to solve the problem of deposition of wiring material in the contact hole, a protrusion is formed on the lower wiring contact portion and connected to the upper wiring. It relates to a multi-layer interconnection process of the semiconductor device.

종래 반도체 장치의 다층배선간 연결공정 제1도에 도시되어 있다.A connection process between the multilayer wirings of a conventional semiconductor device is shown in FIG.

먼저 a도와 같이, 실리콘 기판(10)위에 층간 절연을 위한 제1산화막(11)을 증착한 다음 그 위에 일차 금속배선층(101)을 증착한다.First, as shown in a, the first oxide film 11 for interlayer insulation is deposited on the silicon substrate 10, and then the primary metal wiring layer 101 is deposited thereon.

그리고 b도와 같이 일차 금속배선층(100)위에 배선간 절연을 위한 제2산화막(12)을 증착한다.Then, as shown in b, a second oxide film 12 for inter-wire insulation is deposited on the primary metal wiring layer 100.

그다음 c도와 같이 콘택홀을 형성하기 위해 제2산화막(12)이에 포토레지스트(111)를 도포한다.Then, the photoresist 111 is applied to the second oxide film 12 to form a contact hole as shown in FIG.

이어 d도와 같이 콘택홀 형성용 마스크를 이용한 노광 및 현상으로 일차 포토레지스트 패턴(111')을 정의한다.Next, as shown in d, the primary photoresist pattern 111 ′ is defined by exposure and development using a contact hole forming mask.

그리고 e도와 같이 비등방성 식각을 실시하여 포토 레지스트 패턴(111')으로 보호되지 안흔 부위의 제2산화막(12)을 제거하므로써 일차 금속배선층(101)의 콘택부위를 개방시켜 콘택홀을 형성한다.Then, anisotropic etching is performed as shown in e to remove the second oxide film 12 in the unmarked portion, which is not protected by the photoresist pattern 111 ', thereby opening the contact portion of the primary metal wiring layer 101 to form a contact hole.

이어 f도와 같이 포토레지스터 패턴(111')을 제거한다.Subsequently, the photoresist pattern 111 'is removed as shown in FIG.

상기 공정 후 (G)도와 같이 잔류하는 제2산화막(12')표면 및 측면 그리고 노출된 일차 금속배선층(101)표면에 이차 금속배선층(102)을 증착한다.After the process, the secondary metal wiring layer 102 is deposited on the remaining surface and side surfaces of the second oxide film 12 ′ and the exposed surface of the primary metal wiring layer 101 as shown in (G).

이때 증착되는 이차 금속배선층(102)은 특히 노출된 제2산화막(12')의 측면과 노출된 일차 금속배선층(101)표면이 만나는 모서리 부분에서 그림자 효과(shadow effect)로 인하여 그 피복성이 매우 열약하게 된다.In this case, the deposited secondary metal wiring layer 102 has a very high coating property due to a shadow effect at the corner portion where the side surface of the exposed second oxide film 12 ′ and the exposed surface of the primary metal wiring layer 101 meet. You become weak.

이어 (H)도와 같이 이차 금속 배선층(102)의 패턴을 정의하기 위하여 포토레지스트를 도포한 후 이차금속배선층 형성용 마스크를 이용한 노광 및 현상으로 이차 포토레지스트 패턴(112)을 정의한다.Next, as shown in (H), the photoresist is applied to define the pattern of the secondary metal wiring layer 102, and then the secondary photoresist pattern 112 is defined by exposure and development using a mask for forming the secondary metal wiring layer.

이때 마스크는 그 폭이 일차 포토레지스트 패턴(111')형성용 마스크보다 a만큼 큰 것을 사용하는데 이는 이차 금속배선층의 연결성 마진을 확보하기 위해서이다.In this case, the width of the mask is larger than that of the mask for forming the primary photoresist pattern 111 ′, in order to secure the connection margin of the secondary metal wiring layer.

그러나 이러한 증가는 소자의 집적도 향상에 방해가 된다.This increase, however, hinders device integration.

그 다음 (Ⅰ)도와 같이 이차 포토레지스트 패턴(112)으로 보호되지 않는 부위의 이차 금속 배선층을 식각하여 이차 금속배선 패턴(102')을 정의한다.Next, as shown in (I), the secondary metal interconnection layer 102 ′ is defined by etching the secondary metal interconnection layer in a portion not protected by the secondary photoresist pattern 112.

이후 (J)도와 같이 이차 포토레지스트 패턴을 제거하여 반도체 장치의 다층배선간 연결공정을 완료한다.Thereafter, as shown in (J), the secondary photoresist pattern is removed to complete the connection process between the multilayer wirings of the semiconductor device.

이때 형성된 이차 금속배선 패턴(102')은 마친 확보를 위해 a만큼 크기가 증가된다.In this case, the formed secondary metal wiring pattern 102 ′ is increased in size by a to ensure completion.

위에서 설명한 바와 같이 종래의 다층배선간 연결공증은 콘택홀 내의 금속배선층 증착상태가 열악하게 되어 연결불량을 유발시킬 수 있으며, 또한 서로 다른 금속배선층간의 연결성을 개선시키기 위하여 여분의 마진확보가 필요하며 이는 반도체 소자의 집적도를 저하시키는 요인이 된다.As described above, the conventional notarization between the multi-layered wirings may cause poor connection due to the poor deposition state of the metallization layer in the contact hole, and also requires extra margin to improve the connectivity between the different metallization layers. It becomes a factor which reduces the integration degree of a semiconductor element.

본 발명은 상기와 같은 문제점을 해결하기 위하여 개선된 반도체 장치의 다층배선간 연결공정을 제공하며, 이는 (가) 반도체 기판위에 제1절연막을 형성하는 단계와, (나) 제1절연막 위에 제1도전층을 형성하는 단계와, (다) 상기 제1도전층으로 된 1차배선을 형성하고, 1차배선위의 콘택 부위를 제외한 부위의 소정두께를 제거하는 단계와, (라) 상기 제1도전층의 콘택부위 측면과 잔류하는 상기 제1도전층의 표면에 제2절연막을 형성하는 단계와, (마) 상기 제1도전층의 콘택부위 표면 및 상기 제2절연막 표면에 제2도전층을 형성하는 단계와, (바) 상기 제2도전층을 패터닝 및 식각하여 2차배선을 형성하는 단계로 이루어진다.The present invention provides an improved inter-layer interconnection process of a semiconductor device in order to solve the above problems, which includes (a) forming a first insulating film on a semiconductor substrate, and (b) a first insulating film on a first insulating film. Forming a conductive layer, (c) forming a primary wiring of the first conductive layer, removing a predetermined thickness of a portion except for a contact portion on the primary wiring, and (d) the first Forming a second insulating film on the side of the contact portion of the conductive layer and the surface of the first conductive layer remaining; and (e) forming a second conductive layer on the contact portion surface of the first conductive layer and the surface of the second insulating layer. Forming a second wiring by patterning and etching the second conductive layer.

제2도는 본 발명에 따른 반도체 장치의 다층 배선간 공정을 나타낸 것이다.2 shows a multi-layer interconnection process of a semiconductor device according to the present invention.

먼저 a도와 같이 실리콘 기판(20)위에 층간절연을 위한 제1절연막(21)으로 산화막을 형성한 다음 제1금속배선층(201)은 제1절연막(21)위에 증착한다.First, an oxide film is formed on the silicon substrate 20 as the first insulating film 21 for interlayer insulation, as shown in a. Then, the first metal wiring layer 201 is deposited on the first insulating film 21.

그리고 b도와 같이 제1금속배선층(201)의 소정부분을 제거하기 위하여 포토레지스트(211)를 제1금속배선층(201)위에 도포한다.As shown in b, a photoresist 211 is applied on the first metal wiring layer 201 to remove a predetermined portion of the first metal wiring layer 201.

그 다음 c도와 같이 이후 상층에 형성될 제2금속 배선층과의 연결을 위한 제1금속 배선층(201)의 돌출부를 형성하기 위하여 콘택 부위형성용 마스크를 이용한 노광 및 현상으로 제1포토레지스트 패턴(211')을 정의한다.Next, as shown in c, the first photoresist pattern 211 is exposed and developed using a contact forming mask to form a protrusion of the first metal wiring layer 201 for connection with the second metal wiring layer to be formed on the upper layer. Define ').

상기 공정 후 d도와 같이 전면에 시간제어식각(time control etch)실시하여 제1포토레지스트 패턴(211')으로 부터 보호되지 않는 부위의 제1금속배선층(201)의 소정두께를 제거한다.After the process, a time control etch is performed on the entire surface as shown in d to remove a predetermined thickness of the first metal wiring layer 201 at the portion not protected from the first photoresist pattern 211 ′.

이때 제1금속 배선층은 제1포토레지스트 패턴(211')으로 보호된 부위는 돌출부(201b)가 되고 그 나머지 부위는 소정두께가 제거된 형태의 잔류된 제1금속배선층(201a)이 된다.In this case, the portion of the first metal wiring layer protected by the first photoresist pattern 211 ′ becomes the protruding portion 201b, and the remaining portion of the first metal wiring layer becomes the remaining first metal wiring layer 201a having a predetermined thickness removed.

이후 제1포토레지스트 패턴(211')을 제거한다.Thereafter, the first photoresist pattern 211 ′ is removed.

이어 e도와 같이 돌출부(201b)의 표면 측면 그리고 잔류된 제1금속배선층(201a)표면에 제2절연막(22)으로 산화막을 증착한 다음 이를 평탄화시킨다.Subsequently, an oxide film is deposited on the surface side of the protrusion 201b and the remaining surface of the first metal wiring layer 201a as the second insulating layer 22, and then planarized.

그리고 f도와 같이 돌출부(201b)의 표면이 노출될 때까지 제2절연막을 식각하여 잔류된 제2절연막(22')을 형성한다. 이때 잔류된 제2절연막(22')의 높이는 돌출부(201b)의 높이보다 높아서는 안된다.The second insulating layer 22 is etched until the surface of the protrusion 201b is exposed as shown in FIG. F to form the second insulating layer 22 ′ remaining. At this time, the height of the remaining second insulating film 22 'should not be higher than the height of the protrusion 201b.

그다음 g도와 같이 제1금속 배선층의 돌출부(201b)표면과 잔류된 제2절연막(22')표면에 제2금속배선층(202)을 증착한다.Next, as shown in FIG. 7, the second metal wiring layer 202 is deposited on the surface of the protruding portion 201b of the first metal wiring layer and the surface of the remaining second insulating film 22 ′.

이어 h도와 같이 제2금속배선층(202)위에 포토레지스트를 도호한 다음 제2금속배선층(202)패턴 정의용 마스크를 이용한 노광 및 현상으로 제2포토레지스트 패턴(212)을 정의한다.Subsequently, the photoresist is applied on the second metal wiring layer 202 as shown in the diagram h, and the second photoresist pattern 212 is defined by exposure and development using a mask for defining the pattern of the second metal wiring layer 202.

이후 (자)도와 같이 제2포토레지스트 패턴(212)을 이용하여 이로부터 보호되지 않는 부위의 제2금속배선층을 제거하여 원하는 제2금속 배선층 패턴(202')을 형성하므로써 반도체 장치의 다층배선간 연결공정이 완료된다.Thereafter, as shown in (i), the second metal wiring layer of the unprotected portion is removed by using the second photoresist pattern 212 to form the desired second metal wiring layer pattern 202 ′ between the multilayer wirings of the semiconductor device. The connection process is complete.

이때 형성된 제2금속배선층 패턴(202')의 폭은 거의 제1금속배선층의 돌출부(201b)와 같게된다.In this case, the width of the formed second metal wiring layer pattern 202 ′ is substantially equal to the protrusion 201b of the first metal wiring layer.

이상에서 상술한 바와 같이 본 발명은 반도체 장치의 다층 배선간 연결공정으로 특히 다층 금속배선간의 연결공정에 있어서, 종래의 콘택홀을 이용하지 않으므로써 콘택홀내의 배선물질 증착불량 문제를 완저히 제거하여 배선간 연결성을 향상시키며, 또한 불필요한 얼라인 마진이 필요없게 되어 소자의 집적도 향상에 기여할 수 있는 것이다.As described above, the present invention is a connection process between multilayer wirings of a semiconductor device, in particular, in a connection process between multilayer metal wirings, by completely eliminating the problem of poor deposition of wiring material in the contact hole by using a conventional contact hole. This improves the interconnectivity and eliminates unnecessary alignment margins, contributing to improved device integration.

Claims (5)

반도체기판 위에 제1도전층을 형성하는 공정과, 상기 제1도전층의 일부위를 소정두께만큼 식각하여 콘택부위인 돌출부를 갖는 제1금속배선층을 형성하는 공정과, 상기 제1금속배선층 상에 상기 돌출부를 덮도록 절연막을 형성하는 공정과, 상기 돌출부 표면이 노출되는 시점까지 절연막을 식각하여 평탄화하는 공정과, 상기 평탄화된 절연막 상에 상기 돌출부를 덮도록 제2금속층을 형성하는 공정과, 상기 돌출부와 연결되도록 상기 제2도전층을 식각하여 제2금속배선층을 형성하는 공정을 구비한 반도체장치의 다층배선간 연결공정.Forming a first conductive layer on the semiconductor substrate, etching a portion of the first conductive layer by a predetermined thickness to form a first metal wiring layer having a protruding portion that is a contact portion, and on the first metal wiring layer Forming an insulating film to cover the protrusion, etching the insulating film to a point where the surface of the protrusion is exposed, and forming a second metal layer to cover the protrusion on the planarized insulating film; Forming a second metal wiring layer by etching the second conductive layer so as to be connected to the protruding portion. 제1항에 있어서, 상기 콘택부위 형성은 상기 제1도전층의 콘택부위에 식각방해막 패턴을 형성한 후, 상기 식각방해막을 마스크로 하여 상기 제1도전층을 소정두께로 제거하여 돌출부로 형성하는 것이 특징인 반도체장치의 다층배선간 연결공정.The method of claim 1, wherein the contact portion is formed by forming an etch stop pattern on the contact portion of the first conductive layer, and then removing the first conductive layer to a predetermined thickness using the etch stop layer as a mask to form a protrusion. The process of connecting the multilayer wiring of a semiconductor device characterized in that. 제1항에 있어서, 상기 제1도전층, 제2도전층은 금속으로 형성하는 것이 특징인 반도체장치의 다층 배선간 연결공정.2. The process of claim 1, wherein the first conductive layer and the second conductive layer are formed of metal. 제1항에 있어서, 상기 제2도전층의 패터닝 폭은 상기 돌출부의 폭과 같은 것이 특징인 반도체장치의 다층배선간 연결공정.2. The process of claim 1, wherein the patterning width of the second conductive layer is equal to the width of the protrusion. 제1항에 있어서, 상기 절연막은 평탄화가 가능한 절연물질로 형성하는 것이 특징인 반도체장치의 다층배선간 연결공정.The process of claim 1, wherein the insulating layer is formed of an insulating material that can be planarized.
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JPS6459935A (en) * 1987-08-31 1989-03-07 Nec Corp Formation of multilayer interconnection of semiconductor device

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