KR100248150B1 - Method of forming contact hole in semiconductor device - Google Patents
Method of forming contact hole in semiconductor device Download PDFInfo
- Publication number
- KR100248150B1 KR100248150B1 KR1019930028622A KR930028622A KR100248150B1 KR 100248150 B1 KR100248150 B1 KR 100248150B1 KR 1019930028622 A KR1019930028622 A KR 1019930028622A KR 930028622 A KR930028622 A KR 930028622A KR 100248150 B1 KR100248150 B1 KR 100248150B1
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- contact
- forming
- oxide film
- etching
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract description 14
- 239000004065 semiconductor Substances 0.000 title abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 238000000151 deposition Methods 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 콘택홀 형성방법으로서, 실리콘 기판위에 필요한 회로요소를 형성한후, 이들과 절연을 위하여 실리콘 산화막을 소정 두께로 데포지션하고 포토레지스트로 콘택홀부위를 정의한후 경사식각을 이용하여 콘택홀부분을 식각하여 제거하는 단계, 실리콘 산화막과 식각선택성이 있는 물질로 콘택홀을 채워서 콘택홀플러그를 형성하는 단계, 상기 실리콘 산화막을 소정 두께만큼 식각하여 제거하고, 콘택홀플러그를 제거하여 최종 콘택홀을 형성하는 단계를 포함하여 이루어 진다.The present invention provides a method for forming a contact hole in a semiconductor device, and after forming a circuit element necessary on a silicon substrate, depositing a silicon oxide film to a predetermined thickness and insulating the contact hole with a photoresist for insulation therebetween, and then using an inclined etching. Etching to remove the contact hole portion, forming a contact hole plug by filling the contact hole with a silicon oxide film and an etch selectivity material, etching and removing the silicon oxide film by a predetermined thickness, and removing the contact hole plug. And forming a final contact hole.
이렇게 하므로서 스테퍼장비 및 노광장비로서 정의할수 있는 최소한의 콘택홀 크기보다 더욱 작은 콘택홀을 정확하게 형성할 수 있게 되고 콘택과 이웃선과의 접촉이 일어나는 문제나 오버레이 마진 확보 문제를 해결할 수 있다.By doing so, it is possible to accurately form a contact hole smaller than the minimum contact hole size that can be defined as a stepper device and an exposure device, and solve the problem of contact between the contact line and the neighbor line or securing the overlay margin.
Description
제1도는 본 발명의 반도체 소자의 콘택홀 형성방법을 설명하기위한 콘택홀부위의 일부 단면도.1 is a partial cross-sectional view of a contact hole portion for explaining a method for forming a contact hole in a semiconductor device of the present invention.
제2도는 본 발명의 반도체 소자의 콘택홀 형성방법의 효과를 설명하기 위한 콘택홀부위의 일부 레이아웃 및 일부 단면도.2 is a partial layout and partial cross-sectional view of a contact hole portion for explaining the effect of the method for forming a contact hole in a semiconductor device of the present invention.
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것이며, 특히 콘택과 인접선과의 쇼트방지 및 콘택과 콘택위를 지나가는 배선과의 오버레이마진을 증가 시킬수 있는 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole capable of increasing a margin of contact between a contact and an adjacent line and an overlay margin between the contact and the wiring passing over the contact.
반도체 소자를 제조할 때 반도체 기판에 트랜지스터, 캐패시터, 등의 회로 요소를 형성한 후, 이 들 회로요소를 다른 요소들과 연결하거나 반도체 칩 외부로 연결하기 위하여 회로요소의 일부와 콘택을 통하여 도체 배선과 연결하는 것이 필요하게 된다.When manufacturing a semiconductor device, circuit elements such as transistors, capacitors, and the like are formed on a semiconductor substrate, and then conductor wiring is connected through a part of the circuit elements and contacts to connect the circuit elements with other elements or outside the semiconductor chip. It is necessary to connect with.
이러한 콘택을 형성하기 위하여 종래에는 반도체 기판위에 회로요소를 형성한후 웨이퍼 전면 위에 절연막을 데포지션하고 평탄화 공정을 실시한 후, 콘택홀을 형성하고 그위에 메탈이나 도전층을 형성하고 패턴형성공정을 실시하여 배선을 연결한다.In order to form such a contact, conventionally, a circuit element is formed on a semiconductor substrate, then an insulating film is deposited on the entire surface of the wafer, a planarization process is performed, a contact hole is formed, a metal or a conductive layer is formed thereon, and a pattern forming process is performed. Connect the wiring.
이 때 콘택홀을 형성하기위하여는 사진식각공정을 이용하여야 하는데, 노광시의 스테퍼의 성능으로 인하여 어떤 한정된 크기로만 정의하는 것이 가능하고 또한 콘택과 이웃선과의 도통을 방지하기위하여 스로퍼식각(경사식각)등으로 콘택을 형성하기도 한다.At this time, the photolithography process should be used to form the contact hole, but due to the performance of the stepper during exposure, it is possible to define only a limited size, and to prevent the contact between the contact and the neighboring line. Etching may be used to form the contact.
그러나 이러한 종래 방법에는 집적도가 증가되면서 회로요소와 배선 간격이 미세하여지면서 사진식각시 포토레지스터 증착 후 스테퍼 장비의 한계로 콘택과 이웃선과의 접촉으로 쇼트되는 것을 방지하기가 어렵고, 상하층간의 오버레이 마진(다층배선의 공정여유) 확보가 힘들며, 콘택부의 얇은 산화막으로 인하여 경사식각시 정션부의 콘택크기를 감소시키는데 문제가 있었다.However, in this conventional method, it is difficult to prevent short-circuit due to contact with neighboring lines due to the limitation of stepper equipment after photoresist deposition during photolithography as the density of circuit elements and wiring becomes minute as the integration degree increases, and overlay margin between upper and lower layers It is difficult to secure the process layer of the multi-layer wiring, and there is a problem in reducing the contact size of the junction portion during the inclined etching due to the thin oxide film of the contact portion.
본 발명은 기존의 스테페퍼 장비를 이용하면서도 사진식각시 콘택과 이웃선과의 접촉으로 쇼트되는 것을 방지하고 상하층 간의 오버레이 마진을 확보하며 콘택부의 얇은 산화막으로 인하여 경사식각시 정션부의 콘택 크기를 감소시키는 문제를 해소하려는 것이다.The present invention prevents the short-circuit due to contact with neighboring lines during photolithography while using existing stepper equipment, secures an overlay margin between upper and lower layers, and reduces the contact size of the junction portion during inclined etching due to a thin oxide layer of the contact portion. It is to solve the problem.
본 발명은 반도체 소자의 콘택홀 형성방법으로서, 실리콘 기판위에 필요한 회로요소를 형성한후, 이들과 절연을 위하여 실리콘 산화막을 소정두께로 데포지션하고 포토레지스트로 콘택홀부위를 정의한후 경사식각을 이용하여 콘택홀부분을 식각하여 제거하는 단계, 실리콘 산화막과 식각선택성이 있는 물질로 콘택홀을 채워서 콘택홀플러그를 형성하는 단계, 상기 실리콘 산화막을 소정 두께만큼 식각하여 제거하고, 콘택홀플러그를 제거하여 최종 콘택홀을 형성하는 단계를 포함하여 이루어 진다.The present invention provides a method for forming a contact hole in a semiconductor device, and after forming a circuit element on a silicon substrate, depositing a silicon oxide film to a predetermined thickness to insulate them, and defining a contact hole with a photoresist and then using an inclined etching. Etching to remove the contact hole portion, forming a contact hole plug by filling the contact hole with a silicon oxide film and an etch selectivity material, etching and removing the silicon oxide film by a predetermined thickness, and removing the contact hole plug. And forming a final contact hole.
실리콘 산화막과 식각선택성이 있는 물질로서 포토레지스트, 또는 실리콘 질화막을 사용하여 이를 웨이퍼 전면에 데포지션하고 에치백하여 콘택홀플러그를 형성한다.The contact hole plug is formed by depositing and etching back the entire surface of the wafer using a photoresist or a silicon nitride film as a material having an etching selectivity with a silicon oxide film.
도면을 참조하면서 실시예를 자세히 설명한다.Embodiments will be described in detail with reference to the drawings.
제1a도에서 보인 바와 같이, 실리콘 기판(1)위에 소자가 형성될 활성영역과 격리영역을 형성하고 게이트전극(2)과 소오스 드레인 영역(6), 등의 회로요소를 형성한후, 이들과 절연을 위하여 산화막(3)을 소정 두께(약 1 내지 1.5㎛)로 데포지션하고 포토레지스트(4)를 코팅하여 노광 현상공정으로 콘택홀을 정의하고 경사식각을 이용하여 콘택홀부분(5)을 식각하여 제거한다.As shown in FIG. 1A, an active region and an isolation region are formed on the silicon substrate 1, and circuit elements such as the gate electrode 2 and the source drain region 6 are formed. For insulation, the oxide film 3 is deposited to a predetermined thickness (about 1 to 1.5 μm), the photoresist 4 is coated, and the contact hole is defined by an exposure developing process, and the contact hole portion 5 is formed by using an inclined etching. Etch and remove
다음에 제1b도에서 보인바와 같이, 실리콘 산화막과 식각선택성이 있는 물질, 예로서 포토레지스트나 실리콘 질화막 등으로 콘택홀을 채우면서 데포지션하고 에치백하여 콘택홀플러그(7)를 형성한다.Next, as shown in FIG. 1B, the contact hole plug 7 is formed by depositing and etching back while filling the contact hole with a silicon oxide film and an etch-selective material such as a photoresist or silicon nitride film.
다음에 제1c도에서 보인바와 같이, 산화막(3)을 소정 두께만큼 식각하여 제거한다.Next, as shown in FIG. 1C, the oxide film 3 is etched and removed by a predetermined thickness.
이어서 제1d도에서 보인바와 같이, 콘택홀플러그를 제거하고 도전물질 예로서 알루미늄 이나 티타늄 등의 메탈이나 폴리실리콘, 또는 실리사이드 등을 데포지션한 후 사진식각 공정으로 배선형성을 한다.Subsequently, as shown in FIG. 1d, the contact hole plug is removed, and metals such as aluminum or titanium, polysilicon, or silicide are deposited, and the wiring is formed by a photolithography process.
이렇게 하므로서 스테퍼장비 및 노광장비로서 정의할 수 있는 최소한의 콘택홀 크기보다 더욱 작은 콘택홀을 정확하게 형성할 수 있게 된다.In this way, contact holes smaller than the minimum contact hole size that can be defined as stepper equipment and exposure equipment can be accurately formed.
제2a도에서 보인바와 같이, 제1라인 (21) 형성후 두꺼운 산화막을 이용함으로써 경사식각시 콘택크기가 작아져서 "a" 부분의 길이를 증가시킨다. 따라서 콘택과 이웃하는 선과의 도통을 방지할수 있다. 그리고 제2라인(22) 형성시 콘부와의 간격인 "b"를 역시 크게하여 콘택부의 손상을 줄일수 있다. 더 나아가서 콘택홀플러그를 형성한 후 산화막을 소정부분 식각하므로써 소자 전체의 토포로지를 작게 할수 있다.As shown in FIG. 2A, by using a thick oxide film after the formation of the first line 21, the contact size is reduced during the inclined etching, thereby increasing the length of the "a" part. Therefore, it is possible to prevent the contact between the contact and the neighboring line. In addition, when the second line 22 is formed, “b”, which is a distance from the cone portion, may also be increased to reduce damage to the contact portion. Further, by forming a contact hole plug, the oxide film is etched by a predetermined portion, whereby the topology of the entire device can be reduced.
제2b도에서 23번은 필드산화막, 24번은 산화막, 25번은 콘택홀플러그를 가르킨다.In FIG. 2B, 23 indicates a field oxide film, 24 an oxide film, and 25 a contact hole plug.
본 방법을 이용하면 기존의 장비를 이용하여 종래 방법에서 회로요소와 배선 간격이 미세하여지면서 사진식각시 포토레지스터 증착 후 스테퍼 장비의 한계로 콘택과 이웃선과의 접촉이 일어나는 문제나 오버레이 마진 확보 문제를 해결할 수 있다.By using this method, the gap between circuit elements and wiring becomes smaller in the conventional method using existing equipment, and the problem of contact with neighboring lines or contact margins due to the limitation of stepper equipment after photoresist deposition during photolithography is solved. I can solve it.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930028622A KR100248150B1 (en) | 1993-12-20 | 1993-12-20 | Method of forming contact hole in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930028622A KR100248150B1 (en) | 1993-12-20 | 1993-12-20 | Method of forming contact hole in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950021076A KR950021076A (en) | 1995-07-26 |
| KR100248150B1 true KR100248150B1 (en) | 2000-03-15 |
Family
ID=19371755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930028622A KR100248150B1 (en) | 1993-12-20 | 1993-12-20 | Method of forming contact hole in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100248150B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100443123B1 (en) * | 1998-01-13 | 2004-09-18 | 삼성전자주식회사 | Method for fabricating semiconductor device to improve reliability and correspond to high integrated semiconductor device |
-
1993
- 1993-12-20 KR KR1019930028622A patent/KR100248150B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100443123B1 (en) * | 1998-01-13 | 2004-09-18 | 삼성전자주식회사 | Method for fabricating semiconductor device to improve reliability and correspond to high integrated semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR950021076A (en) | 1995-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR900001834B1 (en) | Method of manufacturing semiconductor device | |
| KR100248150B1 (en) | Method of forming contact hole in semiconductor device | |
| KR20020074551A (en) | Method of forming a metal line in a semiconductor device | |
| KR0121106B1 (en) | Method of metal wiring of semiconductor element | |
| KR100583121B1 (en) | A method for manufacturing metal contact hole of semiconductor device | |
| KR100191710B1 (en) | Metal wiring method of semiconductor device | |
| KR100360152B1 (en) | Method for forming metal line | |
| KR100265991B1 (en) | Manufacture of semiconductor device | |
| KR0165491B1 (en) | Semiconductor memory device having dumy pattern & its fabrication method | |
| KR0137980B1 (en) | Fabrication method of tungsten plug | |
| KR970000693B1 (en) | Over lap margin securing method of semiconductor device | |
| KR100209210B1 (en) | Method for forming a contact of semiconductor device | |
| KR960011250B1 (en) | Semiconductor contact device manufacturing method | |
| KR100230735B1 (en) | Process for fabricating semiconductor device | |
| KR950010852B1 (en) | Fine contact patterning method of semiconductor device | |
| KR100372657B1 (en) | Method for forming contact of semiconductor device | |
| KR19990060819A (en) | Metal wiring formation method of semiconductor device | |
| KR100243290B1 (en) | Semiconductor device having a sturucture of wring for preventing shift of wiring layer | |
| KR20010004008A (en) | Method for forming metal wiring of semiconductor device having Air-gap | |
| KR0137979B1 (en) | Fine contact forming method of semiconductor device | |
| KR0137433B1 (en) | Contact hole fabrication method of semiconductor device | |
| KR0137566B1 (en) | Contact hole fabrication method of semiconductor device | |
| KR910000277B1 (en) | Multilayer semiconductor | |
| KR0172553B1 (en) | Method of manufacturing semiconductor device | |
| KR100237758B1 (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20071120 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |