JPH05316381A - Blanking circuit - Google Patents

Blanking circuit

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Publication number
JPH05316381A
JPH05316381A JP11718092A JP11718092A JPH05316381A JP H05316381 A JPH05316381 A JP H05316381A JP 11718092 A JP11718092 A JP 11718092A JP 11718092 A JP11718092 A JP 11718092A JP H05316381 A JPH05316381 A JP H05316381A
Authority
JP
Japan
Prior art keywords
pulse
comparator
display area
blanking
reference voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11718092A
Other languages
Japanese (ja)
Other versions
JP3246674B2 (en
Inventor
Hideaki Konishi
秀明 小西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11718092A priority Critical patent/JP3246674B2/en
Publication of JPH05316381A publication Critical patent/JPH05316381A/en
Application granted granted Critical
Publication of JP3246674B2 publication Critical patent/JP3246674B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Details Of Television Scanning (AREA)

Abstract

PURPOSE:To prevent halation by comparing a deflection use sawtooth wave with a DC bias applied thereto with a reference voltage so as to discriminate whether or not a video signal is in existence in a valid display area and blanking the video signal resident at the outside of the valid display area. CONSTITUTION:A reference voltage Vb is fed to one input of a comparator IC1, a deflection use sawtooth wave with a DC bias applied thereto is applied to the other input and a pulse 1 is generated when the sawtooth wave voltage V1 exceeds the reference voltage Vb. A reference voltage Va is fed to one input of a comparator IC2, a deflection use sawtooth wave with a DC bias applied thereto is applied to the other input. The polarity of the input signal to the comparator IC2 is opposite to that to the comparator IC1 and the comparator IC2 generates a pulse 2 when the sawtooth voltage V2 is decreased more than the reference voltage Va. The pulse 1 through a diode D1, the pulse 2 through a diode D2 and a pulse 3 through a diode 3 used to apply blanking to a signal for a blanking period are synthesized to form a new pulse.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はＣＲＴを使用し、テレビ
ジョン受像機やモニター受像機の様に、オーバースキャ
ン走査で動作する映像受像機などに適するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for a video receiver which uses a CRT and operates by overscan scanning, such as a television receiver and a monitor receiver.

【０００２】[0002]

【従来の技術】近年、ＣＲＴを使用したテレビジョン受
像機やモニター受像機にでは、図４の様に走査線の帰線
期間に対して、ブランキングをかけ、ＣＲＴ管面上に帰
線が見えることを防いでいる。2. Description of the Related Art In recent years, in a television receiver or a monitor receiver using a CRT, blanking is applied to the blanking period of the scanning line as shown in FIG. It prevents you from seeing.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら実際オー
バースキャンで偏向した場合、図３の様にＣＲＴの内側
に当たり反射した電子ビームがＣＲＴ管面を光らせる現
象（以下、ハレーション現象と呼ぶ）が発生する。本発
明では有効表示領域内の走査か、そうでないかを基準電
圧とＤＣ的に比較する回路を用い、有効表示領域外を走
査する映像信号に対し、ブランキングをかけることでハ
レーション現象を防止するようにブランキング回路を構
成している。However, when the deflection is actually performed by overscan, a phenomenon (hereinafter referred to as a halation phenomenon) occurs in which the reflected electron beam hits the inside of the CRT and shines on the surface of the CRT tube as shown in FIG. In the present invention, a circuit that compares the scanning within the effective display area with the reference voltage in terms of DC is used, and the halation phenomenon is prevented by blanking the video signal scanning outside the effective display area. Thus, the blanking circuit is configured.

【０００４】[0004]

【課題を解決するための手段】本発明のブランキング回
路はＤＣバイアスをかけた偏向のこぎり波を基準電圧と
比較し、有効表示領域部分かそうでないかを判定し、有
効表示領域外の映像信号に対してブランキングをかける
様にしている。A blanking circuit of the present invention compares a DC saw biased sawtooth wave with a reference voltage to determine whether an effective display area portion or not, and a video signal outside the effective display area. It is designed to be blanked against.

【０００５】[0005]

【作用】本発明のブランキング回路においては、帰線期
間だけでなく、有効表示領域外全体に対してブランキン
グをかけるため、ハレーション現象を防止することがで
きる。In the blanking circuit of the present invention, not only the blanking period but also the entire area outside the effective display area is blanked, so that the halation phenomenon can be prevented.

【０００６】[0006]

【実施例】以下、本発明のブランキング回路を図１から
図５によって説明する。図１は本発明のブランキング回
路の全体図である。図１において偏向のこぎり波をコン
デンサＣ１を通して入力する。この入力のこぎり波を抵
抗１・抵抗２でバイアスをかけＤＣ変換する。バイアス
をかけたのこぎり波は図２の様になる。ここで図２の基
準電圧Ｖa及び基準電圧ＶbはそれぞれＣＲＴの有効表示
領域を示す基準電圧であり、基準電圧Ｖaより低い電圧
と基準電圧Ｖbより高い電圧部分はそれぞれ有効表示領
域外で視聴者には見ることが出きない部分である。図３
はＣＲＴの有効表示領域を表す図であり、図３の様にの
こぎり波でＶa以下あるいはＶb以上の電圧の部分では見
えないばかりでなく、それがＣＲＴの内部の面に反射
し、ハレーションとして画面に表われる。ここで図１の
コンパレーターＩＣ１に対して、一方に基準電圧Ｖbを
加え、もう一方にはバイアスをかけＤＣ変換した偏向の
こぎり波を加え、こののこぎり波電圧Ｖ1がＶbを越えた
時にパルス１を発生させる。またコンパレーターＩＣ２
には一方に基準電圧Ｖaをもう一方にバイアスをかけた
偏向のこぎり波を加える。コンパレーターＩＣ２はコン
パレーターＩＣ１とは極性を逆向けに入力信号を加えて
おくと基準電圧Ｖa以下にのこぎり波電圧Ｖ2が下がった
時にパルス２を発生する。そしてこのパルス１をダイオ
ードＤ１を通して、またパルス２をダイオードＤ２を通
して、通常使用している帰線期間に対してブランキング
をかけているパルス３をダイオードＤ３を通して合成
し、これを新しいブランキングパルスとする様にした。
すなわち図５の様にパルス１、パルス２、パルス３を合
成して、新しいブランキングパルスをつくり、そして有
効表示領域外の走査線すべてに対してブランキングをか
ける様にしたのが本ブランキング回路である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The blanking circuit of the present invention will be described below with reference to FIGS. FIG. 1 is an overall view of the blanking circuit of the present invention. In FIG. 1, a deflection sawtooth wave is input through a capacitor C1. The sawtooth wave of this input is DC-converted by biasing it with resistors 1 and 2. The biased sawtooth wave looks like Figure 2. Here, the reference voltage V a and the reference voltage V b in FIG. 2 is a reference voltage indicating an effective display area of the CRT respectively, a reference voltage V a voltage lower than the reference voltage higher portion than the voltage V b is the effective display area outside each That is the part that the viewer cannot see. Figure 3
Is a diagram showing an effective display area of the CRT, and as shown in FIG. 3, not only is it invisible at a voltage of V a or less or V b or more due to a sawtooth wave, it is reflected on the inner surface of the CRT and halation Appears on the screen as. Here respect comparator IC1 of Figure 1, while the reference voltage V b was added to the deflection sawtooth wave DC conversion bias is added to the other, when the sawtooth voltage V 1 is beyond the V b Generate pulse 1. Also comparator IC2
Is applied with a reference sawtooth voltage V a on one side and a deflection sawtooth wave biased on the other side. Comparator IC2 is a comparator IC1 generates a pulse 2 when the sawtooth voltage V 2 drops an input signal keep the below reference voltage V a in addition to the opposite for the polarity. Then, this pulse 1 is synthesized through the diode D1, the pulse 2 is synthesized through the diode D2, and the pulse 3 which is blanking the normally used blanking period is synthesized through the diode D3, which is used as a new blanking pulse. I decided to do it.
That is, as shown in FIG. 5, this blanking is performed by combining pulse 1, pulse 2 and pulse 3 to create a new blanking pulse and blanking all scanning lines outside the effective display area. Circuit.

【０００７】[0007]

【発明の効果】本発明はオーバースキャン走査に対し
て、ＣＲＴ内面での反射によるハレーションを防止する
のに有効である。The present invention is effective in preventing halation due to reflection on the inner surface of a CRT in overscan scanning.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例のブランキング回路FIG. 1 is a blanking circuit according to an embodiment of the present invention.

【図２】図１における偏向のこぎり波形ならびにバイア
スをかけたのこぎり波形2 is a deflection sawtooth waveform and a biased sawtooth waveform in FIG.

【図３】図１におけるＣＲＴの有効表示領域とのこぎり
波の関係図3 is a diagram showing the relationship between the effective display area of the CRT and the sawtooth wave in FIG.

【図４】従来のブランキングパルス波形図FIG. 4 is a conventional blanking pulse waveform diagram.

【図５】図１におけるブランキングパルスの合成図FIG. 5 is a composite diagram of blanking pulses in FIG.

【符号の説明】[Explanation of symbols]

Ｒ１，Ｒ２，Ｒ３，Ｒ４，Ｒ５ 抵抗 Ｃ１ コンデンサ Ｄ１，Ｄ２，Ｄ３ ダイオード ＩＣ１，ＩＣ２ ＩＣ（コンパレーター） R1, R2, R3, R4, R5 Resistance C1 Capacitor D1, D2, D3 Diode IC1, IC2 IC (comparator)

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 ＣＲＴを使用した映像受像機の偏向に対
して、そのＣＲＴ管面の有効表示領域に該当する基準電
圧を決定する回路と偏向のこぎり波にＤＣバイアスを加
える回路の両出力をコンパレーターに入力し、その出力
により、偏向された走査線がＣＲＴの有効表示領域内に
あるかどうかを判別することを特徴とするブランキング
回路。1. Comparing both outputs of a circuit for determining a reference voltage corresponding to an effective display area of a CRT tube surface and a circuit for applying a DC bias to a sawtooth wave of the deflection for deflection of a video receiver using a CRT. A blanking circuit, which is characterized in that it is inputted to a vibrator and the output thereof judges whether or not the deflected scanning line is within the effective display area of the CRT. 【請求項２】 ＣＲＴの有効表示領域に相当する基準電
圧を決定する回路と偏向のこぎり波にＤＣバイアスを加
える回路の両出力をコンパレーターに入力し、その出力
により、偏向された電子ビームがＣＲＴの有効表示領域
内にあるかを判別する回路を用い、走査線が有効表示領
域外に出た場合に、コンパレーターの出力パルスをブラ
ンキングパルスとして、映像信号にブランキングをかけ
る様にしたことを特徴とするブランキング回路。2. A comparator is supplied with both outputs of a circuit for determining a reference voltage corresponding to an effective display area of a CRT and a circuit for applying a DC bias to a sawtooth wave of a deflection, and the deflected electron beam is caused by the output of the comparator. Use a circuit that determines whether the image signal is within the effective display area, and when the scanning line goes out of the effective display area, the output pulse of the comparator is used as a blanking pulse to blank the video signal. Blanking circuit characterized by.
JP11718092A 1992-05-11 1992-05-11 Blanking circuit Expired - Fee Related JP3246674B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11718092A JP3246674B2 (en) 1992-05-11 1992-05-11 Blanking circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11718092A JP3246674B2 (en) 1992-05-11 1992-05-11 Blanking circuit

Publications (2)

Publication Number Publication Date
JPH05316381A true JPH05316381A (en) 1993-11-26
JP3246674B2 JP3246674B2 (en) 2002-01-15

Family

ID=14705402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11718092A Expired - Fee Related JP3246674B2 (en) 1992-05-11 1992-05-11 Blanking circuit

Country Status (1)

Country Link
JP (1) JP3246674B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05328165A (en) * 1992-05-20 1993-12-10 Victor Co Of Japan Ltd Vertical blanking signal generating circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05328165A (en) * 1992-05-20 1993-12-10 Victor Co Of Japan Ltd Vertical blanking signal generating circuit

Also Published As

Publication number Publication date
JP3246674B2 (en) 2002-01-15

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