JPH05283759A - Manufacture of single electron tunnel transistor element - Google Patents
Manufacture of single electron tunnel transistor elementInfo
- Publication number
- JPH05283759A JPH05283759A JP4074838A JP7483892A JPH05283759A JP H05283759 A JPH05283759 A JP H05283759A JP 4074838 A JP4074838 A JP 4074838A JP 7483892 A JP7483892 A JP 7483892A JP H05283759 A JPH05283759 A JP H05283759A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- thin film
- transistor element
- tunnel transistor
- electron tunnel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000010409 thin film Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 4
- 239000002887 superconductor Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 4
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims 1
- 239000000395 magnesium oxide Substances 0.000 claims 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims 1
- 229910021521 yttrium barium copper oxide Inorganic materials 0.000 abstract description 14
- 239000013078 crystal Substances 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 2
- 238000007788 roughening Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 8
- 239000008187 granular material Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 3
- 235000010724 Wisteria floribunda Nutrition 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910002480 Cu-O Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/7613—Single electron transistors; Coulomb blockade devices
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ソース電極とドレイン
電極との間にある粒状物質からなるチャネルの単一電子
トンネルをゲート電極へ印加する電圧で制御する単一電
子トンネルトランジスタ素子の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a single electron tunnel transistor device in which a single electron tunnel of a channel made of a granular material between a source electrode and a drain electrode is controlled by a voltage applied to a gate electrode. Regarding
【０００２】[0002]
【従来の技術】粒状物質の粒界におけるトンネル効果を
利用した単一電子トンネル (以下ＳＥＴと略す）トラン
ジスタ素子は、スイッチング速度の速いこと、消費電力
が小さいことなどの利点が得られるものとして注目され
ている。図２はＳＥＴトランジスタの構造を示し、絶縁
体２で覆われた粒状物質１からなるチャネル１０を基板
３の上に有し、そのチャネル１０をはさんでソース端子
Ｓに接続されたソース電極４とドレイン端子Ｄに接続さ
れたドレイン電極５、チャネル１０の上に絶縁体２を介
してゲート端子Ｇに接続されたゲート電極６がそれぞれ
設けられてＦＥＴ構造を構成している。このチャネル１
０には、例えばＩＳＥＣ '89にL.Kuzmin (Abstracts p3
44) 、N. Yoshikawa ( Abstracts p298)、T.Akeyoshi他
( Abstracts p334)が発表しているように、Al、Au、Pt
などの高融点を持つ金属材料のほかに、ＮｂＮやBi−Sr
−Ca−Cu−Ｏなどの超電導体が用いられている。2. Description of the Related Art A single-electron tunnel (hereinafter abbreviated as SET) transistor device utilizing the tunnel effect at the grain boundary of a granular material is noted as having advantages such as high switching speed and low power consumption. Has been done. FIG. 2 shows the structure of a SET transistor, which has a channel 10 made of a granular material 1 covered with an insulator 2 on a substrate 3, and a source electrode 4 connected to a source terminal S with the channel 10 sandwiched therebetween. A drain electrode 5 connected to the drain terminal D and a gate electrode 6 connected to the gate terminal G via the insulator 2 are provided on the channel 10 to form an FET structure. This channel 1
0, for example, LSEC Kuzmin (Abstracts p3
44), N. Yoshikawa (Abstracts p298), T. Akeyoshi et al.
As announced by (Abstracts p334), Al, Au, Pt
In addition to metallic materials with high melting points such as NbN and Bi-Sr
A superconductor such as -Ca-Cu-O is used.
【０００３】[0003]
【発明が解決しようとする課題】良好な特性を持つＳＥ
Ｔトランジスタ素子を得るためのキーポイントの一つと
してチャネル部における粒の均一形成、すなわち粒径お
よび粒間の距離を均一にすることが挙げられる。高融点
金属は、一般に島状成長することが知られている。この
ため、膜厚を数nm程度に極端に薄くすれば、均一な粒を
持つチャネルを形成することができる。またＮｂＮの場
合には、一般にスパッタリング法により合成されるが、
スパッタ条件により均一な粒を持つチャネルを形成する
ことができる。しかし、チャネルに酸化物超電導体を用
いた場合には、チャネルの再現性のよい形成が困難であ
った。SE having good characteristics
One of the key points for obtaining the T-transistor element is to uniformly form grains in the channel portion, that is, to make the grain size and the distance between grains uniform. It is known that refractory metals generally grow in an island shape. Therefore, if the film thickness is made extremely thin to about several nm, it is possible to form channels having uniform particles. In the case of NbN, it is generally synthesized by the sputtering method,
Channels having uniform grains can be formed depending on the sputtering conditions. However, when an oxide superconductor was used for the channel, it was difficult to form the channel with good reproducibility.
【０００４】本発明の目的は、上記の問題を解決し、酸
化物超電導体を用いて、しかも再現性のよいＳＥＴトラ
ンジスタ素子の製造方法を提供することにある。An object of the present invention is to solve the above problems and to provide a method for manufacturing a SET transistor element using an oxide superconductor and having good reproducibility.
【０００５】[0005]
【課題を解決するための手段】上述の目的を達成するた
めに、本発明のＳＥＴトランジスタ素子の製造方法は、
凹凸処理を施した基板表面上に、その凹凸の高さの２倍
より薄い膜厚の酸化物超電導体の薄膜を形成し、その薄
膜からなるチャネルをはさんでソース電極およびドレイ
ン電極、チャネル上に絶縁体を介してゲート電極を設け
るものとする。酸化物超電導体の薄膜を反応性蒸着法で
形成することが効果的である。そして、基板の材料とし
てMgＯ単結晶あるいはSiTiＯ3 x を用い、酸化物超電導
体としてＹBa2 Cu3 Ｏx ( 以下ＹＢＣＯと記す) を用い
ることが有効である。また、基板表面の凹凸処理をカー
ボランダム粒を用いて行うことあるいはイオン照射によ
り行うことが有効である。In order to achieve the above-mentioned object, a method for manufacturing a SET transistor element of the present invention comprises:
A thin film of oxide superconductor with a thickness less than twice the height of the unevenness is formed on the surface of the substrate that has been subjected to unevenness treatment, and the thin film channel is sandwiched between the source electrode, drain electrode, and channel. A gate electrode is to be provided through an insulator. It is effective to form a thin film of an oxide superconductor by a reactive vapor deposition method. Then, it is effective to use MgO single crystal or SiTiO 3 x as the material for the substrate and YBa 2 Cu 3 O x (hereinafter referred to as YBCO) as the oxide superconductor. Further, it is effective to perform the unevenness treatment on the substrate surface by using carborundum grains or by ion irradiation.
【０００６】[0006]
【作用】基板に凹凸処理を施し、その基板の凹凸高さの
２倍よりも膜厚の薄い酸化物超電導体の膜を形成する
と、擬似的な粒界が均一に形成される。このような相互
間に擬似的な粒界を持つ微小な粒からなる膜に電圧を印
加した場合には、粒界が微小なコンデンサとして作用す
るため、容量をＣ、電気素量をｅとして２Ｃ／ｅに相当
した電圧で、単一電子の隣の粒へのトンネルが生じる。When the substrate is subjected to the concavo-convex treatment to form an oxide superconductor film having a thickness smaller than twice the height of the concavo-convex of the substrate, pseudo grain boundaries are uniformly formed. When a voltage is applied to a film made up of minute grains having pseudo grain boundaries between them, the grain boundaries act as minute capacitors, so the capacitance is C and the elementary charge is 2C. At a voltage corresponding to / e, a single electron tunnels to the next grain.
【０００７】[0007]
【実施例】本発明の一実施例により製造されたＳＥＴト
ランジスタ素子は、図２に示した素子と同様な構造をも
ち、基板３の材料にMgＯ単結晶を用い、その表面を粒径
100nm のカーボランダムで研磨することにより凹凸処理
をした。凹凸の高さは約50nmであった。そしてその面の
上に反応性蒸着法でＹＢＣＯの薄膜を形成した。その薄
膜の厚さを変え、異なる膜厚を持つＹＢＣＯの抵抗の温
度変化を測定した結果を図３に示す。膜厚が基板凹凸の
２倍より厚い場合には通常のＹＢＣＯの特性であるが、
膜厚が基板凹凸の２倍より薄い場合には、ＳＥＴに起因
した抵抗の増加が観測された。蒸着法は、スパッタ法や
ＣＶＤ法と比較してステップカバレージが悪いことが知
られている。このため図１に概念的に示すように、ＹＢ
ＣＯからなる粒状物質１相互間にMgＯ基板３の表面の凹
凸により擬似粒界が形成されたことにより、トンネル効
果があらわれたものと考えられる。このようにして作ら
れたチャネル１０をはさんで、膜厚が500nm と厚いＹＢ
ＣＯによりソース電極４およびドレイン電極５を形成し
た。膜厚が基板凹凸の２倍より厚いため、これらの電極
に擬似粒界は形成されていない。そしてゲート絶縁体２
としてMgＯを用い、ゲート電極６をAlで形成した。基板
および絶縁体を構成するMgＯはＹＢＣＯと熱膨脹係数が
近似しており、温度変動の際にチャネル１０に応力が加
わることがない。また単結晶MgＯはＹＢＣＯと格子常数
が近似しているため、その上に均一にＹＢＣＯ薄膜が形
成されやすい。同様にＹＢＣＯと格子定数や熱膨脹係数
の近いSiTiＯ3 を基板に使用することができる。また、
基板表面の凹凸処理をイオン照射で行ってもよい。EXAMPLE A SET transistor element manufactured according to an example of the present invention has a structure similar to that of the element shown in FIG. 2, uses MgO single crystal as the material of the substrate 3, and the surface thereof has a grain size.
Concavo-convex treatment was performed by polishing with 100 nm carborundum. The height of the irregularities was about 50 nm. Then, a YBCO thin film was formed on the surface by reactive vapor deposition. FIG. 3 shows the result of measuring the temperature change of the resistance of YBCO having different film thicknesses while changing the thickness of the thin film. When the film thickness is thicker than twice the unevenness of the substrate, it is a characteristic of normal YBCO.
When the film thickness was thinner than twice the substrate unevenness, an increase in resistance due to SET was observed. It is known that the vapor deposition method has worse step coverage than the sputtering method and the CVD method. Therefore, as conceptually shown in FIG.
It is considered that the tunnel effect appeared because the pseudo grain boundaries were formed between the granular substances 1 made of CO by the unevenness of the surface of the MgO substrate 3. YB with a thickness of 500 nm is sandwiched between the channels 10 made in this way.
The source electrode 4 and the drain electrode 5 were formed of CO. Since the film thickness is thicker than twice the substrate irregularities, no pseudo grain boundary is formed in these electrodes. And the gate insulator 2
The gate electrode 6 was formed of Al using MgO. MgO forming the substrate and the insulator has a thermal expansion coefficient similar to that of YBCO, and therefore stress is not applied to the channel 10 when the temperature changes. Further, since single crystal MgO has a lattice constant close to that of YBCO, a YBCO thin film is easily formed on it. Similarly, SiTiO 3 having a lattice constant and a thermal expansion coefficient close to that of YBCO can be used for the substrate. Also,
The unevenness treatment on the substrate surface may be performed by ion irradiation.
【０００８】図４は、製造した図２の構造のＳＥＴトラ
ンジスタ素子のＳ−Ｇ間バイアス電圧0.25Ｖにおける特
性を示し、ゲート電圧の変化に対して、この素子特有の
ソース・ドレイン電流の周期的な振動が観測された。FIG. 4 shows the characteristics of the manufactured SET transistor element having the structure shown in FIG. 2 at an S-G bias voltage of 0.25 V. The source-drain current peculiar to this element changes periodically with respect to the change of the gate voltage. Various vibrations were observed.
【０００９】[0009]
【発明の効果】本発明によれば、凹凸処理した基板上へ
の酸化物超電導体の薄膜を堆積することにより、トンネ
ル効果を生ずる擬似粒界を形成したので、再現性よくＳ
ＥＴトランジスタ素子を製造することが可能になった。According to the present invention, a pseudo grain boundary that causes a tunnel effect is formed by depositing a thin film of an oxide superconductor on a substrate having a textured surface.
It has become possible to manufacture ET transistor devices.
【図１】本発明の一実施例によるＳＥＴトランジスタ素
子の要部拡大図FIG. 1 is an enlarged view of a main part of a SET transistor element according to an embodiment of the present invention.
【図２】本発明によた製造されるＳＥＴトランジスタ素
子の一例の構造を示す断面図FIG. 2 is a sectional view showing the structure of an example of a SET transistor device manufactured according to the present invention.
【図３】凹凸基板上に堆積された種々の膜厚のＹＢＣＯ
膜の抵抗の温度依存性を示す線図FIG. 3 YBCO of various thicknesses deposited on a textured substrate
Diagram showing temperature dependence of film resistance
【図４】本発明の一実施例によるＳＥＴトランジスタ素
子の特性線図FIG. 4 is a characteristic diagram of a SET transistor device according to an embodiment of the present invention.
１ 粒状物質 ２ 絶縁体 ３ 基板 ４ ソース電極 ５ ドレイン電極 ６ ゲート電極 １０ チャネル 1 granular material 2 insulator 3 substrate 4 source electrode 5 drain electrode 6 gate electrode 10 channel
───────────────────────────────────────────────────── フロントページの続き (72)発明者 津田 孝一 神奈川県川崎市川崎区田辺新田１番１号 富士電機株式会社内 (72)発明者 向江 和郎 神奈川県川崎市川崎区田辺新田１番１号 富士電機株式会社内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Koichi Tsuda 1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Fuji Electric Co., Ltd. No. 1 inside Fuji Electric Co., Ltd.
Claims (7)
の高さの２倍より薄い膜厚の酸化物超電導体の薄膜を形
成し、その薄膜からなるチャネルをはさんでソース電極
およびドレイン電極、チャネル上に絶縁体を介してゲー
ト電極を設けることを特徴とする単一電子トンネルトラ
ンジスタ素子の製造方法。1. A thin film of an oxide superconductor having a thickness smaller than twice the height of the unevenness is formed on the surface of the substrate subjected to the unevenness treatment, and a source electrode and a thin film are sandwiched between the thin film and the source electrode. A method of manufacturing a single-electron tunnel transistor element, comprising providing a gate electrode on a drain electrode and a channel via an insulator.
成する請求項１記載の単一電子トンネルトランジスタ素
子の製造方法。2. The method for producing a single electron tunnel transistor device according to claim 1, wherein the oxide superconductor thin film is formed by a reactive vapor deposition method.
請求項１あるいは２記載の単一電子トンネルトランジス
タ素子の製造方法。3. The method for manufacturing a single electron tunnel transistor element according to claim 1, wherein magnesium oxide is used as the substrate material.
用いる請求項１あるいは２記載の単一電子トンネルトラ
ンジスタ素子の製造方法。4. The method for manufacturing a single electron tunnel transistor element according to claim 1, wherein strontium titanate is used as the substrate material.
いる請求項１ないし４のいずれかに記載の単一電子トン
ネルトランジスタ素子の製造方法。5. The method for manufacturing a single electron tunnel transistor element according to claim 1, wherein YBa 2 Cu 3 O x is used as the oxide superconductor.
用いて行う請求項１ないし５のいずれかに記載の単一電
子トンネルトランジスタ素子の製造方法。6. The method for manufacturing a single electron tunnel transistor element according to claim 1, wherein the unevenness treatment of the substrate surface is carried out by using carborundum grains.
う請求項１ないし５のいずれかに記載の単一電子トンネ
ルトランジスタ素子の製造方法。7. The method for manufacturing a single electron tunnel transistor element according to claim 1, wherein the unevenness treatment on the substrate surface is performed by ion irradiation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4074838A JPH05283759A (en) | 1992-03-31 | 1992-03-31 | Manufacture of single electron tunnel transistor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4074838A JPH05283759A (en) | 1992-03-31 | 1992-03-31 | Manufacture of single electron tunnel transistor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05283759A true JPH05283759A (en) | 1993-10-29 |
Family
ID=13558880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4074838A Pending JPH05283759A (en) | 1992-03-31 | 1992-03-31 | Manufacture of single electron tunnel transistor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05283759A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07240509A (en) * | 1994-01-19 | 1995-09-12 | Siemens Ag | Micro electron device |
| EP0750353A2 (en) * | 1995-06-23 | 1996-12-27 | Matsushita Electric Industrial Co., Ltd. | Single electron tunnel device and method for fabricating the same |
| WO2000041247A3 (en) * | 1998-12-30 | 2000-11-09 | Alexandr Mikhailovich Ilyanok | Quantum-size electronic devices and operating conditions thereof |
| KR100468834B1 (en) * | 1998-10-09 | 2005-04-06 | 삼성전자주식회사 | Single electron transistor using oxidation process and manufacturing method |
| KR100446598B1 (en) * | 1997-09-04 | 2005-05-16 | 삼성전자주식회사 | A single electron tunneling device and a fabricating method thereof |
| JP2015209363A (en) * | 2014-04-28 | 2015-11-24 | 国立大学法人島根大学 | Re123 crystal film forming method |
-
1992
- 1992-03-31 JP JP4074838A patent/JPH05283759A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07240509A (en) * | 1994-01-19 | 1995-09-12 | Siemens Ag | Micro electron device |
| EP0750353A2 (en) * | 1995-06-23 | 1996-12-27 | Matsushita Electric Industrial Co., Ltd. | Single electron tunnel device and method for fabricating the same |
| EP0750353A3 (en) * | 1995-06-23 | 1997-07-02 | Matsushita Electric Ind Co Ltd | Single electron tunnel device and method for fabricating the same |
| US5731598A (en) * | 1995-06-23 | 1998-03-24 | Matsushita Electric Industrial Co. Ltd. | Single electron tunnel device and method for fabricating the same |
| KR100446598B1 (en) * | 1997-09-04 | 2005-05-16 | 삼성전자주식회사 | A single electron tunneling device and a fabricating method thereof |
| KR100468834B1 (en) * | 1998-10-09 | 2005-04-06 | 삼성전자주식회사 | Single electron transistor using oxidation process and manufacturing method |
| WO2000041247A3 (en) * | 1998-12-30 | 2000-11-09 | Alexandr Mikhailovich Ilyanok | Quantum-size electronic devices and operating conditions thereof |
| US6570224B1 (en) | 1998-12-30 | 2003-05-27 | Alexander Mikhailovich Ilyanok | Quantum-size electronic devices and operating conditions thereof |
| CN100367512C (en) * | 1998-12-30 | 2008-02-06 | 量子香港有限公司 | Quantum-size electronic devices and operating conditions thereof |
| JP2015209363A (en) * | 2014-04-28 | 2015-11-24 | 国立大学法人島根大学 | Re123 crystal film forming method |
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