JPH0256970A - Thin-film transistor and manufacture thereof - Google Patents
Thin-film transistor and manufacture thereofInfo
- Publication number
- JPH0256970A JPH0256970A JP20764188A JP20764188A JPH0256970A JP H0256970 A JPH0256970 A JP H0256970A JP 20764188 A JP20764188 A JP 20764188A JP 20764188 A JP20764188 A JP 20764188A JP H0256970 A JPH0256970 A JP H0256970A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- cdse
- film
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims 2
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims description 26
- 238000000137 annealing Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 abstract description 8
- 229910001120 nichrome Inorganic materials 0.000 abstract description 8
- 239000000969 carrier Substances 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、表示装置、例えばエレクトロルミネッセンス
パネルの駆動回路に用いられる大面積にわたり、均一な
特性を有する薄膜トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film transistor having uniform characteristics over a large area and used in a drive circuit for a display device, such as an electroluminescent panel.
従来の技術
従来のＣｄＳｅ薄膜トランジスタの構成を第２図に示す
。絶縁基板１上に、ゲート電極６が形成され、その上部
に、ゲート絶縁膜５を介してＣｄＳｅ膜３が形成されて
いる。ＣｄＳｅ膜３にはソース、ドレイン両電極２．４
が付与されている。2. Description of the Related Art The structure of a conventional CdSe thin film transistor is shown in FIG. A gate electrode 6 is formed on an insulating substrate 1, and a CdSe film 3 is formed on top of the gate electrode 6 with a gate insulating film 5 interposed therebetween. Both source and drain electrodes 2.4 are provided on the CdSe film 3.
has been granted.
ゲート電圧よって誘起されるキャリアの導通路は、ソー
ス電極２から、ドレイン電極４方向であり、絶縁基板１
に平行であった。The carrier conduction path induced by the gate voltage is from the source electrode 2 to the drain electrode 4, and from the insulating substrate 1.
was parallel to
発明が解決しようとする課題
ＣｄＳｅ膜３は多結晶膜であるため、結晶粒界が存在す
る。キャリアの導通路が結晶粒界を横切って、形成され
ると、キャリアが結晶粒界で散乱を受けるために、実効
的なキャリアの移動度が１０〜５０ｃｍ２／ｖｓとなり
、ＣｄＳｅ単結晶で報告されている〜６００ ｃ ｍ
２ ／ ｖ ｓという値に比べて、非常に小さ（なって
しまう。Problems to be Solved by the Invention Since the CdSe film 3 is a polycrystalline film, grain boundaries exist. When carrier conduction paths are formed across grain boundaries, the carriers are scattered at the grain boundaries, resulting in an effective carrier mobility of 10 to 50 cm2/vs, which is reported for CdSe single crystals. ~600 cm
It is very small compared to the value 2/vs.
本発明は、キャリアの結晶粒界での散乱の影響を少なく
シ、実効的なキャリアの移動度を大きくすることを目的
とする。An object of the present invention is to reduce the influence of scattering of carriers at grain boundaries and to increase effective carrier mobility.
課題を解決するための手段
絶縁基板上にソース（ドレイン）電極層、ＣｄＳｅ半導
体層、ドレイン（ソース）電極層を、順次、絶縁基板と
平行に、且つ、ＣｄＳｅ半導体層を挟む２層の電極が、
電気的接触を持たないように積層し、前記３層の１端面
を一致させるようにパターンニングし、その上に、前記
端面を覆う形状のゲート絶縁膜を形成し、更にその上に
、前記ゲート絶縁膜上でその下に前記端面を含み、前記
ソース（ドレイン） 、ＣｄＳｅ半導体層、ドレイン（
ソース）電極と電気的接触を持たない領域に、ゲート電
極を形成する。Means for Solving the Problem A source (drain) electrode layer, a CdSe semiconductor layer, and a drain (source) electrode layer are sequentially formed on an insulating substrate, parallel to the insulating substrate, and two layers of electrodes sandwiching the CdSe semiconductor layer. ,
The three layers are stacked so as not to have electrical contact, patterned so that one end surface of the three layers coincides with each other, a gate insulating film having a shape that covers the end surface is formed, and the gate The source (drain), the CdSe semiconductor layer, the drain (
A gate electrode is formed in a region that has no electrical contact with the source (source) electrode.
作用
上記の構成によれば、ＣｄＳｅ膜は基板に対して垂直に
、強いＣ軸配向性を持っており、基板に対して垂直方向
に結晶成長が起こりやすい。従って、基板に対して垂直
方向の結晶粒界の密度は基板に対して平行方向に比べて
？小さくなる。そのため、ＣｄＳｅ薄膜トランジスタの
キャリアの導通路が、基板に対して、垂直方向に形成さ
れるようにすることで、キャリアの結晶粒界での散乱の
影響を少な（なり、実効的なキャリアの移動度が大きく
なる。Effect: According to the above structure, the CdSe film has a strong C-axis orientation perpendicular to the substrate, and crystal growth tends to occur perpendicularly to the substrate. Therefore, what is the density of grain boundaries in the direction perpendicular to the substrate compared to the density in the direction parallel to the substrate? becomes smaller. Therefore, by forming the carrier conduction path in a CdSe thin film transistor in a direction perpendicular to the substrate, the influence of scattering of carriers at grain boundaries can be reduced (this reduces the effective carrier mobility). becomes larger.
実施例
以下、本発明の実施例を、図面を用いて説明する。第１
図は、本発明による薄膜トランジスタの構成である。Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1st
The figure shows the configuration of a thin film transistor according to the present invention.
第１図に示すように、ガラス基板１上に、膜厚が５０ｎ
ｍ程度のＮｉＣｒ層を、電子ビーム蒸着法で形成し、ソ
ース（ドレイン）電極２とする。As shown in FIG. 1, a film with a thickness of 50n
A NiCr layer having a thickness of about 100 m is formed by electron beam evaporation to form the source (drain) electrode 2.
その上に、半導体層として、ＣｄＳｅ膜３を５００ｎｍ
程度、抵抗加熱蒸着法で形成する。その上に、ドレイン
（ソース）電極４として、膜厚が５０ｎｍ程度のＮｉＣ
ｒ層を、電子ビーム蒸着法で形成する。その後、ＮｉＣ
ｒ層２）ＣｄＳｅ膜３、ＮｉＣｒ層４を、−度に逆スッ
パタエッチングを行い、前記３層の１端面を一致させる
ようにパターンニングを行う。前記端面を覆う形状に、
ゲート絶縁膜５として、例えば、スパッタリング法で作
製した２００ｎｍ程度の厚さのＡｌ−Ｔａ−０層を形成
する。更に、その上に、ゲート絶縁膜５上で、その下に
前記３層の端面を含み、前記ソース（ドレイン）電極２
）ＣｄＳｅ半導体層３、ドレイン（ソース）電極４と電
気的接触を持たない領域に、ゲート電極６を、３０ｎｍ
程度、抵抗加熱蒸着法で形成する。On top of that, a CdSe film 3 with a thickness of 500 nm is formed as a semiconductor layer.
It is formed by resistance heating vapor deposition method. On top of that, a NiC film with a thickness of about 50 nm is formed as a drain (source) electrode 4.
The r layer is formed by electron beam evaporation. After that, NiC
r layer 2) The CdSe film 3 and the NiCr layer 4 are subjected to reverse sputter etching at - degrees, and patterned so that one end surface of the three layers coincides with each other. In a shape that covers the end surface,
As the gate insulating film 5, for example, an Al-Ta-0 layer with a thickness of about 200 nm is formed using a sputtering method. Furthermore, the source (drain) electrode 2 is formed on the gate insulating film 5 and includes the end faces of the three layers below.
) A gate electrode 6 is formed with a thickness of 30 nm in a region that has no electrical contact with the CdSe semiconductor layer 3 and the drain (source) electrode 4.
It is formed by resistance heating vapor deposition method.
第３図は、絶縁基板に蒸着したＣｄＳｅ膜のＸ線回折を
示す図である。この図の唯一のピークは、ＣｄＳｅの（
００２）面のものである。これから明らかなように、Ｃ
ｄＳｅ膜は基板に対して垂直に、強いＣ軸配向性を持っ
ており、基板に対して垂直方向に結晶成長が起こりやす
い。そのため、基板に対して垂直方向の結晶粒界の密度
は基板に対して平行方向に比べて、小さ（なる。そのた
め、ＣｄＳｅ薄膜トランジスタのキャリアの導通路が、
基板に対して、垂直方向に形成されるようにすることで
、キャリアの結晶粒界での散乱の影響を少なくし、実効
的なキャリアの移動度を大きくすることができる。FIG. 3 is a diagram showing X-ray diffraction of a CdSe film deposited on an insulating substrate. The only peak in this figure is CdSe (
002) surface. As is clear from this, C.
The dSe film has strong C-axis orientation perpendicular to the substrate, and crystal growth tends to occur in the direction perpendicular to the substrate. Therefore, the density of grain boundaries in the direction perpendicular to the substrate is smaller than that in the direction parallel to the substrate.As a result, the carrier conduction path of the CdSe thin film transistor is
By forming it in a direction perpendicular to the substrate, it is possible to reduce the influence of carrier scattering at grain boundaries and increase the effective carrier mobility.
その後、アルゴンガス雰囲気中で、フラッシュアニール
を行う。通常のような長時間（例えば、３０分）のアニ
ールでは、電極材料であるＮｉＣｒが、ＣｄＳｅ膜へ拡
散し、第４図に示すようなトランジスタ特性となり、良
好な特性を示さない。また、アニールを行わないと、Ｃ
ｄ Ｓ ｅ膜とＮｉＣｒ膜の接触抵抗が大きくなり、第
５図に示すような特性となり、フラッシュアニールは、
単時間であるため、良好なオーミック接触が得られ、且
つ、拡散は小さい。フラッシュアニールを行ったときの
特性は、第６図に示すようなトランジスタ特性となり、
良好な特性を示す。この時のキャリアの移動度は、３０
０〜４００ ｃ ｍ ２ ／ ｖＢであった。Thereafter, flash annealing is performed in an argon gas atmosphere. When annealing is performed for a normal long time (for example, 30 minutes), NiCr, which is an electrode material, diffuses into the CdSe film, resulting in transistor characteristics as shown in FIG. 4, which do not exhibit good characteristics. Also, if annealing is not performed, C
The contact resistance between the dS e film and the NiCr film increases, resulting in the characteristics shown in Figure 5, and flash annealing
Since it is a single time, good ohmic contact can be obtained and diffusion is small. When flash annealing is performed, the transistor characteristics are as shown in Figure 6.
Shows good properties. The carrier mobility at this time is 30
It was 0-400 cm2/vB.
発明の効果
本発明によれば、移動度が大きい薄膜トランジスタが得
られるため、特に、スピードを要求される、各種トラン
ジスタ回路に広（活用できる。Effects of the Invention According to the present invention, since a thin film transistor with high mobility can be obtained, it can be widely used in various transistor circuits that require high speed.
第１図は、本発明の一実施例における薄膜トランジスタ
の構成を示す断面図、第２図は、従来の薄膜トランジス
タの構成を示す断面図、第３図は、ＣｄＳｅ膜のＸ線回
折パターンを示す図、第４図は、本発明にもとすく構造
の薄膜トランジスタの、長持間（〜３０分）のアニール
を行った後の特性図、第５図は、同薄膜トランジスタの
、アニールしなかった時の特性図、第６図は、同薄膜ト
ランジスタの、フラッシュアニールした後の特性図であ
る。
１・・絶縁基板、２・・ソース（ドレイン）電極、３・
・ＣｄＳｅ膜、４・・ソース（ドレイン）電極、５・・
ゲート絶縁膜、６・・ゲート電極。
代理人の氏名 弁理士 粟野重孝 ほか１名Ｃｃｌａｅ
順FIG. 1 is a cross-sectional view showing the structure of a thin film transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the structure of a conventional thin film transistor, and FIG. 3 is a view showing an X-ray diffraction pattern of a CdSe film. , Fig. 4 is a characteristic diagram of a thin film transistor having a structure according to the present invention after long-term annealing (~30 minutes), and Fig. 5 is a characteristic diagram of the same thin film transistor without annealing. 6 are characteristic diagrams of the same thin film transistor after flash annealing. 1. Insulating substrate, 2. Source (drain) electrode, 3.
・CdSe film, 4... Source (drain) electrode, 5...
Gate insulating film, 6...gate electrode. Name of agent: Patent attorney Shigetaka Awano and one other person Cclae
order
Claims (2)
ｅ半導体層、ドレイン（ソース）電極層を、順次、絶縁
基板と平行に、且つ、ＣｄＳｅ半導体層を挟む２層の電
極が、電気的接触を持たないように積層し、前記３層の
１端面を一致させるようにパターンニングし、その上に
、前記端面を覆う形状のゲート絶縁膜を形成し、更にそ
の上に、前記ゲート絶縁膜上でその下に前記端面を含み
、前記ソース（ドレイン）、ＣｄＳｅ半導体層、ドレイ
ン（ソース）電極と電気的接触を持たない領域に、ゲー
ト電極を形成したことを特徴とする薄膜トランジスタ。(1) Source (drain) electrode layer, CdS on an insulating substrate
The e-semiconductor layer and the drain (source) electrode layer are sequentially stacked parallel to the insulating substrate so that the two electrode layers sandwiching the CdSe semiconductor layer do not have electrical contact, and one end surface of the three layers is A gate insulating film having a shape that covers the end face is formed on the gate insulating film, and a gate insulating film is formed on the gate insulating film and includes the end face below the gate insulating film, and the source (drain) , a thin film transistor characterized in that a gate electrode is formed in a region having no electrical contact with a CdSe semiconductor layer and a drain (source) electrode.
、不活性ガス中でフラッシュアニールすることを特徴と
する薄膜トランジスタの製造方法。(2) A method for manufacturing a thin film transistor, comprising flash annealing the thin film transistor according to claim 1 in an inert gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20764188A JPH0256970A (en) | 1988-08-22 | 1988-08-22 | Thin-film transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20764188A JPH0256970A (en) | 1988-08-22 | 1988-08-22 | Thin-film transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0256970A true JPH0256970A (en) | 1990-02-26 |
Family
ID=16543147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20764188A Pending JPH0256970A (en) | 1988-08-22 | 1988-08-22 | Thin-film transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0256970A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003058723A1 (en) * | 2001-12-28 | 2003-07-17 | National Institute Of Advanced Industrial Science And Technology | Organic thin-film transistor and manufacturing method thereof |
| CN106024906A (en) * | 2016-07-18 | 2016-10-12 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate and liquid crystal display device |
-
1988
- 1988-08-22 JP JP20764188A patent/JPH0256970A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003058723A1 (en) * | 2001-12-28 | 2003-07-17 | National Institute Of Advanced Industrial Science And Technology | Organic thin-film transistor and manufacturing method thereof |
| US7138682B2 (en) | 2001-12-28 | 2006-11-21 | National Institute Of Advanced Industrial Science And Technology | Organic thin-film transistor and method of manufacturing the same |
| CN106024906A (en) * | 2016-07-18 | 2016-10-12 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate and liquid crystal display device |
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