JPH05152942A - Clock extract circuit - Google Patents
Clock extract circuitInfo
- Publication number
- JPH05152942A JPH05152942A JP3342367A JP34236791A JPH05152942A JP H05152942 A JPH05152942 A JP H05152942A JP 3342367 A JP3342367 A JP 3342367A JP 34236791 A JP34236791 A JP 34236791A JP H05152942 A JPH05152942 A JP H05152942A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pattern
- digital
- value
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はクロック抽出回路に関
し、特にデジタルＰＬＬを用いたクロック抽出回路に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock extraction circuit, and more particularly to a clock extraction circuit using a digital PLL.
【０００２】[0002]
【従来の技術】一般にこの種のクロック抽出回路では、
デジタルＰＬＬのＱにより同期引込み時間や同期保持能
力が決定されており、Ｑの値を低くすると同期引込み時
間が短縮でき、Ｑの値を高くすると同期保持能力が向上
される。従来のクロック抽出回路では、Ｑを一定の値に
固定して使用していた。2. Description of the Related Art Generally, in this type of clock extraction circuit,
The sync pull-in time and the sync hold capacity are determined by the Q of the digital PLL. The sync pull-in time can be shortened by decreasing the value of Q, and the sync hold capacity can be improved by increasing the value of Q. In the conventional clock extraction circuit, Q is fixed and used at a fixed value.
【０００３】[0003]
【発明が解決しようとする課題】このような従来のクロ
ック抽出回路では、Ｑの値が高いと同期引込みに要する
時間が長くなり、Ｑの値が低いと同期外れが起こり易く
なり、迅速でしかも安定したクロック抽出が得られない
という問題がある。本発明の目的は、クロックを迅速
に、かつ安定して抽出することを可能にしたクロック抽
出回路を提供することにある。In such a conventional clock extraction circuit, when the value of Q is high, the time required for pulling in the synchronization is long, and when the value of Q is low, the loss of synchronization is likely to occur, which is quick and quick. There is a problem that stable clock extraction cannot be obtained. An object of the present invention is to provide a clock extraction circuit that can extract a clock quickly and stably.
【０００４】[0004]
【課題を解決するための手段】本発明のクロック抽出回
路は、デジタル信号を入力して特定のパターンを検出す
るパターン検出回路と、このパターン検出回路の検出出
力に基づいてデジタルＰＬＬのＱを低値或いは高値に設
定する可変Ｑ回路とを備えるSUMMARY OF THE INVENTION A clock extraction circuit of the present invention includes a pattern detection circuit for inputting a digital signal to detect a specific pattern, and a digital PLL having a low Q value based on the detection output of the pattern detection circuit. With a variable Q circuit for setting a high value or a high value
【０００５】[0005]
【作用】特定のパターンを検出するまではデジタルＰＬ
ＬのＱの値を低くして同期引込み時間を短縮させ、検出
したときにはＱの値を高くして同期保持能力を向上させ
る。[Operation] Digital PL until a specific pattern is detected
The Q value of L is lowered to shorten the sync pull-in time, and when detected, the Q value is raised to improve the sync holding capability.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例のブロック構成図であり、
１は入力されるデータから特定のパターンを検出するパ
ターン検出回路、２はデジタルＰＬＬ、３はパターン検
出回路１でパターンが検出されたときにデジルタＰＬＬ
２のＱの値を変化させる可変Ｑ回路である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.
Reference numeral 1 is a pattern detection circuit for detecting a specific pattern from input data, 2 is a digital PLL, and 3 is a digital PLL when the pattern detection circuit 1 detects a pattern.
It is a variable Q circuit that changes the value of Q of 2.
【０００７】この構成では、入力されたデジタルデータ
に対して、パターン検出回路１が特定のデータパターン
を検出し、この特定のデータパターンが検出されると可
変Ｑ回路３へ検出情報を出力する。可変Ｑ回路３では、
パターン検出回路１からの検出情報が入力されるまでは
デジタルＰＬＬ２のＱの値を低く設定しておき、特定の
パターンの検出情報が入力されたときにはデジタルＰＬ
Ｌ２のＱの値を高くさせる。With this configuration, the pattern detection circuit 1 detects a specific data pattern in the input digital data, and when the specific data pattern is detected, the detection information is output to the variable Q circuit 3. In the variable Q circuit 3,
The Q value of the digital PLL 2 is set low until the detection information from the pattern detection circuit 1 is input, and when the detection information of a specific pattern is input, the digital PL is set.
Increase the Q value of L2.
【０００８】このため、デジタルＰＬＬは特定のデータ
パターンが検出される迄の間は、Ｑの値が低く設定され
て同期引込み時間が短縮される状態にある。したがっ
て、この状態ではデジタルデータに対して迅速に引込み
を行ない、クロック抽出を迅速に行う。そして、特定の
パターンが検出された後は、Ｑの値が高く設定されるた
め、抽出したクロックに対して同期保持能力が高めら
れ、同期状態を安定に保持することになる。Therefore, in the digital PLL, the value of Q is set low until the specific data pattern is detected, and the synchronization pull-in time is shortened. Therefore, in this state, the digital data is quickly pulled in and the clock is quickly extracted. Then, after the specific pattern is detected, the value of Q is set to a high value, so that the synchronization holding capability is enhanced with respect to the extracted clock, and the synchronization state is held stably.
【０００９】[0009]
【発明の効果】以上説明したように本発明は、特定のパ
ターンを検出するまではデジタルＰＬＬのＱの値を低く
して同期引込み時間を短縮させ、検出したときにはＱの
値を高くして同期保持能力を向上させるので、迅速でか
つ安定したクロック抽出が実現できる効果がある。As described above, according to the present invention, the Q value of the digital PLL is lowered to shorten the synchronization pull-in time until a specific pattern is detected, and when detected, the Q value is increased to synchronize. Since the holding capacity is improved, there is an effect that a quick and stable clock extraction can be realized.
【図１】本発明の一実施例のブロック構成図である。FIG. 1 is a block diagram of an embodiment of the present invention.
１ パターン検出回路 ２ デジタルＰＬＬ ３ 可変Ｑ回路 1 pattern detection circuit 2 digital PLL 3 variable Q circuit
Claims (1)
路において、デジタル信号を入力して特定のパターンを
検出するパターン検出回路と、このパターン検出回路の
検出出力に基づいて前記デジタルＰＬＬのＱを低値或い
は高値に設定する可変Ｑ回路とを備えることを特徴とす
るクロック抽出回路。1. A clock extraction circuit using a digital PLL, a pattern detection circuit for inputting a digital signal to detect a specific pattern, and a low Q value of the digital PLL based on a detection output of the pattern detection circuit. Alternatively, the clock extraction circuit is provided with a variable Q circuit that is set to a high value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3342367A JPH05152942A (en) | 1991-11-30 | 1991-11-30 | Clock extract circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3342367A JPH05152942A (en) | 1991-11-30 | 1991-11-30 | Clock extract circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05152942A true JPH05152942A (en) | 1993-06-18 |
Family
ID=18353181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3342367A Pending JPH05152942A (en) | 1991-11-30 | 1991-11-30 | Clock extract circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05152942A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20210076198A (en) | 2016-10-10 | 2021-06-23 | 다나카 기킨조쿠 고교 가부시키가이샤 | Catalyst for solid polymer fuel cell and method for producing same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01293718A (en) * | 1988-05-20 | 1989-11-27 | Hitachi Ltd | Phase locked loop circuit |
-
1991
- 1991-11-30 JP JP3342367A patent/JPH05152942A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01293718A (en) * | 1988-05-20 | 1989-11-27 | Hitachi Ltd | Phase locked loop circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20210076198A (en) | 2016-10-10 | 2021-06-23 | 다나카 기킨조쿠 고교 가부시키가이샤 | Catalyst for solid polymer fuel cell and method for producing same |
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