JPH05109922A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH05109922A
JPH05109922A JP3271629A JP27162991A JPH05109922A JP H05109922 A JPH05109922 A JP H05109922A JP 3271629 A JP3271629 A JP 3271629A JP 27162991 A JP27162991 A JP 27162991A JP H05109922 A JPH05109922 A JP H05109922A
Authority
JP
Japan
Prior art keywords
semiconductor device
external connection
hole
resin substrate
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3271629A
Other languages
English (en)
Inventor
Chikayuki Kato
周幸 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3271629A priority Critical patent/JPH05109922A/ja
Priority to EP92309278A priority patent/EP0539075A1/en
Publication of JPH05109922A publication Critical patent/JPH05109922A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】半導体素子の大きさを限定することなく、多ピ
ンで小型の半導体装置を提供する。 【構成】半導体素子１の下面に接着剤５及び絶縁シート
６を介して、樹脂基板８のスルーホールを有しており、
そのスルーホール内には外部接続用リードピン９が挿入
されている。樹脂基板８上の配線回路はスルーホールよ
り外側に向って形成されていて、半導体素子と電気的接
続するための素子接続用端子７は、スルーホールの外側
に有している。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置に係わり、特
にピングリッドアレイ型パッケージの半導体装置に関す
る。
【０００２】
【従来の技術】従来の半導体装置は図３に示すように、
外部接続用リードピン９が樹脂基板８に、格子状に設け
られたスルーホール１０に挿入されている。樹脂基板８
の表面には配線回路が形成されており、最内列外部リー
ドピンより内側に形成された素子接続用端子７と外部接
続用リードピンとは電気的に接続されている。素子接続
用端子７のさらに内側には接着剤５により固定された半
導体素子１が搭載されており、半導体素子１の上面は外
部から保護するために封止樹脂２により覆われている。
尚、図３において（Ａ）は断面図、（Ｂ）はその樹脂基
板の上面図である。
【０００３】
【発明が解決しようとする課題】この従来の半導体装置
では素子接続用端子が樹脂基板に設けた最内列のスルー
ホールより内側に形成されているため、最内列スルーホ
ールより大きな半導体素子を搭載することができない。
どうしても大きな半導体素子を搭載するためには、最内
列のスルーホールを無くして足りないピン数を最外列に
新たに設ける必要が生じ、外形サイズが大きくなってし
まうという問題があった。また、この種の外形サイズを
大きくしたパッケージは、ＪＥＤＥＣやＥＩＡＪ等でピ
ン数ごとに外形サイズが標準化されている為、特殊仕様
になってしまうという問題があった。
【０００４】
【課題を解決するための手段】本発明の半導体装置は複
数の外部接続用リードピンが樹脂基板に格子状に形成し
たスルーホール内に挿入されており、最内列に配列され
た外部接続用リードピンより少なくとも外側に素子接続
用端子を設け、半導体素子と接続している。
【０００５】
【実施例】次に本発明によって図面を参照して説明す
る。図１の（Ａ）は本発明の第１の実施例の半導体装置
の断面図である。樹脂基板８は、ガラス布エポキシやガ
ラス布ＢＴやガラス布ポリイミド等の積層板で成ってお
り、表裏両面には銅が張られている。また表裏の銅を導
通させるためにスルーホール１０を設けてめっきを行な
い、表裏面の銅をエッチングすることにより回路が形成
されている。スルーホール１０には、リン青銅、コバー
ル、４２ａｌｌｏｙ等に半田めっきが施こされている外
部接続用リードピン９が挿入されている。図１の（Ｂ）
は本発明の第１の実施例の樹脂基板の上面図である。外
部接続用リードピンを挿入するスルーホールが半導体素
子１の外形内に設けられており、半導体素子１と外部接
続用リードピン９とを電気的接続するための素子接続用
端子７がスルーホールの外側に形成されている。半導体
素子１は絶縁シート６を介して接着剤５に固定されてい
る。素子接続用端子７と半導体素子１を接続線３により
電気的接続させ、エポキシ系の封止樹脂２により接続線
及び半導体素子を外圧より保護する。
【０００６】図２の（Ａ）は本発明の第２の実施例の断
面図であり、図２の（Ｂ）は本発明の第２の実施例の樹
脂基板の上面図である。本実施例では、スルーホールと
スルーホールの周に素子接続用端子７を設けることによ
り、半導体素子の大きさを限定することなく搭載可能と
なる。
【０００７】
【発明の効果】以上説明したように本発明は、少なくと
も最内列に形成したスルーホールに挿入した外部接続用
リードピンより外側に素子接続用端子を有しているの
で、最内列ピンの配列サイズに関係なく又、パッケージ
サイズも規格外の大きなサイズにする必要なく、大きな
半導体素子を搭載することが可能となるという効果を有
する。
【図面の簡単な説明】
【図１】本発明の第１の実施例を示す縦断面図およびそ
の樹脂基板の上面図。
【図２】本発明の第２の実施例を示す縦断面図およびそ
の樹脂基板の上面図。
【図３】従来技術の半導体装置を示す縦断面図およびそ
の樹脂基板の上面図。
【符号の説明】
１ 半導体素子 ２ 封止樹脂 ３ 接続線 ４ 樹脂止め枠 ５ 接着剤 ６ 絶縁シート ７ 素子接続用端子 ８ 樹脂基板 ９ 外部接続用リードピン １０ スルーホール

Claims (2)

    【特許請求の範囲】
  1. 【請求項１】 複数の外部接続用リードピンを樹脂基板
    に格子状に形成したスルーホールに挿入して取付けた前
    記樹脂基板上に、半導体装置を搭載してなる半導体装置
    において、少なくとも最内列に形成された前記スルーホ
    ールに挿入された外部接続用リードピンより外側に素子
    接続用端子を有していることを特徴とする半導体装置。
  2. 【請求項２】 外部接続用リードピンがすべて半導体素
    子の外形内の下面に取付けられていることを特徴とする
    請求項１に記載の半導体装置。
JP3271629A 1991-10-21 1991-10-21 半導体装置 Pending JPH05109922A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3271629A JPH05109922A (ja) 1991-10-21 1991-10-21 半導体装置
EP92309278A EP0539075A1 (en) 1991-10-21 1992-10-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3271629A JPH05109922A (ja) 1991-10-21 1991-10-21 半導体装置

Publications (1)

Publication Number Publication Date
JPH05109922A true JPH05109922A (ja) 1993-04-30

Family

ID=17502739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3271629A Pending JPH05109922A (ja) 1991-10-21 1991-10-21 半導体装置

Country Status (2)

Country Link
EP (1) EP0539075A1 (ja)
JP (1) JPH05109922A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123919A (ja) * 1994-03-18 2007-05-17 Hitachi Chem Co Ltd 半導体パッケ−ジの製造法及び半導体パッケ−ジ
JP2008153708A (ja) * 1994-03-18 2008-07-03 Hitachi Chem Co Ltd 半導体パッケージの製造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5479319A (en) * 1992-12-30 1995-12-26 Interconnect Systems, Inc. Multi-level assemblies for interconnecting integrated circuits
TW272311B (ja) * 1994-01-12 1996-03-11 At & T Corp
ZA964464B (en) * 1995-06-01 1996-12-11 Siemens Ag Base board for an integrated electrical circuit module
US6384344B1 (en) 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts
EP1397031A3 (en) * 1996-09-12 2005-01-19 Ibiden Co., Ltd. Circuit board for mounting electronic parts
EP1814153A3 (en) * 1996-09-12 2008-09-24 Ibiden Co., Ltd. Circuit board for mounting electronic parts

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177759A (ja) * 1985-02-04 1986-08-09 Hitachi Micro Comput Eng Ltd 半導体装置
JPH02168662A (ja) * 1988-09-07 1990-06-28 Hitachi Ltd チップキャリア

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4887148A (en) * 1988-07-15 1989-12-12 Advanced Micro Devices, Inc. Pin grid array package structure
EP0351581A1 (de) * 1988-07-22 1990-01-24 Oerlikon-Contraves AG Hochintegrierte Schaltung sowie Verfahren zu deren Herstellung
US5077633A (en) * 1989-05-01 1991-12-31 Motorola Inc. Grounding an ultra high density pad array chip carrier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177759A (ja) * 1985-02-04 1986-08-09 Hitachi Micro Comput Eng Ltd 半導体装置
JPH02168662A (ja) * 1988-09-07 1990-06-28 Hitachi Ltd チップキャリア

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123919A (ja) * 1994-03-18 2007-05-17 Hitachi Chem Co Ltd 半導体パッケ−ジの製造法及び半導体パッケ−ジ
JP2008153708A (ja) * 1994-03-18 2008-07-03 Hitachi Chem Co Ltd 半導体パッケージの製造方法

Also Published As

Publication number Publication date
EP0539075A1 (en) 1993-04-28

Similar Documents

Publication Publication Date Title
US6603198B2 (en) Semiconductor structure having stacked semiconductor devices
JP3432982B2 (ja) 表面実装型半導体装置の製造方法
US6600221B2 (en) Semiconductor device with stacked semiconductor chips
US5451815A (en) Semiconductor device with surface mount package adapted for vertical mounting
JP3311914B2 (ja) チップ型発光ダイオード
JPH06224246A (ja) 半導体素子用高多端子化パッケージ
JP2716012B2 (ja) 半導体パッケージ及びその実装方法
JPH0234184B2 (ja)
US20060138630A1 (en) Stacked ball grid array packages
JP2568748B2 (ja) 半導体装置
JPH05109922A (ja) 半導体装置
JPH01261849A (ja) 半導体装置の製造方法
JP3150560B2 (ja) 半導体装置
JP2000183275A (ja) 半導体装置
JP2946361B2 (ja) 電子部品搭載用基板
US5345363A (en) Method and apparatus of coupling a die to a lead frame with a tape automated bonded tape that has openings which expose portions of the tape leads
JPH07297236A (ja) 半導体素子実装用フィルムと半導体素子実装構造
JPH11102991A (ja) 半導体素子搭載フレーム
KR100206975B1 (ko) 반도체 패키지
KR20020028038A (ko) 반도체 패키지의 적층 구조 및 그 적층 방법
JP3205272B2 (ja) 半導体装置
JPH04267361A (ja) リードレスチップキャリア
JP3063733B2 (ja) 半導体パッケージ
JP2626809B2 (ja) 電子部品搭載用基板のリードフレーム
KR100760953B1 (ko) 방열판을 구비한 비지에이 반도체 패키지

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19971021