JPH0469922A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0469922A JPH0469922A JP2183622A JP18362290A JPH0469922A JP H0469922 A JPH0469922 A JP H0469922A JP 2183622 A JP2183622 A JP 2183622A JP 18362290 A JP18362290 A JP 18362290A JP H0469922 A JPH0469922 A JP H0469922A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- layers
- film
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000010410 layer Substances 0.000 claims abstract description 124
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 150000001875 compounds Chemical class 0.000 claims abstract description 12
- 239000011247 coating layer Substances 0.000 claims abstract description 6
- 239000012808 vapor phase Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 18
- 239000013078 crystal Substances 0.000 abstract description 13
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 43
- 239000007789 gas Substances 0.000 description 17
- 230000035882 stress Effects 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 241000700560 Molluscum contagiosum virus Species 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 235000013842 nitrous oxide Nutrition 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置の改良に関し、特にシリコン基板上
に化合物半導体層を形成した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in semiconductor devices, and particularly to semiconductor devices in which a compound semiconductor layer is formed on a silicon substrate.
（従来の技術）
各種半導体基板のうち、シリコン基板は比較的安価で大
面積化が可能であるが、性能的および機能的には、Ｇａ
Ａｓなどの化合物半導体の方がすぐれている。ところが
、化合物半導体結晶は一般に高価であり、大面積で高品
質な結晶基板はほとんど得られないという問題かある。(Prior art) Among various semiconductor substrates, silicon substrates are relatively inexpensive and can be made large in area, but in terms of performance and functionality, silicon substrates are
Compound semiconductors such as As are superior. However, compound semiconductor crystals are generally expensive, and there is a problem in that large-area, high-quality crystal substrates are almost impossible to obtain.
そこで、近時は、両者の特徴をそれぞれ活かすべく、シ
リコン基板上にＧａＡｓ膜なとの化合物半導体層を形成
して各種デバイスを形成することが種々試みられている
。Therefore, in recent years, various attempts have been made to form various devices by forming a compound semiconductor layer such as a GaAs film on a silicon substrate in order to take advantage of the characteristics of both.
ところが、シリコン結晶と化合物半導体結晶とは、格子
定数が相違することから、シリコン基板上に化合物半導
体層を形成すると、格子定数の相違に起因する不整合転
位が必ず発生する。この転位は少数キャリアの再結合中
心として作用するため、少数キャリア寿命の大幅な減少
を引き起こす。However, since silicon crystals and compound semiconductor crystals have different lattice constants, when a compound semiconductor layer is formed on a silicon substrate, mismatch dislocations due to the difference in lattice constants inevitably occur. This dislocation acts as a recombination center for minority carriers, causing a significant decrease in minority carrier lifetime.
したがって、半導体発光素子などのように少数キャリア
を用いる半導体装置では、電気的および光学的にその性
能が著しく低下することになる。Therefore, in a semiconductor device that uses minority carriers, such as a semiconductor light emitting device, its electrical and optical performance will be significantly degraded.
したがって、このような不整合転位はできるだけ減少さ
せなければならない。Therefore, such misaligned dislocations must be reduced as much as possible.
不整合転位を低減させる一つの方法として、選択成長法
がある。すなわち、シリコン基板の表面にシリコン基板
の一部が露出するように酸化シリコン膜や窒化シリコン
膜を形成して、シリコン基板の露出部にだけＧａＡｓ膜
をエピタキシャル成長させることによって小面積単位で
内部応力をできるだけ発生させないようにして成長させ
る方法である。A selective growth method is one method for reducing mismatched dislocations. That is, by forming a silicon oxide film or a silicon nitride film on the surface of a silicon substrate so that a part of the silicon substrate is exposed, and epitaxially growing a GaAs film only on the exposed part of the silicon substrate, internal stress can be reduced in small area units. This is a method of growth that minimizes their occurrence.
しかしながら、このような選択成長法でＧａＡｓ膜を形
成したとしても、シリコン基板とＧａＡｓ膜との界面領
域では、ＳｔとＧａＡｓの格子定数の差により高密度の
不整合転位が発生し、その一部は成長中に成長方向に伝
播し、成長層を貫通する。特に成長終了後成長温度から
室温への降温中にシリコン基板とＧａＡｓ層間の熱膨張
係数の大きな相違による応力は成長方向への転位の伝播
を太き（作用するため、転位は表面近傍の活性層形成領
域まで到達する。ＳｉとＧａＡｓの界面領域で発生した
不整合転位の密度は約１０ ”ｃｍ−”であり、ＧａＡ
ｓを３μｍ積層した後のＧａＡｓ表面まで到達した転位
の密度は約１０”ｃｍ−”程度の高転位密度であること
が知られている。However, even if a GaAs film is formed by such a selective growth method, a high density of mismatched dislocations will occur in the interface region between the silicon substrate and the GaAs film due to the difference in lattice constant between St and GaAs, and some of them will be dislocated. propagates in the growth direction during growth and penetrates the growth layer. In particular, during cooling from the growth temperature to room temperature after growth, the stress due to the large difference in thermal expansion coefficient between the silicon substrate and the GaAs layer thickens the propagation of dislocations in the growth direction. The density of mismatched dislocations generated in the Si-GaAs interface region is approximately 10 cm, and the GaAs
It is known that the density of dislocations that have reached the GaAs surface after stacking s of 3 μm is as high as about 10 cm.
また、不整合転位を低減させる他の方法として、ＧａＡ
ｓ層内に、例えばＩｎＧａＡｓ膜とＧａＡｓ膜などから
成る歪超格子層を介挿することも提案されている。歪超
格子とは、格子定数が異なる２種類の半導体薄膜を交互
に積層した構造であり、−層毎の層厚が薄いので格子は
歪みながらも連続的に接続される性質を持つ。この不整
合により生じる格子の歪応力が転位線の伝播を阻止する
ように作用すると考えられている。すなわち、半導体の
上に格子定数の異なる半導体を極く薄く成長させた場合
、上層の半導体は歪応力を受けながらも下層の半導体層
の格子に連続的に接続する。この場合、下層の半導体も
歪応力を受けており下層の半導体を伝播する転位は、こ
の歪応力により横方向に曲げられて上層の半導体に伝播
する。そして上層の半導体の層厚が増すにともなって歪
応力も大きくなり、転位の曲がりも大きくなり、特に上
層の半導体の層厚を格子不整合転位を発生する臨界層厚
以下に制御することによって、相対する転位が繋がる機
会が多くなり、転位か低減する。In addition, as another method to reduce mismatch dislocations, GaA
It has also been proposed to insert a strained superlattice layer made of, for example, an InGaAs film and a GaAs film into the s-layer. A strained superlattice is a structure in which two types of semiconductor thin films with different lattice constants are alternately laminated, and since each layer is thin, the lattice has the property of being continuously connected even though it is strained. It is believed that the strain stress of the lattice caused by this mismatch acts to prevent the propagation of dislocation lines. That is, when semiconductors with different lattice constants are grown extremely thinly on top of a semiconductor, the upper semiconductor layer is continuously connected to the lattice of the lower semiconductor layer even though it is subjected to strain stress. In this case, the lower layer semiconductor is also subjected to strain stress, and dislocations propagating in the lower layer semiconductor are bent laterally by this strain stress and propagate to the upper layer semiconductor. As the layer thickness of the upper layer semiconductor increases, the strain stress also increases and the bending of dislocations also increases.In particular, by controlling the layer thickness of the upper layer semiconductor to below the critical layer thickness at which lattice mismatch dislocations occur, Opposite dislocations have more opportunities to connect, reducing the number of dislocations.
ところが、このような歪超格子層をＧａＡｓ膜に形成し
たとしても、シリコン基板とＧａＡｓ膜との間で発生し
た不整合転位は３ＸＩＯ”ｃｍ−”までしか低減させる
ことができず、実用化には支障がある。However, even if such a strained superlattice layer is formed in a GaAs film, the mismatch dislocations generated between the silicon substrate and the GaAs film can only be reduced to 3XIO cm-, making it difficult to put it into practical use. is a problem.
本発明は、このような背景のもとに案出されたものであ
り、シリコン基板上にＧａＡｓ膜をエピタキシャル成長
させたとき、ＧａＡｓ膜中に残留する転位密度を一層低
減させて高品質の半導体装置を提供することを目的とす
るものである。The present invention was devised against this background, and when a GaAs film is epitaxially grown on a silicon substrate, the dislocation density remaining in the GaAs film is further reduced, thereby producing a high quality semiconductor device. The purpose is to provide the following.
（発明の構成）
本発明によれば、シリコン基板上に透孔部を有する被覆
層を形成するとともに、この透孔部に化合物半導体層を
気相成長させた半導体装置において、前記化合物半導体
層内にＩｎｚ Ｇａｐ−ｘ Ａｓ層とＧａＡｓ層とから
成る歪超格子層、もしくはｒｎｙ Ｇａｐ−、Ａｓ層と
Ｉ ｎ ｔ Ｇ ａ ｌ−ｇ Ａ ｓ層（２≠ｙ）とか
ら成る歪超格子層を形成して成る半導体装置が提供され
、そのことにより上記目的が達成される。(Structure of the Invention) According to the present invention, in a semiconductor device in which a coating layer having a through hole is formed on a silicon substrate and a compound semiconductor layer is grown in the vapor phase in the through hole, A strained superlattice layer consisting of an Inz Gap-x As layer and a GaAs layer, or a strained superlattice layer consisting of an As layer and an IntGal-gAs layer (2≠y). A semiconductor device is provided, which achieves the above objects.
（作用）
上記のように構成することより、シリコン基板とＧａＡ
ｓ膜の界面領域で発生する歪応力をできるだけ減少させ
るとともに、発生した歪応力は歪超格子層で吸収するこ
とによって、貫通転位密度を低減させることができる。(Function) By configuring as above, silicon substrate and GaA
The threading dislocation density can be reduced by reducing the strain stress generated in the interface region of the s-film as much as possible, and by absorbing the generated strain stress in the strained superlattice layer.
（実施例） 以下、本発明を添付図面に基づき詳細に説明する。(Example) Hereinafter, the present invention will be explained in detail based on the accompanying drawings.
第１図は、本発明に係る半導体装置の一実施例を示す断
面図であり、】はシリコン基板、２はシリコン基板ｌ上
に形成されたＧａＡｓ膜である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor device according to the present invention, where ] is a silicon substrate and 2 is a GaAs film formed on the silicon substrate l.
前記シリコン基板１は（１００）面から（００１）面に
２°オフして切り出した単結晶シリコン基板で構成され
る。このシリコン基板ｌは、従来周知の単結晶製造法に
よって形成される。The silicon substrate 1 is composed of a single crystal silicon substrate cut out from the (100) plane to the (001) plane with an angle of 2°. This silicon substrate 1 is formed by a conventionally well-known single crystal manufacturing method.
前記シリコン基板ｌ上には、酸化シリコン膜（Ｓｉｎ）
または窒化シリコ”ン膜（ＳｉＮ）などから成る被覆層
２が形成されている。この被覆層２を酸化シリコン膜で
構成する場合は、シランガス（ＳｉＨ，）２笑気ガス（
Ｎ、Ｏ）とをグロ・・放電分解して堆積４るプラズマＣ
Ｖ １．’１法で形成される。また、窒化シリコン膜で
構成する場合は、。A silicon oxide film (Sin) is formed on the silicon substrate l.
Alternatively, a covering layer 2 made of a silicon nitride film (SiN) is formed. When the covering layer 2 is made of a silicon oxide film, silane gas (SiH, ) 2 laughing gas (
Plasma C deposited by decomposing N, O) and
V1. '1 method. Also, when it is composed of a silicon nitride film.
シランガスとアンＸニアガスとをグロー放電分解して堆
積するプラズマＣＶＤで形成される。It is formed by plasma CVD, which deposits silane gas and anxonia gas by glow discharge decomposition.
前記被覆層２には、シリコン基板１の一部が露出するよ
うに透孔部２ａが形成されている。この透孔部２ａは、
被覆層２Ｑ〕一部を！−［Ｆ／ Ｎ Ｉ−（４溶液なと
でエツチング除去することにより形成１さねる。この透
孔部２ａは、透孔部２ａの面積比と非透孔部どの面積比
が、２．５：１以上になるように形成される。なぜなら
、後述するＧａＡｓ膜を形成する際に、熱処理を加え転
位密度低減の効果を出すためである。また、透孔部２ａ
は、平面視した形状が矩形状であって、矩形状の一辺の
長さが５０へ・１００μｍに選ばれる。A through hole 2a is formed in the covering layer 2 so that a part of the silicon substrate 1 is exposed. This through hole 2a is
Covering layer 2Q] Part! -[F/N I-(4) Formation 1 is performed by etching and removing with a solution.The through-hole portion 2a is formed such that the area ratio of the through-hole portion 2a to that of the non-through-hole portion is 2.5. : 1 or more.This is because heat treatment is applied when forming a GaAs film, which will be described later, to achieve the effect of reducing dislocation density.
has a rectangular shape in plan view, and the length of one side of the rectangle is selected to be 50 to 100 μm.
面記透孔部２ａ内には、ＧａＡｓ膜：（か形成される。A GaAs film is formed in the through-hole portion 2a.
このＧａＡｓ膜３は、二段階成長法や熱り゛ビクル法な
どを適宜採用して厚み１〜３μｍ程度にＭＯＣＶＤ法な
どで形成される。ずなわぢ、ＭＯＣＶＤ装置内を９００
〜１０００°Ｃで−・旦加熱した後に、４００〜４５０
°Ｃに上゛げてＧａＡｓ膜３ａを厚み０．２〜１μｍ程
度成長させるとＪもに６００〜・７５０℃に上げてさら
に０．８〜２゜８μｍ程度Ｇ ａ Ａ ｓ膜３ｂを成長
させ（二段階成長法）、次に３００−９００℃で温度を
）下させ（熱勺イクル）、熱膨張係数に起因Ｊる内部応
力を発生させる。このように二段階成長法や熱→」ビク
ル法でＧ ａ Ａ ｓ膜３を形成することにより、シリ
コン基板ｌとＧａＡｓ膜３の界面領域で発生するミスフ
ィツト転位をある程度低減できるとともに、透孔部２ａ
を上述のような大きさに形成して透孔部２ａごとにＧａ
Ａｓ層３を堆積フることに、より、ＧａＡｓ結晶層３と
シリコン基板１どの間の熱膨張率の相違に基づく熱応力
は、ＧａＡｓ結晶層３の個々の占有面積によって規定さ
れる大きさどなり、シリコン基板１の与える影響はｉｌ
’及的に抑制され、熱応力に起因する転位の発生も抑制
される。This GaAs film 3 is formed by MOCVD or the like to a thickness of about 1 to 3 .mu.m by appropriately employing a two-step growth method, a thermal vehicle method, or the like. Zunawaji, inside the MOCVD equipment 900
After heating at ~1000°C, 400~450°C
When the temperature is raised to 600 to 750°C and the GaAs film 3a is grown to a thickness of about 0.2 to 1 μm, the temperature is raised to 600 to 750°C and the GaAs film 3b is further grown to a thickness of about 0.8 to 2.8 μm. (two-step growth method), then lower the temperature at 300-900° C. (thermal cycle) to generate internal stress due to the coefficient of thermal expansion. By forming the GaAs film 3 using the two-step growth method or the thermal →''vehicle method as described above, misfit dislocations occurring in the interface region between the silicon substrate l and the GaAs film 3 can be reduced to some extent, and the through-hole portions can be reduced to some extent. 2a
is formed to the above-mentioned size, and Ga is formed in each through hole 2a.
By depositing the As layer 3, the thermal stress due to the difference in thermal expansion coefficient between the GaAs crystal layer 3 and the silicon substrate 1 is reduced to a magnitude determined by the respective occupied areas of the GaAs crystal layer 3. , the influence of silicon substrate 1 is il
The generation of dislocations caused by thermal stress is also suppressed.
前記Ｃ； ａ Ａ ｓ Ｊｌ！！ ：３上に、歪超格＝
ｆ″−層４を形成”？る。この歪超格子層４は、Ｉ ｎ
ＩＩ Ｇ ａ ＋ −ｘ Ａ Ｓ層とＧａＡｓ層、も
しくはＩ ｎ ｙ Ｇ ａ ＋−ｓ、Ａ Ｓ層とＩ ｎ
ｍ Ｃｙ ａ ｌ−Ｉ Ａ Ｓ層ど４交１１：に複数
層積層し、で構成している。この場合、ぞれぞｒｉの層
の弾性限度を考慮しで、Ｉ ｎ、Ｇａ１−ｘ Ａ、ｓ層
おＪ、びＩ ｎｙ Ｇａｐ−、Ａｓ層は６０（］人程度
の厚みに、まｌ、・ＧａＡｓ層およびＩ ｎ、Ｇａ、、
−、、Ａｓ層は１００人程程度厚みに形成される。Ｉｎ
、Ｇａｎ□Ａｓ層どＧａＡｓ層、もしくはＩ ｎ ｙ
Ｇ ａ １１．Ａ ｓ層とＩｎｚＧａ１、Ａｓ層は、そ
ｔｌぞれ３層・−１゜層づつ程度積Ｎ４″ればよい。な
お“、ＩｎＧａＡｓ膜の混晶比ｘ、ｙ’、ｚは、Ｏ＜ｘ
、 ｙ、、ｚ （ｚ＃ｙ）く１の範囲で適宜選択する４
：とができる。、−のようなＩｎＧａＡｓ膜は、７２０
°Ｃの成長温度でキャリアガスとしてＨ，ガスを用いる
とともに、原料ガスとしてＡ ｓ Ｅ（２ガス、ＴＭＧ
ａ （Ｍａ）ガス、ＴＭＩｎ（Ｍａ）ガスを用いるＭ
ＯＣＶ １１１１）法により形成される。この場合、Ｔ
ＭＧａガスとＴＭＩｎガスどの流量比で・インジウム（
Ｉｎ）の混晶比ｘ、ｙ、ｚを決定すればよい。Said C; a As Jl! ! :3 on top, distorted super case =
f″-form layer 4”? Ru. This strained superlattice layer 4 is I n
II Ga + -x AS layer and GaAs layer, or In y Ga + -s, As layer and In
A plurality of layers are laminated at four intersections (11: m Cy a l-I A S layers). In this case, considering the elastic limit of each layer of ri, the In, Ga1-x A, s layers, J, and Iny Gap-, As layers have a thickness of about 60 (]). , ・GaAs layer and In, Ga, ,
-, The As layer is formed to a thickness of about 100 layers. In
, a GaAs layer such as a Gan□As layer, or an In y
G a 11. The As layer, InzGa1, and As layers should each have a thickness of approximately 3 layers and -1° layers each with a thickness of N4''.The mixed crystal ratios x, y', and z of the InGaAs film are O<x.
, y,, z (z#y) Select as appropriate within the range of 14
: Can be done. , - InGaAs films such as 720
At the growth temperature of °C, H gas is used as a carrier gas, and A s E (2 gas, TMG
M using a (Ma) gas and TMIn (Ma) gas
It is formed by the OCV 1111) method. In this case, T
At what flow rate ratio of MGa gas and TMIn gas?・Indium (
What is necessary is to determine the mixed crystal ratio x, y, z of In).
前記歪超格子層４十に、第２のＧａＡｓ層５を形成する
。この第２のＧ ａ Ａ ｓ Ｍ ５も例えばＭＯＣＶ
Ｄ法により形成される。A second GaAs layer 5 is formed on the strained superlattice layer 40. This second Ga As M 5 is also, for example, MOCV
Formed by method D.
なお、 ｆ−記のような歪超格子層４は、２層以上形成
してもよい。２層以上形成することにより、歪応力を分
断して吸収できることから、貫通転位密度はより低減で
きる。Note that two or more strained superlattice layers 4 as shown in f- may be formed. By forming two or more layers, the strain stress can be divided and absorbed, so that the threading dislocation density can be further reduced.
また、本発明に係る半導体装置は、例えば半導体発光素
子のバッファ層などどして用いら第１る。Further, the semiconductor device according to the present invention can be used, for example, as a buffer layer of a semiconductor light emitting device.
第２図は、本発明に係る他の実施例を示す断面図である
。この実施例によれば、シリコン基板１１」−５に、酸
化シリコン膜や窒化シリコン膜などから成る被覆層１２
を形成し、この被覆層１２中（，１、シリコン基板１１
の一部が露出するように酸化シリコン膜や窒化シリコン
膜の透孔部１２ａを形成するとともに、この透孔部１２
ａ内に、酸化シリコン膜や窒化シリコン膜が複数残った
島状部分１２ｂを形成したものである。この島状部分１
２ ｂが形成された透孔部１２ａで、ＧａＡｓ膜１：（
を、二段階成長法や熱サイクル法などを適宜採用して厚
み１〜３μｍ程度にＭＯＣＶＤ法などで形成する。すな
わち、ＭＯＣＶＤ装置内を９００〜１０００℃で一旦加
熱した後に、４００〜４５０°Ｃに下げてＧａＡｓ膜１
３ａを厚み０．２〜１μｍ程度成長させるとともに６０
０〜７５０℃に上げてさらにＧａＡｓ膜１３ｂを０．８
〜２．８μｍ程度成長させ（二段階成長法）、次に３０
０〜９００℃で温度を上下させ（熱サイクル）、熱膨張
係数に起因する内部応力を発生させる。このように島状
部分１２ｂを埋め込むようにＧａＡｓ層１３を形成する
と、島状部分１２ｂを越えて横方向に結晶が成長し、シ
リコン基板１１の界面から延びる貫通転位の影響が現れ
ず、貫通転位密度を格段に低減できる。FIG. 2 is a sectional view showing another embodiment of the present invention. According to this embodiment, a coating layer 12 made of a silicon oxide film, a silicon nitride film, etc. is provided on a silicon substrate 11''-5.
In this coating layer 12 (, 1, silicon substrate 11
A through hole 12a of the silicon oxide film or silicon nitride film is formed so that a part of the through hole 12a is exposed.
An island-like portion 12b in which a plurality of silicon oxide films or silicon nitride films remain is formed in the region a. This island-like part 1
2b is formed in the through hole 12a, the GaAs film 1:(
is formed by MOCVD or the like to a thickness of about 1 to 3 μm by appropriately employing a two-step growth method, a thermal cycle method, or the like. That is, after heating the inside of the MOCVD apparatus at 900 to 1000°C, the temperature is lowered to 400 to 450°C and the GaAs film 1 is heated.
3a to a thickness of about 0.2 to 1 μm and 60
The temperature is raised to 0 to 750°C, and the GaAs film 13b is further heated to 0.8°C.
~ 2.8 μm (two-step growth method), then 30 μm
The temperature is raised and lowered from 0 to 900°C (thermal cycle) to generate internal stress due to the coefficient of thermal expansion. When the GaAs layer 13 is formed so as to bury the island-shaped portion 12b in this way, crystals grow laterally beyond the island-shaped portion 12b, and the influence of threading dislocations extending from the interface of the silicon substrate 11 does not appear. Density can be significantly reduced.
前記ＧａＡｓ膜１３上に、歪超格子層１４を形成する。A strained superlattice layer 14 is formed on the GaAs film 13.
この歪超格子層１４は、ＩｎヨＧａ＋−ｘＡｓ層とＧａ
Ａｓ層、もしくはＩｎ、Ｇａ＋−ｙ Ａｓ層とＩｎ、Ｇ
ａ＋−、Ａｓ層とを交互に複数層積層して構成している
。この場合、それぞれの層の弾性限度を考慮して、Ｉｎ
ヨＧ ａ Ｉ−ｘ Ａ ｓ層およびＩｎアＧ ａ ＋−
アＡｓ層は６００人程程度厚みに、またＧａＡｓ層およ
びＩ ｎ ｘ Ｇ ａ ＋−ｘ Ａ ｓ層は１００人程
程度厚みに形成される。Ｉ ｎ ｘ Ｇ ａ ＋−エＡ
ｓ層とＧａＡｓ層、もしくはＩ ｎ ｙ Ｇ ａ ＋−
７ＡＳ層とＩｎ、Ｇａ＋−ｍ Ａｓ層は、それぞれ３層
〜１０層づつ程度積層すればよい。なお、ＩｎＧａＡｓ
膜の混晶比ｘ、ｙ、ｚは、０＜ｘ、ｙ、ｚ（ｚｆ＝ｙ）
＜１の範囲で適宜選択することかできる。このようなＩ
ｎＧａＡｓ膜は７２０°Ｃの成長温度で、キャリアガス
としてＨ２ガスを用いるとともに、原料ガスとしてＡ
ｓ Ｈｓガス、ＴＭＧ ａ（Ｍａ）ガス、ＴＭＩｎ （
Ｍａ）ガスを用いるＭＯＣＶＤ法により形成される。こ
の場合、ＴＭＧａガスとＴＭＩ ｎガスとの流量比でイ
ンジウム（Ｉｎ）の混晶比ｘ、ｙ、ｚを決定すればよい
。This strained superlattice layer 14 consists of an In layer, a Ga+−xAs layer, and a Ga layer.
As layer or In, Ga+-y As layer and In, G
It is constructed by alternately stacking a+- and As layers. In this case, considering the elastic limit of each layer, In
Yo G a I-x A s layer and In A G a +-
The As layer is formed to have a thickness of about 600 layers, and the GaAs layer and In x Ga + - x As layer are formed to have a thickness of about 100 layers. I n x Ga + - Air A
s layer and GaAs layer, or In y Ga +-
The 7AS layer and the In, Ga+-mAs layers may each be laminated in an amount of about 3 to 10 layers. In addition, InGaAs
The mixed crystal ratio x, y, z of the film is 0<x, y, z (zf=y)
It can be selected as appropriate within the range <1. I like this
The nGaAs film was grown at a growth temperature of 720°C using H2 gas as a carrier gas and A as a source gas.
s Hs gas, TMG a(Ma) gas, TMIn (
It is formed by the MOCVD method using Ma) gas. In this case, the mixed crystal ratios x, y, and z of indium (In) may be determined based on the flow rate ratio of TMGa gas and TMI n gas.
前記歪超格子層１４上に、第２のＧａＡｓ膜１５膜形５
する。この第２のＧａＡｓ層１３も例えばＭＯＣＶＤ法
により形成される。A second GaAs film 15 film type 5 is formed on the strained superlattice layer 14.
do. This second GaAs layer 13 is also formed, for example, by MOCVD.
（発明の効果）
以上のように、本発明に係る半導体装置によれば、シリ
コン基板上にシリコン基板の一部が露出するように被覆
層を形成するとともに、このシリコン基板上の露出部に
化合物半導体層を気相成長させた半導体装置において、
前記化合物半導体層内にＩ ｎ ！ Ｇ ａ ＋ −ｘ
Ａ ｓ層とＧａＡｓ層とから成る歪超格子層、もしく
はＩｎアＧ ａ ＋−ｙ Ａ ｓ層とＩ ｎ ｚ Ｇ
ａ Ｉ−ｇ Ａ ｓ層（Ｚ≠ｙ）とから成る歪超格子層
を形成して成ることから、シリコン基板上にＧａＡｓ膜
をエピタキシャル成長させたとき、ＧａＡｓ膜中に残留
する転位密度を一層低減させて高品質の半導体装置を提
供することができる。(Effects of the Invention) As described above, according to the semiconductor device of the present invention, a coating layer is formed on a silicon substrate so that a part of the silicon substrate is exposed, and a compound is formed on the exposed portion of the silicon substrate. In a semiconductor device in which a semiconductor layer is grown in a vapor phase,
I n ! in the compound semiconductor layer! G a + −x
A strained superlattice layer consisting of an A s layer and a GaAs layer, or a strained superlattice layer consisting of an InA Ga + -y As layer and an In z G
Since it forms a strained superlattice layer consisting of a I-g A s layer (Z≠y), when a GaAs film is epitaxially grown on a silicon substrate, the dislocation density remaining in the GaAs film can be further reduced. This makes it possible to provide high quality semiconductor devices.
第１図は本発明に係る半導体装置の一実施例を示す断面
図、第２図は他の実施例を示す断面図である。
３．１３ ：ＧａＡｓ層
４．１４ ：歪超格子層FIG. 1 is a sectional view showing one embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view showing another embodiment. 3.13: GaAs layer 4.14: Strained superlattice layer
Claims (1)
ともに、この透孔部に化合物半導体層を気相成長させた
半導体装置において、前記化合物半導体層内にＩｎ＿ｘ
Ｇａ＿１＿−＿ｘＡｓ層とＧａＡｓ層とから成る歪超格
子層、もしくはＩｎ＿ｙＧａ＿１＿−＿ｙＡｓ層とＩｎ
＿ｚＧａ＿１＿−＿ｚＡｓ層（ｚ≠ｙ）とから成る歪超
格子層を形成して成る半導体装置。In a semiconductor device in which a coating layer having a through hole is formed on a silicon substrate and a compound semiconductor layer is grown in the vapor phase in the through hole, In_x is formed in the compound semiconductor layer.
A strained superlattice layer consisting of a Ga_1_-_xAs layer and a GaAs layer, or an In_yGa_1_-_yAs layer and an In
A semiconductor device formed by forming a strained superlattice layer consisting of _zGa_1_-_zAs layers (z≠y).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2183622A JPH0469922A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2183622A JPH0469922A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0469922A true JPH0469922A (en) | 1992-03-05 |
Family
ID=16138997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2183622A Pending JPH0469922A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0469922A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5459331A (en) * | 1993-05-10 | 1995-10-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, heterojunction bipolar transistor, and high electron mobility transistor |
| JP2009177168A (en) * | 2007-12-28 | 2009-08-06 | Sumitomo Chemical Co Ltd | Semiconductor substrate and method of manufacturing the same, and electronic device |
-
1990
- 1990-07-10 JP JP2183622A patent/JPH0469922A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5459331A (en) * | 1993-05-10 | 1995-10-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, heterojunction bipolar transistor, and high electron mobility transistor |
| JP2009177168A (en) * | 2007-12-28 | 2009-08-06 | Sumitomo Chemical Co Ltd | Semiconductor substrate and method of manufacturing the same, and electronic device |
| US8772830B2 (en) | 2007-12-28 | 2014-07-08 | Sumitomo Chemical Company, Limited | Semiconductor wafer including lattice matched or pseudo-lattice matched buffer and GE layers, and electronic device |
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