JPH0469921A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0469921A JPH0469921A JP18362190A JP18362190A JPH0469921A JP H0469921 A JPH0469921 A JP H0469921A JP 18362190 A JP18362190 A JP 18362190A JP 18362190 A JP18362190 A JP 18362190A JP H0469921 A JPH0469921 A JP H0469921A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- layers
- film
- xas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 239000004065 semiconductor Substances 0.000 title claims description 32
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 abstract description 16
- 239000013078 crystal Substances 0.000 abstract description 9
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 29
- 150000001875 compounds Chemical class 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は半導体装置の改良に関し、特にシリコン基板上
に化合物半導体層を形成した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in semiconductor devices, and particularly to semiconductor devices in which a compound semiconductor layer is formed on a silicon substrate.
(従来の技術)
各種半導体基板のうち、シリコン基板は比較的安価で大
面積化か可能であるが、性能的および機能的には、Ga
Asなとの化合物半導体の方かすぐれている。ところか
、化合物半導体結晶は一般に高価であり、大面積で高品
質な結晶基板はほとんと得られないという問題かある。(Prior art) Among various semiconductor substrates, silicon substrates are relatively inexpensive and can be made large in area, but in terms of performance and functionality, silicon substrates are
Compound semiconductors such as As are superior. However, compound semiconductor crystals are generally expensive, and there is a problem in that large-area, high-quality crystal substrates are almost impossible to obtain.
そこで、近時は、両者の特徴をそれぞれ活かすべく、シ
リコン基板上にGaAs膜なとの化合物半導体層を形成
して各種デバイスを形成することか種々試みられている
。Therefore, recently, various attempts have been made to form various devices by forming a compound semiconductor layer such as a GaAs film on a silicon substrate in order to take advantage of the characteristics of both.
ところが、シリコン結晶と化合物半導体結晶とは、格子
定数か相違することから、シリコン基板上に化合物半導
体層を形成すると、格子定数の相違に起因する不整合転
位が必ず発生する。この転位は少数キャリアの再結合中
心どして作用するため、少数キャリア寿命の大幅な減少
を引き起こす。However, since silicon crystals and compound semiconductor crystals have different lattice constants, when a compound semiconductor layer is formed on a silicon substrate, mismatch dislocations due to the difference in lattice constants inevitably occur. Since this dislocation acts as a recombination center for minority carriers, it causes a significant decrease in minority carrier lifetime.
したかって、半導体発光素子なとのように少数キャリア
を用いる半導体装置では、電気的および光学的にその性
能か著しく低下することになる。Therefore, in a semiconductor device that uses minority carriers, such as a semiconductor light emitting device, its electrical and optical performance will be significantly degraded.
したかって、このような不整合転位はできるだけ、減少
させなければならない。Therefore, such misalignment dislocations must be reduced as much as possible.
不整合転位を低減させる方法の一つとして、二段階成長
法かある。すなわち、シリコン基板を900°C程度の
温度で熱処理した後、シリコン基板上f1mMOcVD
法あるいはMBE法r400’c程度の比較的低温で約
500人程度の厚みを有する予備堆積層を形成し、しか
る後通常のGaAsのエピタキシャル成長温度(600
〜750°C)まで基板を昇温した後、GaAs層層を
さらに所望厚みにまで成長させる方法である。One method for reducing mismatched dislocations is a two-step growth method. That is, after heat-treating the silicon substrate at a temperature of about 900°C, f1mMOcVD on the silicon substrate
A predeposition layer having a thickness of about 500 nm is formed at a relatively low temperature of about 400'c by the MBE method or MBE method, and then the normal GaAs epitaxial growth temperature (600°C) is formed.
In this method, the temperature of the substrate is raised to 750° C.), and then the GaAs layer is further grown to a desired thickness.
しかしながら、このような二段階成長法でGaAs層を
形成したとしても、シリコン基板とGaAs層との界面
領域では、SiとGaAsの格子定数の差により高密度
の不整合転位か発生し、その一部は成長中に成長方向に
伝播し、成長層を貫通する。特に成長終了後成長温度か
ら室温への降温中にシリコン基板とGaAs層間の熱膨
張係数の大きな相違による応力は成長方向への転位の伝
播を大きく作用するため、転位は表面近傍の活性層形成
領域まで到達する。SiとGaAsの界面領域で発生し
た不整合転位の密度は約1012cm−2であり、G
a A、 sを3μm積層した後のGaAS表面まで到
達した転位の密度は約10”cm−2程度の高転位密度
であることが知られている。However, even if a GaAs layer is formed using such a two-step growth method, a high density of mismatched dislocations will occur in the interface region between the silicon substrate and the GaAs layer due to the difference in lattice constant between Si and GaAs. The part propagates in the growth direction during growth and penetrates the growth layer. In particular, the stress caused by the large difference in thermal expansion coefficient between the silicon substrate and the GaAs layer during cooling from the growth temperature to room temperature after the completion of growth greatly affects the propagation of dislocations in the growth direction. reach up to. The density of mismatched dislocations generated in the Si-GaAs interface region is approximately 1012 cm-2, and G
It is known that the density of dislocations that have reached the GaAS surface after laminating 3 μm of A, s is a high dislocation density of about 10” cm −2 .
また、不整合転位を低減させる他の方法として、GaA
s層内に、例えばInGaAs膜とGaAs膜なとから
成る歪超格子層を介挿することも提案されている。歪超
格子とは、格子定数か異なる2種類の半導体薄膜を交互
に積層した構造であり、−層毎の層厚が薄いので格子は
歪みながらも連続的に接続される性質を持つ。この不整
合により生じる格子の歪応力が転位線の伝播を阻止する
ように作用すると考えられている。すなわち、半導体の
−Eに格子定数の異なる半導体を極く薄く成長させた場
合、上層の半導体は歪応力を受けなからも下層の半導体
層の格子に連続的に接続する。この場合、下層の半導体
も歪応力を受けており下層の半導体を伝播する転位は、
この歪応力により横方向に曲げられて上層の半導体に伝
播する。そして上層の半導体の層厚か増すにともなって
歪応力も大きくなり、転位の曲かりも大きくなり、特に
上層の半導体の層厚を格子不整合転位を発生する臨界層
厚以下に制御することによって、相対する転位か繋がる
機会か多くなり、転位か低減する。In addition, as another method to reduce mismatch dislocations, GaA
It has also been proposed to insert a strained superlattice layer made of, for example, an InGaAs film and a GaAs film into the s-layer. A strained superlattice is a structure in which two types of semiconductor thin films with different lattice constants are alternately laminated, and since each layer is thin, the lattice has the property of being continuously connected even though it is strained. It is believed that the strain stress of the lattice caused by this mismatch acts to prevent the propagation of dislocation lines. That is, when semiconductors having different lattice constants are grown extremely thinly at -E of a semiconductor, the upper semiconductor layer is continuously connected to the lattice of the lower semiconductor layer even though it is not subjected to strain stress. In this case, the underlying semiconductor is also subjected to strain stress, and the dislocations propagating through the underlying semiconductor are
This strain stress causes it to bend laterally and propagate to the upper semiconductor layer. As the thickness of the upper semiconductor layer increases, the strain stress also increases, and the bending of dislocations also increases. , the opportunities for opposing dislocations to connect increase, and the number of dislocations decreases.
しかし、このような歪超格子層をGaAs膜に形成した
としても、転位密度は3XIO’cm−2か限界であり
、それ以下に下げることはできなかった。However, even if such a strained superlattice layer is formed in a GaAs film, the dislocation density is at a limit of 3XIO'cm-2, and it has not been possible to reduce the dislocation density below that.
本発明は、このような背景のもとに案出されたものであ
り、シリコン基板上にGaAs膜をエピタキシャル成長
させたとき、G a、 A s膜中に残留する転位密度
を一層低減させて高品質の半導体装置を提供することを
目的とするものである。The present invention was devised against this background, and when a GaAs film is epitaxially grown on a silicon substrate, the dislocation density remaining in the Ga, As film can be further reduced to increase the density. The purpose is to provide quality semiconductor devices.
(発明の構成)
本発明によれば、シリコン基板上にGaAs膜を形成し
た半導体装置において、前記GaAs膜中に、In、G
ap−yAs層とGaAs層とから成る歪超格子層、も
しくはI n y G a +−アAs層とIn、Ga
p−z As層(z≠y)とから成る歪超格子層を複数
層形成して成る半導体装置が提供され、そのことにより
上記目的か達成される。(Structure of the Invention) According to the present invention, in a semiconductor device in which a GaAs film is formed on a silicon substrate, In, G and
A strained superlattice layer consisting of an ap-yAs layer and a GaAs layer, or an In, Ga
A semiconductor device is provided in which a plurality of strained superlattice layers including p-z As layers (z≠y) are formed, thereby achieving the above object.
(作用)
」二記のように構成することより、シリコン基板とGa
As膜の界面領域で発生した歪応力を一ケ所に集中させ
て吸収するのてはなく、複数ケ所に分断して吸収するこ
とから、貫通転位密度を低減させることができる。(Function) By configuring as described in section 2, the silicon substrate and Ga
Since the strain stress generated in the interface region of the As film is absorbed not by concentrating it in one place, but by dividing it into a plurality of places and absorbing it, the threading dislocation density can be reduced.
(実施例) 以下、本発明を添付図面に基づき詳細に説明する。(Example) Hereinafter, the present invention will be explained in detail based on the accompanying drawings.
第1図は、本発明に係る半導体装置の一実施例を示す断
面図であり、1はシリコン基板、2はシリコン基板1上
に形成されたGaAs膜である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, in which 1 is a silicon substrate and 2 is a GaAs film formed on the silicon substrate 1. In FIG.
前記シリコン基板1は(100)面から(001)面に
2°オフして切り出した単結晶シリコン基板で構成され
る。このシリコン基板1は、従来周知の単結晶製造法に
よって形成される。The silicon substrate 1 is composed of a single crystal silicon substrate cut out from the (100) plane to the (001) plane with an angle of 2°. This silicon substrate 1 is formed by a conventionally well-known single crystal manufacturing method.
前記シリコン基板l上には、GaAs膜2が形成される
。このGaAs膜2は、二段階成長法や熱サイクル法な
どを適宜採用して厚み1〜3μm程度にMOCVD法な
とで形成される。すなわち、MOCVD装置内を900
〜1000°Cで一旦加熱した後に、400〜450℃
に下げてGaAs膜を厚み0.2〜1μm程度成長させ
るとともに600〜650℃に上げてさらに0.8〜2
,8μm程度成長させ(二段階成長法)、次に300〜
900°Cて温度を上下させ(熱サイクル)、熱膨張係
数に起因する内部応力を発生させる。このように二段階
成長法や熱サイクル法てGaAs膜2を形成することに
より、シリコン基板1とGaAs膜2の界面領域で発生
するミスフィツト転位をある程度低減できる。A GaAs film 2 is formed on the silicon substrate l. This GaAs film 2 is formed to a thickness of about 1 to 3 μm by a MOCVD method or the like by appropriately employing a two-step growth method, a thermal cycle method, or the like. In other words, the inside of the MOCVD equipment is
After heating at ~1000°C, 400~450°C
The temperature was lowered to 600-650°C to grow a GaAs film to a thickness of about 0.2-1 μm, and the temperature was further increased to 0.8-2 μm.
, about 8 μm (two-step growth method), then about 300 μm
The temperature is raised and lowered (thermal cycle) at 900°C to generate internal stress due to the coefficient of thermal expansion. By forming the GaAs film 2 using the two-step growth method or the thermal cycle method as described above, misfit dislocations occurring in the interface region between the silicon substrate 1 and the GaAs film 2 can be reduced to some extent.
前記GaAs膜2上に、第1の歪超格子層3を形成する
。この第1の歪超格子層3は、InxGa+−8As層
3aとGaAs層3b、もしくはIn y G a +
−y A s層3aとI n t G a + −x
A 3層3bとを交互に複数層積層して構成している
。この場合、それぞれの層の弾性限度を考慮して、In
x Ga+−x As層3aおよびI n、 Ga+−
y AS層3aは600人程度の厚みに、末だGaAs
層3bおよびIn、Ga+−+ As層3bは100人
程度の厚みに形成される。I nx G a +−エA
s層3aとGaAs層3b、もしくはIn、Ga+yA
s層3aとInyGa1−yAs層3bは、それぞれ3
層〜10層づつ程度積層すればよい。なお、I n G
a A、 s膜の混晶比X、 y、Zは、oくx、y
、z (zfy)く1の範囲で適宜選択することができ
、Xは例えば0.001〜0.2程度に、またyおよび
Zは例えばその差が0.01〜0.0層程度で且つ中間
層部分に向かってXおよびyの比か徐々に大きくなるよ
うにoくy17(zf−y)<1の範囲で設定すること
が望まこのようなInGaAs膜は?20’C(7)成
ルて、キャリアガスとしてH2ガスを用いるに、原料ガ
スとしてAsHsガス、TMCa)ガス、TMIn (
Ma)ガスを用いVD法により形成される。この場合、
TM(JhスとTMrnガスとの流量比でインジウム(
n)の混晶比x、y、zを決定すればよい。A first strained superlattice layer 3 is formed on the GaAs film 2. This first strained superlattice layer 3 is composed of an InxGa+-8As layer 3a and a GaAs layer 3b, or an In y Ga +
-y As layer 3a and In t Ga + -x
It is constructed by laminating a plurality of A three layers 3b alternately. In this case, considering the elastic limit of each layer, In
x Ga+-x As layer 3a and In, Ga+-
y The AS layer 3a is about 600 layers thick and is made of GaAs.
The layer 3b and the In, Ga+-+ As layer 3b are formed to have a thickness of about 100 layers. Inx Ga +-Air A
s layer 3a and GaAs layer 3b, or In, Ga+yA
The s layer 3a and the InyGa1-yAs layer 3b each have a thickness of 3
What is necessary is to laminate about 10 layers to 10 layers at a time. In addition, I n G
a The mixed crystal ratios X, y, and Z of the A, s film are ox, y
. It is desirable to set the ratio of X and y in the range of y17(zf-y)<1 so that the ratio of X and y gradually increases toward the intermediate layer part.What kind of InGaAs film is this? 20'C(7), H2 gas is used as the carrier gas, AsHs gas, TMCa) gas, TMIn (
It is formed by the VD method using Ma) gas. in this case,
The flow rate ratio of TM (Jh gas and TMrn gas)
What is necessary is to determine the mixed crystal ratio x, y, z of n).
前記第1の歪超格子層3上に、第2のGaAs層4を形
成する。この第2のGaAs層4も例えばMOCVD法
により形成され、厚みが0.7μm程度となるように形
成される。A second GaAs layer 4 is formed on the first strained superlattice layer 3. This second GaAs layer 4 is also formed, for example, by the MOCVD method, and is formed to have a thickness of about 0.7 μm.
第2のGaAs層4」二に、第2の歪超格子層5を形成
する。この第2の歪超格子層5の構成も第1の歪超格子
層3と同一である。A second strained superlattice layer 5 is formed on the second GaAs layer 4. The structure of this second strained superlattice layer 5 is also the same as that of the first strained superlattice layer 3.
第2の歪超格子層5上に、第3のGaAs膜6を形成す
る。この第3のGaAs膜6の構成は、第2のGaAs
層4と同一である。A third GaAs film 6 is formed on the second strained superlattice layer 5. The structure of the third GaAs film 6 is similar to that of the second GaAs film 6.
Same as layer 4.
なお、上記のような歪超格子層3.5は、2層に限らず
、3層以上であってもよい。Note that the strained superlattice layer 3.5 as described above is not limited to two layers, but may be three or more layers.
また、本発明に係る半導体装置は、例えば半導体発光素
子のバッファ層などとして用いられる。Further, the semiconductor device according to the present invention is used, for example, as a buffer layer of a semiconductor light emitting device.
本発明等がシリコン基板上に、0.5μmの予備堆積層
と1.5μmの成長層から成る第1のGaAs膜を形成
した後、厚み600人のI n o、 o5G a O
,9aA S層と厚み100人の’nO,IGa。After the present invention et al. formed a first GaAs film on a silicon substrate consisting of a 0.5 μm pre-deposition layer and a 1.5 μm growth layer, a 600 nm thick GaAs film was formed.
, 9aA S layer and a thickness of 100'nO, IGa.
aAs層を交互に3層づつ形成して、厚み0. 7μm
の第2のGaAs膜を形成し、さらに上記と同一構成の
第2の歪超格子層、第3のGaAs膜、第3の歪超格子
層、および第4のGaAs膜を順次形成して第4のGa
AS膜上のEPDを調べたところ、6 X I O’
cm−’で、極めて結晶欠陥の少ないものであることか
認められた。Three aAs layers are formed alternately to a thickness of 0. 7μm
A second strained superlattice layer, a third GaAs film, a third strained superlattice layer, and a fourth GaAs film having the same configuration as above are formed in order. 4 Ga
When examining the EPD on the AS film, it was found that 6 X I O'
cm-', it was recognized that the crystal defects were extremely small.
(発明の効果)
以上のように、本発明に係る半導体装置によれば、シリ
コン基板上にGaAs膜を形成した半導体装置において
、前記GaAs膜中にIn、Ga1−yAs層とGaA
s層とから成る歪超格子層、もしくはIn、Ga+−y
As層とInyGa1−zAs層とから成る歪超格子
層を複数層形成して、シリコン基板とGaAs膜の界面
領域で発生した歪応力を複数ケ所に分断して吸収するこ
とから、貫通転位密度を低減させることができる。(Effects of the Invention) As described above, according to the semiconductor device of the present invention, in a semiconductor device in which a GaAs film is formed on a silicon substrate, an In, Ga1-yAs layer and a GaA layer are formed in the GaAs film.
Strained superlattice layer consisting of s layer, or In, Ga+-y
By forming multiple strained superlattice layers consisting of an As layer and an InyGa1-zAs layer, the strain stress generated at the interface region between the silicon substrate and the GaAs film is divided into multiple locations and absorbed, thereby reducing the threading dislocation density. can be reduced.
第1図は本発明に係る半導体装置の一実施例を示す断面
図である。
1 :シリコン基板
2.4.6、:GaAs膜
3 :第1の歪超格子層
5 :第2の歪超格子層
第1図FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. 1 : Silicon substrate 2.4.6, : GaAs film 3 : First strained superlattice layer 5 : Second strained superlattice layer FIG.
Claims (1)
おいて、前記GaAs膜中に、In_xGa_1_−_
xAs層とGaAs層とから成る歪超格子層、もしくは
In_yGa_1_−_yAs層とIn_zGa_1_
−_zAs層(z≠y)とから成る歪超格子層を複数層
形成して成る半導体装置。In a semiconductor device in which a GaAs film is formed on a silicon substrate, In_xGa_1_-_
A strained superlattice layer consisting of an xAs layer and a GaAs layer, or an In_yGa_1_-_yAs layer and In_zGa_1_
- A semiconductor device comprising a plurality of strained superlattice layers each including a _zAs layer (z≠y).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18362190A JPH0469921A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18362190A JPH0469921A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0469921A true JPH0469921A (en) | 1992-03-05 |
Family
ID=16138981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18362190A Pending JPH0469921A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0469921A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014175598A (en) * | 2013-03-12 | 2014-09-22 | Asahi Kasei Corp | Compound semiconductor laminate and semiconductor device |
-
1990
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2014175598A (en) * | 2013-03-12 | 2014-09-22 | Asahi Kasei Corp | Compound semiconductor laminate and semiconductor device |
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