JP3255798B2 - Compound semiconductor device and method of manufacturing the same - Google Patents
Compound semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP3255798B2 JP3255798B2 JP14607794A JP14607794A JP3255798B2 JP 3255798 B2 JP3255798 B2 JP 3255798B2 JP 14607794 A JP14607794 A JP 14607794A JP 14607794 A JP14607794 A JP 14607794A JP 3255798 B2 JP3255798 B2 JP 3255798B2
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- Japan
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- compound semiconductor
- semiconductor layer
- gallium arsenide
- layer
- lattice constant
- Prior art date
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Description
【０００１】[0001]
【産業上の利用分野】本発明は化合物半導体装置とその
形成方法に関し、特にシリコン基板上に化合物半導体層
を形成した化合物半導体装置とその形成方法に関する。The present invention relates to a compound semiconductor device and a method of forming the same, and more particularly, to a compound semiconductor device having a compound semiconductor layer formed on a silicon substrate and a method of forming the same.
【０００２】[0002]
【従来の技術】シリコン基板上に例えばガリウム砒素な
どの化合物半導体層を形成する場合、シリコン（Ｓｉ）
の格子定数が５．４３０９５Åであり、ガリウム砒素
（ＧａＡｓ）の格子定数が５．６５３３Åであることか
ら、この格子定数の相違に起因してガリウム砒素層に転
位が発生する。この転位はガリウム砒素層の表面まで連
続することもあり、この表面部まで連続する転位は転位
密度で表現される。このような転位は、デバイスを作成
した場合に、キャリヤの再結合中心となり、デバイス特
性を著しく損ねる。そこでこのような転位を低減させる
方法として、従来は、シリコン基板上に例えばＭＯＣＶ
Ｄ法（有機金属化学気相成長法）でガリウム砒素層を形
成する際に、ガリウム砒素層の形成途中で、成長を中断
させ、降温と昇温を繰り返すことによって転位を合体消
滅させる熱サイクル法や、ガリウム砒素とは格子定数が
若干異なるインジウム・ガリウム砒素層などから成る歪
超格子層をガリウム砒素層間に交互に複数層形成するこ
とによって表面への転位の伝播を中断させる歪超格子法
があった。この歪超格子法で用いられるインジウム・ガ
リウム砒素層は例えば１２０Å程度の厚みに形成され、
またガリウム砒素層は例えば８０Å程度の厚みに形成さ
れる。このようなガリウム砒素層とインジウム・ガリウ
ム砒素層をそれぞれ５〜１０層程度交互に形成する。ま
た転位低減効果を高めるために、これら熱サイクル法と
歪超格子法を組み合わせて用いることもあった。2. Description of the Related Art When a compound semiconductor layer such as gallium arsenide is formed on a silicon substrate, silicon (Si) is used.
Is 5.43095 ° and the lattice constant of gallium arsenide (GaAs) is 5.6533 °, so that dislocation occurs in the gallium arsenide layer due to the difference in the lattice constant. These dislocations may continue to the surface of the gallium arsenide layer, and the dislocations that continue to the surface portion are expressed by dislocation density. Such a dislocation becomes a recombination center of the carrier when the device is manufactured, and significantly degrades the device characteristics. Therefore, as a method for reducing such dislocations, conventionally, for example, MOCV
When forming a gallium arsenide layer by the method D (organic metal chemical vapor deposition), a thermal cycle method in which the growth is interrupted during the formation of the gallium arsenide layer and the dislocations are coalesced and eliminated by repeating the temperature decrease and the temperature increase. Also, the strain superlattice method of interrupting the propagation of dislocations to the surface by alternately forming a plurality of strained superlattice layers composed of an indium gallium arsenide layer with a lattice constant slightly different from that of gallium arsenide between gallium arsenide layers has been proposed. there were. The indium gallium arsenide layer used in the strained superlattice method is formed to a thickness of, for example, about 120 °,
The gallium arsenide layer is formed to a thickness of, for example, about 80 °. About 5 to 10 such gallium arsenide layers and about 5 to 10 indium gallium arsenide layers are alternately formed. Further, in order to enhance the dislocation reduction effect, the thermal cycling method and the strained superlattice method are sometimes used in combination.
【０００３】[0003]
【発明が解決しようとする課題】ところが従来の化合物
半導体装置では、熱サイクル法と歪超格子法を組み合わ
せて形成したとしてもガリウム砒素層の表面部近傍での
転位密度は１×１０6ｃｍ-2程度であった。However, in the conventional compound semiconductor device, the dislocation density in the vicinity of the surface of the gallium arsenide layer is 1 × 10 6 cm − even if the device is formed by a combination of the thermal cycling method and the strained superlattice method. It was about 2 .
【０００４】また歪超格子法では、ガリウム砒素層とイ
ンジウム・ガリウム砒素層の膜厚が例えば８０〜１２０
Åと極めて薄いために、かえって成膜に時間を要すると
いう問題があった。すなわちガリウム砒素層やインジウ
ム・ガリウム砒素層を形成する場合、その膜厚が薄くな
れば薄くなる程、その成長速度をより遅くしなければ膜
厚の制御ができない。そのために歪超格子層の形成に時
間がかかる。さらにガリウム砒素層とインジウム・ガリ
ウム砒素層を交互に形成する場合、各層間のガスの切替
え時間も必要なため、より成長時間がかかることにな
る。また膜厚が薄くなるほど、膜厚の制御が困難で再現
性が乏しくなる。In the strained superlattice method, the gallium arsenide layer and the indium gallium arsenide layer have a thickness of, for example, 80 to 120.
There was a problem that the film was rather time-consuming because it was extremely thin. That is, in the case of forming a gallium arsenide layer or an indium gallium arsenide layer, as the film thickness becomes thinner, the film thickness cannot be controlled unless the growth rate is made slower. Therefore, it takes time to form the strained superlattice layer. Further, when the gallium arsenide layer and the indium gallium arsenide layer are alternately formed, a longer time is required for switching the gas between the respective layers, so that a longer growth time is required. Also, as the film thickness becomes smaller, the control of the film thickness becomes more difficult and the reproducibility becomes poor.
【０００５】本発明はこのような問題点に鑑みてなされ
たものであり、化合物半導体層での転位密度を低減させ
た化合物半導体装置を提供すると共に、化合物半導体装
置を短時間に再現性よく形成できる化合物半導体装置の
形成方法を提供することを目的とする。The present invention has been made in view of the above problems, and provides a compound semiconductor device in which the dislocation density in a compound semiconductor layer is reduced, and a method of forming a compound semiconductor device in a short time with good reproducibility. It is an object of the present invention to provide a method for forming a compound semiconductor device that can be performed.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明に係る化合物半導体装置では、シリコン基板
上に化合物半導体層を設けた化合物半導体装置におい
て、前記化合物半導体層を第一の化合物半導体層、厚み
が４００〜１４００Åの第二の化合物半導体層、および
第三の化合物半導体層で構成すると共に、前記第一の化
合物半導体層と第二の化合物半導体層の格子定数を３≦
（ａ−ｂ）／ａ×１０3≦１０（但し、ａは第一の化合
物半導体層の格子定数、ｂは第二の化合物半導体層の格
子定数）に設定した。In order to achieve the above object, in a compound semiconductor device according to the present invention, in a compound semiconductor device having a compound semiconductor layer provided on a silicon substrate, the compound semiconductor layer is formed of a first compound semiconductor layer. A semiconductor layer, a second compound semiconductor layer having a thickness of 400 to 1400 °, and a third compound semiconductor layer, and a lattice constant of the first compound semiconductor layer and the second compound semiconductor layer is 3 ≦
(Ab) / a × 10 3 ≦ 10 (where a is the lattice constant of the first compound semiconductor layer and b is the lattice constant of the second compound semiconductor layer).
【０００７】また本発明に係る化合物半導体装置の形成
方法では、シリコン基板上に第一の化合物半導体層を成
長させて８００〜９００℃の温度で加熱した後に３５０
〜６００℃の温度で加熱し、この第一の化合物半導体層
上に、格子定数が３≦（ａ−ｂ）／ａ×１０3≦１０
（但し、ａは第一の化合物半導体層の格子定数、ｂは第
二の化合物半導体層の格子定数）の範囲内にある第二の
化合物半導体層を４００〜１４００Å成長させ、この第
二の化合物半導体層上に前記第一の化合物半導体層と同
一組成の第三の化合物半導体層を成長させる。In the method of forming a compound semiconductor device according to the present invention, a first compound semiconductor layer is grown on a silicon substrate and heated at a temperature of 800 to 900 ° C.
It is heated at a temperature of ℃ 600 ° C., and the lattice constant is 3 ≦ (ab) / a × 10 3 ≦ 10 on the first compound semiconductor layer.
(Where a is the lattice constant of the first compound semiconductor layer, and b is the lattice constant of the second compound semiconductor layer). A third compound semiconductor layer having the same composition as the first compound semiconductor layer is grown on the semiconductor layer.
【０００８】[0008]
【作用】上記のように構成すると第一の化合物半導体層
に発生した転位は、第一の化合物半導体層と第二の化合
物半導体層の界面、および第二の化合物半導体層と第三
の化合物半導体層の界面で吸収され、第三の化合物半導
体層表面での転位密度は１×１０6ｃｍ-2以下にまで低
減できる。With the above arrangement, dislocations generated in the first compound semiconductor layer are generated at the interface between the first compound semiconductor layer and the second compound semiconductor layer and between the second compound semiconductor layer and the third compound semiconductor layer. The dislocation density on the surface of the third compound semiconductor layer, which is absorbed at the interface between the layers, can be reduced to 1 × 10 6 cm −2 or less.
【０００９】また第二の化合物半導体層は、その膜厚が
４００〜１４００Åになるように形成することから、従
来の歪超格子層に比べて厚く、この第二の化合物半導体
層の膜厚の制御が容易になって、再現性よく短時間のう
ちに化合物半導体装置を形成でき、化合物半導体装置を
安価に製造できる。Further, since the second compound semiconductor layer is formed so as to have a thickness of 400 to 1400 °, it is thicker than a conventional strained superlattice layer and has a thickness smaller than that of the second compound semiconductor layer. Control becomes easy, a compound semiconductor device can be formed with good reproducibility in a short time, and the compound semiconductor device can be manufactured at low cost.
【００１０】[0010]
【実施例および参考例】以下、本発明の実施例と参考例
を添付図面に基づき詳細に説明する。図１は本発明に係
る化合物半導体装置の参考例を示す図であり、１はシリ
コン基板、２は第一の化合物半導体層、３は第二の化合
物半導体層、４は第三の化合物半導体層である。Embodiments and Reference Examples Embodiments and reference examples of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a view showing a reference example of a compound semiconductor device according to the present invention, wherein 1 is a silicon substrate, 2 is a first compound semiconductor layer, 3 is a second compound semiconductor layer, and 4 is a third compound semiconductor layer. It is.
【００１１】−参考例− 前記シリコン基板１は、（１００）面から例えば（００
１）面に２°オフして切り出した単結晶シリコン（Ｓ
ｉ）で構成される。この単結晶シリコンは格子定数が
５．４３０９５Åである。Reference Example The silicon substrate 1 is, for example, (00) from the (100) plane.
1) Single crystal silicon (S
i). This single crystal silicon has a lattice constant of 5.43095 °.
【００１２】このシリコン基板１上に、第一の化合物半
導体層２を形成する。この第一の化合物半導体層２は、
例えばガリウム砒素（ＧａＡｓ）などで構成され、例え
ば１９０００Å程度の厚みに形成する。ガリウム砒素の
格子定数は５．６５３３Åである。この第一の化合物半
導体層２をガリウム砒素で構成する場合、トリメチル・
ガリウム（ＴＭＧ）ガスとアルシン（ＡｓＨ3）ガスを
用いたＭＯＣＶＤ法で形成する。すなわち、シリコン基
板１上にガリウム砒素層２ａを１５０００Å形成し、８
００〜９００℃の温度で３分程度加熱した後に３５０〜
６００℃に降温して、さらに８００〜９００℃の温度で
３分程度加熱した後に３５０〜６００℃に降温する。こ
の加熱と降温を４回繰り返し、再びガリウム砒素層２ｂ
を４０００Å形成する。このようにガリウム砒素層２ａ
を形成して熱ストレスを加えることによって、シリコン
基板１とガリウム砒素２ａの格子定数の相違によって発
生する転位を合体させたり、横方向に逃がしたりした後
に、再びガリウム砒素層２ｂを形成する。高温での加熱
温度が９００℃以上になると、結晶より砒素が脱離し易
くなり、結晶性が悪くなる。一方８００℃以下では効果
が小さくなる。また降温の温度が６００℃以上では効果
が小さく、３５０℃以下に下げても効果は同じである。On the silicon substrate 1, a first compound semiconductor layer 2 is formed. This first compound semiconductor layer 2
For example, it is made of gallium arsenide (GaAs) or the like, and has a thickness of, for example, about 19000 °. The lattice constant of gallium arsenide is 5.6533 °. When the first compound semiconductor layer 2 is made of gallium arsenide,
It is formed by MOCVD using gallium (TMG) gas and arsine (AsH 3 ) gas. That is, a gallium arsenide layer 2a is formed on a silicon substrate 1 at 15000.degree.
After heating at a temperature of 00 to 900 ° C. for about 3 minutes,
The temperature is lowered to 600 ° C., further heated at a temperature of 800 to 900 ° C. for about 3 minutes, and then lowered to 350 to 600 ° C. This heating and cooling are repeated four times, and the gallium arsenide layer 2b is again formed.
Is formed at 4000 °. Thus, the gallium arsenide layer 2a
Is formed and thermal stress is applied, so that dislocations generated due to a difference in lattice constant between the silicon substrate 1 and the gallium arsenide 2a are combined or released in the lateral direction, and then the gallium arsenide layer 2b is formed again. When the heating temperature at a high temperature is 900 ° C. or higher, arsenic is easily desorbed from the crystal, and the crystallinity is deteriorated. On the other hand, when the temperature is 800 ° C. or less, the effect is reduced. The effect is small when the temperature is lowered to 600 ° C. or higher, and the effect is the same when the temperature is lowered to 350 ° C. or lower.
【００１３】この第一の化合物半導体層２上に、第二の
化合物半導体層３を設ける。この第二の化合物半導体層
３は、例えばインジウム・ガリウム砒素（ＩｎxＧａ1-x
Ａｓ）などで構成され、４００〜１４００Åの厚みに形
成される。この第二の化合物半導体層３をインジウム・
ガリウム砒素で構成する場合、トリメチル・インジウム
（ＴＭＩ）ガスとトリメチル・ガリウムガスとアルシン
ガスを用いたＭＯＣＶＤ法で形成する。On the first compound semiconductor layer 2, a second compound semiconductor layer 3 is provided. The second compound semiconductor layer 3 is made of, for example, indium gallium arsenide (In x Ga 1 -x
As) and is formed to a thickness of 400 to 1400 °. This second compound semiconductor layer 3 is made of indium
In the case of using gallium arsenide, it is formed by an MOCVD method using trimethyl indium (TMI) gas, trimethyl gallium gas, and arsine gas.
【００１４】インジウム・ガリウム砒素の格子定数はイ
ンジウム砒素（ＩｎＡｓ）とガリウム砒素の混晶比に依
存するが、インジウム砒素の格子定数６．０５８４Åと
ガリウム砒素の格子定数５．６５３３Åの差にインジウ
ム砒素の混晶比を乗算して、ガリウム砒素の格子定数に
加算することにより求まる。すなわちインジウム・ガリ
ウム砒素の格子定数は、６．０５８４Å〜５．６５３３
Åである。またインジウム・ガリウム砒素の格子定数が
−３≦（ａ−ｂ）／ａ×１０3≦−１０となるようにす
るためには、インジウム・ガリウム砒素中のインジウム
砒素の混晶比が０．０４１９〜０．１３９６となり、ガ
リウム砒素の混晶比が０．８６０４〜０．９５８１とな
る。インジウム・ガリウム砒素中のインジウム砒素の混
晶比を０．０４１９〜０．１３９６とするためには、ト
リメチル・インジウムガスとトリメチル・ガリウムガス
の流量比を１．８：１〜６．１：１に設定してインジウ
ム・ガリウム砒素層３を形成すればよい。The lattice constant of indium gallium arsenide depends on the mixed crystal ratio of indium arsenide (InAs) and gallium arsenide. , And added to the lattice constant of gallium arsenide. That is, the lattice constant of indium gallium arsenide is 6.0584Å to 5.6533.
Å. In order for the lattice constant of indium gallium arsenide to be −3 ≦ (ab) / a × 10 3 ≦ −10, the mixed crystal ratio of indium arsenide in indium gallium arsenide is 0.0419. ０．１0.1396, and the mixed crystal ratio of gallium arsenide is 0.8604５８0.9581. In order to set the mixed crystal ratio of indium arsenide in indium gallium arsenide to 0.0419 to 0.1396, the flow ratio of trimethyl indium gas to trimethyl gallium gas is set to 1.8: 1 to 6.1: 1. To form the indium gallium arsenide layer 3.
【００１５】この第二の化合物半導体層３上に、第三の
化合物半導体層４を形成する。この第三の化合物半導体
層４も、例えばガリウム砒素などで構成され、３５００
０Å程度の厚みに形成する。このガリウム砒素もトリメ
チル・ガリウムガスとアルシンガスを用いたＭＯＣＶＤ
法で形成する。On this second compound semiconductor layer 3, a third compound semiconductor layer 4 is formed. The third compound semiconductor layer 4 is also made of, for example, gallium arsenide, and
It is formed to a thickness of about 0 °. This gallium arsenide is also MOCVD using trimethyl gallium gas and arsine gas.
It is formed by a method.
【００１６】図２に、第一の化合物半導体層２をガリウ
ム砒素で構成し、第二の化合物半導体層３をインジウム
・ガリウム砒素で構成し、第三の化合物半導体層４をガ
リウム砒素で構成した場合のインジウム・ガリウム砒素
の膜厚と転位密度との関係を示す。なおインジウム・ガ
リウム砒素中のインジウム砒素とガリウム砒素の混晶比
は０．１：０．９であり、転位密度の測定箇所は、上層
のガリウム砒素層の表面部である。図２から判るよう
に、インジウム・ガリウム砒素の膜厚が４００〜１４０
０Åのとき、転位密度は１×１０6ｃｍ-2以下となり、
インジウム・ガリウム砒素が転位低減効果を有すること
が判る。これは転位低減効果が歪超格子の各層にあるの
ではなく、上下の界面、すなわち、最下層のインジウム
・ガリウム砒素層の下側、および最上層のインジウム・
ガリウム砒素層の上側の界面にしか無いためと考えられ
る。インジウム・ガリウム砒素層を一層にした場合で
も、このインジウム・ガリウム砒素層の格子定数と厚み
を所定範囲に設定すれば歪超格子層と同様若しくはそれ
以上の効果を得られることが判る。In FIG. 2, the first compound semiconductor layer 2 is made of gallium arsenide, the second compound semiconductor layer 3 is made of indium gallium arsenide, and the third compound semiconductor layer 4 is made of gallium arsenide. The relation between the film thickness of indium gallium arsenide and the dislocation density in the case is shown. The mixed crystal ratio of indium arsenide and gallium arsenide in indium gallium arsenide is 0.1: 0.9, and the dislocation density is measured at the surface of the upper gallium arsenide layer. As can be seen from FIG. 2, the film thickness of indium gallium arsenide is 400-140.
At 0 °, the dislocation density is 1 × 10 6 cm −2 or less,
It turns out that indium gallium arsenide has a dislocation reduction effect. This is because the dislocation reduction effect is not present in each layer of the strained superlattice, but in the upper and lower interfaces, that is, below the lowermost layer of indium gallium arsenide and the uppermost layer of indium.
This is probably because it exists only at the upper interface of the gallium arsenide layer. It can be seen that even when the indium gallium arsenide layer is formed as a single layer, if the lattice constant and the thickness of the indium gallium arsenide layer are set in a predetermined range, the same effect as or more than that of the strained superlattice layer can be obtained.
【００１７】−実施例− 上述した参考例のように、第一の化合物半導体層２と第
三の化合物半導体層４をガリウム砒素で構成し、第二の
化合物半導体層３をインジウム・ガリウム砒素で構成す
る場合、第二の化合物半導体層３は、格子定数が−３≦
（ａ−ｂ）／ａ×１０3≦−１０（ａは第一の化合物半
導体層の格子定数、ｂは第二の化合物半導体層の格子定
数）となるが、第一の化合物半導体層２と第三の化合物
半導体層４をＧａＡｓで構成し、第二の化合物半導体層
３をＧａＡｓＰで構成したり、ＩｎＰとＩｎＧａＰの組
み合わせで形成すると、第二の化合物半導体層３は、格
子定数が３≦（ａ−ｂ）／ａ×１０3≦１０となる。-Example-As in the above-mentioned reference example, the first compound semiconductor layer 2 and the third compound semiconductor layer 4 are composed of gallium arsenide, and the second compound semiconductor layer 3 is composed of indium gallium arsenide. When configured, the second compound semiconductor layer 3 has a lattice constant of -3 ≦
(Ab) / a × 10 3 ≦ −10 (a is the lattice constant of the first compound semiconductor layer, b is the lattice constant of the second compound semiconductor layer). When the third compound semiconductor layer 4 is made of GaAs and the second compound semiconductor layer 3 is made of GaAsP or formed of a combination of InP and InGaP, the second compound semiconductor layer 3 has a lattice constant of 3 ≦ (A−b) / a × 10 3 ≦ 10.
【００１８】また、上述した参考例の製造方法と同様
に、第二の化合物半導体層３は、格子定数が３≦（ａ−
ｂ）／ａ×１０3≦１０（ａは第一の化合物半導体層の
格子定数、ｂは第二の化合物半導体層の格子定数）とな
るように形成する。すなわち（ａ−ｂ）／ａ×１０3が
３未満の場合は、第一の化合物半導体層２と第二の化合
物半導体層３の格子定数が近似し、転位を低減させる効
果が少ない。また（ａ−ｂ）／ａ×１０3が１０を越え
る場合は、第一の化合物半導体層２と第二の化合物半導
体層３の格子定数が大きく相違し、新たな転位を発生さ
せる。Further, similarly to the manufacturing method of the above-described reference example, the second compound semiconductor layer 3 has a lattice constant of 3 ≦ (a−
b) / a × 10 3 ≦ 10 (a is the lattice constant of the first compound semiconductor layer, and b is the lattice constant of the second compound semiconductor layer). That is, when (ab) / a × 10 3 is less than 3, the lattice constants of the first compound semiconductor layer 2 and the second compound semiconductor layer 3 are close to each other, and the effect of reducing dislocations is small. When (ab) / a × 10 3 exceeds 10, the lattice constants of the first compound semiconductor layer 2 and the second compound semiconductor layer 3 are greatly different, and new dislocations are generated.
【００１９】[0019]
【発明の効果】以上のように、本発明に係る化合物半導
体装置では、シリコン基板上に第一の化合物半導体層、
厚みが４００〜１４００Åの第二の化合物半導体層、お
よび第三の化合物半導体層で構成すると共に、第一の化
合物半導体層と第二の化合物半導体層の格子定数を３≦
（ａ−ｂ）／ａ×１０3≦１０（但し、ａは第一の化合
物半導体層の格子定数、ｂは第二の化合物半導体層の格
子定数）に設定したことから、第一の化合物半導体層に
発生した転位は、第一の化合物半導体層と第二の化合物
半導体層の界面、および第二の化合物半導体層と第三の
化合物半導体層の界面で吸収され、第三の化合物半導体
層表面での転位密度は１×１０6ｃｍ-2以下にまで低減
できる。また、第二の化合物半導体層は、従来の歪超格
子層に比べて膜厚が厚く、膜厚の制御が容易になって、
再現性よく短時間のうちに化合物半導体装置を形成で
き、化合物半導体装置が安価になる。As described above, in the compound semiconductor device according to the present invention, the first compound semiconductor layer is formed on the silicon substrate.
A second compound semiconductor layer having a thickness of 400 to 1400 ° and a third compound semiconductor layer, and the lattice constant of the first compound semiconductor layer and the second compound semiconductor layer is 3 ≦
(Ab) / a × 10 3 ≦ 10 (where a is the lattice constant of the first compound semiconductor layer and b is the lattice constant of the second compound semiconductor layer). Dislocations generated in the layer are absorbed at the interface between the first compound semiconductor layer and the second compound semiconductor layer, and at the interface between the second compound semiconductor layer and the third compound semiconductor layer, and are transferred to the surface of the third compound semiconductor layer. Can be reduced to 1 × 10 6 cm −2 or less. In addition, the second compound semiconductor layer is thicker than the conventional strained superlattice layer, and the thickness can be easily controlled.
A compound semiconductor device can be formed in a short time with good reproducibility, and the compound semiconductor device becomes inexpensive.
【００２０】また本発明に係る化合物半導体装置の形成
方法では、シリコン基板上に第一の化合物半導体層を成
長させて８００〜９００℃の温度で加熱した後に３５０
〜６００℃の温度に降温し、この第一の化合物半導体層
上に、格子定数が３≦（ａ−ｂ）／ａ×１０3≦１０
（但し、ａは第一の化合物半導体層の格子定数、ｂは第
二の化合物半導体層の格子定数）の範囲内にある第二の
化合物半導体層を４００〜１４００Å成長させ、この第
二の化合物半導体層上に前記第一の化合物半導体層と同
一組成の第三の化合物半導体層を形成することから、第
一の化合物半導体層に発生した転位は、第一の化合物半
導体層と第二の化合物半導体層の界面、および第二の化
合物半導体層と第三の化合物半導体層の界面で吸収さ
れ、第三の化合物半導体層表面での転位密度は１×１０
6ｃｍ-2以下にまで低減できる。さらに第二の化合物半
導体層は、従来の歪超格子層に比べて厚いため、膜厚の
制御が容易になって、再現性よく短時間のうちに化合物
半導体装置を形成でき、化合物半導体装置を安価に製造
できる。In the method for forming a compound semiconductor device according to the present invention, a first compound semiconductor layer is grown on a silicon substrate and heated at a temperature of 800 to 900 ° C.
The temperature is lowered to a temperature of ６００600 ° C., and the lattice constant is 3 ≦ (ab) / a × 10 3 ≦ 10 on the first compound semiconductor layer.
(Where a is the lattice constant of the first compound semiconductor layer, and b is the lattice constant of the second compound semiconductor layer). Since a third compound semiconductor layer having the same composition as the first compound semiconductor layer is formed on the semiconductor layer, dislocations generated in the first compound semiconductor layer are caused by the first compound semiconductor layer and the second compound semiconductor layer. Absorbed at the interface between the semiconductor layer and the interface between the second compound semiconductor layer and the third compound semiconductor layer, the dislocation density on the surface of the third compound semiconductor layer is 1 × 10
It can be reduced to 6 cm -2 or less. Further, since the second compound semiconductor layer is thicker than the conventional strained superlattice layer, it is easy to control the film thickness, and the compound semiconductor device can be formed in a short time with good reproducibility. It can be manufactured at low cost.
【図１】本発明に係る化合物半導体装置の一実施例を示
す図である。FIG. 1 is a view showing one embodiment of a compound semiconductor device according to the present invention.
【図２】インジウム・ガリウム砒素の膜厚と転位密度と
の関係を示す図である。FIG. 2 is a diagram showing the relationship between the thickness of indium gallium arsenide and the dislocation density.
１・・・シリコン基板、２・・・第一の化合物半導体
層、３・・・第二の化合物半導体層、４・・・第三の化
合物半導体層DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... 1st compound semiconductor layer, 3 ... 2nd compound semiconductor layer, 4 ... 3rd compound semiconductor layer
Claims (2)
た化合物半導体装置において、前記化合物半導体層を第
一の化合物半導体層、厚みが４００〜１４００Åの第二
の化合物半導体層、および第三の化合物半導体層で構成
すると共に、前記第二の化合物半導体層の格子定数を３
≦（ａ−ｂ）／ａ×１０3≦１０（但し、ａは第一の化
合物半導体層の格子定数、ｂは第二の化合物半導体層の
格子定数）に設定したことを特徴とする化合物半導体装
置。1. A compound semiconductor device having a compound semiconductor layer provided on a silicon substrate, wherein the compound semiconductor layer is a first compound semiconductor layer, a second compound semiconductor layer having a thickness of 400 to 1400 °, and a third compound semiconductor layer. The second compound semiconductor layer has a lattice constant of 3
≦ (ab) / a × 10 3 ≦ 10 (where a is the lattice constant of the first compound semiconductor layer, and b is the lattice constant of the second compound semiconductor layer). apparatus.
を成長させて８００〜９００℃の温度で加熱した後に３
５０〜６００℃の温度で再加熱し、この第一の化合物半
導体層上に、格子定数が３≦（ａ−ｂ）／ａ×１０3≦
１０（但し、ａは第一の化合物半導体層の格子定数、ｂ
は第二の化合物半導体層の格子定数）の範囲内にある第
二の化合物半導体層を厚み４００〜１４００Å成長さ
せ、この第二の化合物半導体層上に前記第一の化合物半
導体層と同一組成の第三の化合物半導体層を成長させる
ことを特徴とする化合物半導体層の形成方法。2. After growing a first compound semiconductor layer on a silicon substrate and heating it at a temperature of 800 to 900 ° C.,
It is reheated at a temperature of 50 to 600 ° C., and a lattice constant of 3 ≦ (ab) / a × 10 3 ≦
10 (where a is the lattice constant of the first compound semiconductor layer, b
Grows a second compound semiconductor layer having a thickness within a range of 400 to 1400 ° within the range of (lattice constant of the second compound semiconductor layer), and has the same composition as the first compound semiconductor layer on the second compound semiconductor layer. A method for forming a compound semiconductor layer, comprising growing a third compound semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14607794A JP3255798B2 (en) | 1994-06-28 | 1994-06-28 | Compound semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14607794A JP3255798B2 (en) | 1994-06-28 | 1994-06-28 | Compound semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0817729A JPH0817729A (en) | 1996-01-19 |
| JP3255798B2 true JP3255798B2 (en) | 2002-02-12 |
Family
ID=15399595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14607794A Expired - Fee Related JP3255798B2 (en) | 1994-06-28 | 1994-06-28 | Compound semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3255798B2 (en) |
-
1994
- 1994-06-28 JP JP14607794A patent/JP3255798B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0817729A (en) | 1996-01-19 |
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