JPH0456365B2 - - Google Patents
Info
- Publication number
- JPH0456365B2 JPH0456365B2 JP18216783A JP18216783A JPH0456365B2 JP H0456365 B2 JPH0456365 B2 JP H0456365B2 JP 18216783 A JP18216783 A JP 18216783A JP 18216783 A JP18216783 A JP 18216783A JP H0456365 B2 JPH0456365 B2 JP H0456365B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- peak detection
- amplifier
- parallel
- diodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 29
- 239000003990 capacitor Substances 0.000 claims description 18
- 230000004069 differentiation Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Digital Magnetic Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
【発明の詳細な説明】
本発明は磁気カードリーダ等に用いられるデー
タ再生回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data reproducing circuit used in magnetic card readers and the like.
この種のデータ再生回路は磁気カード等の記録
媒体に記録されているデータを磁気ヘツドで読み
取り、その読み取り信号を増幅回路を介してピー
ク検出回路に入力してそのピーク検出を行うこと
によりデータ再生を行なつている。このデータ再
生回路におけるピーク検出回路は従来、第１図
イ，ロに示すようにコンデンサＣ１，Ｃ２、抵抗
Ｒ１、演算増幅器Ａ１及び２個の逆並列なダイオ
ードＤ１，Ｄ２又は２個ずつ直列に接続したもの
を逆並列に接続したダイオードＤ１１，Ｄ１２，
Ｄ２１，Ｄ２２で構成し、磁気ヘツドから増幅回
路を介して入力された読み取り信号Ａをコンデン
サＣ１により微分してダイオードＤ１，Ｄ２で定
まる電圧＋V1，−V2又はダイオードＤ１１，Ｄ
１２，Ｄ２１，Ｄ２２により定まる電圧＋V3，−
V4にクランプすることによつて読み取り信号Ａ
のピーク検出を行なつている。 This type of data reproducing circuit reads data recorded on a recording medium such as a magnetic card with a magnetic head, inputs the read signal to a peak detection circuit via an amplifier circuit, and performs data reproduction by detecting the peak. is being carried out. The peak detection circuit in this data reproducing circuit conventionally consists of capacitors C1 and C2, resistor R1, operational amplifier A1, and two anti-parallel diodes D1 and D2, or two connected in series, as shown in Figure 1 A and B. diodes D11, D12, which are connected in antiparallel.
The read signal A input from the magnetic head via the amplifier circuit is differentiated by the capacitor C1, and the voltages +V1, -V2 determined by the diodes D1 and D2 or the diodes D11 and D are generated.
Voltage +V3, - determined by 12, D21, D22
Read signal A by clamping to V4
We are performing peak detection.
しかし第１図イのように逆並列なクランプ用ダ
イオードＤ１，Ｄ２を１段構成にしたピーク検出
回路を有するデータ再生回路では第２図に示すよ
うにピーク検出回路の入力信号が大きいときにそ
の波形の歪（ノイズ等）により出力信号Ｂのサ
ドルレベルの落ち込みが大きくなり、出力信号
Ｂが本来のデータの位置とは異なつた位置でゼロ
クロスしてピークとして検出することによりデー
タ誤読の原因となる。但し第３図に示すようにピ
ーク検出回路の入力信号が小さいときにはそのピ
ーク検出が正確に行なわれる。また第１図ロのよ
うに逆並列なクランプ用ダイオードを２段構成に
したピーク検出回路を有するデータ再生回路では
第４図に示すようにピーク検出回路の入力信号Ａ
が大きくても出力信号Ｂのサドルレベルの落ち込
みがゼロレベルまで達しなくてピーク検出を正確
に行うことができるが、第５図に示すようにピー
ク検出回路の入力信号が小さいときには出力信号
Ｂの波形が鈍つてしまつて正確なピーク検出がで
きず、出力信号Ｂのゼロクロス位置がずれてジツ
ターの原因になる。 However, in a data reproducing circuit having a peak detection circuit configured with one stage of antiparallel clamping diodes D1 and D2 as shown in Figure 1A, when the input signal to the peak detection circuit is large as shown in Figure 2, Waveform distortion (noise, etc.) causes a large drop in the saddle level of output signal B, and output signal B crosses zero at a position different from the original data position and is detected as a peak, causing data misreading. . However, as shown in FIG. 3, when the input signal to the peak detection circuit is small, the peak detection is performed accurately. In addition, in a data reproducing circuit having a peak detection circuit configured with two stages of antiparallel clamping diodes as shown in FIG. 1B, the input signal A of the peak detection circuit is
Even if the saddle level of the output signal B is large, the drop in the saddle level of the output signal B does not reach the zero level, and peak detection can be performed accurately.However, as shown in FIG. The waveform becomes dull, making it impossible to accurately detect the peak, and the zero-crossing position of the output signal B shifts, causing jitter.
本発明はピーク検出回路の入力信号が大きくて
も小さくてもそのピーク検出を安定して行なうこ
とができるようにするためにピーク検出回路にお
いて大きな入力信号に対しては複数段のクランプ
用ダイオードが働いてピーク検出を行ない、小さ
な入力信号に対してはクランプ用ダイオードが１
段だけ働いてピーク検出を行うように構成したも
のである。 In order to be able to perform stable peak detection regardless of whether the input signal to the peak detection circuit is large or small, the present invention uses multiple stages of clamping diodes for large input signals in the peak detection circuit. The clamping diode performs peak detection for small input signals.
The configuration is such that peak detection is performed by operating only one stage.
以下図面を参照しながら本発明について実施例
をあげて説明する。 The present invention will be described below by way of examples with reference to the drawings.
第６図は本発明の一実施例を示し、図中１１は
磁気カード等の記録媒体からデータを読み取る磁
気ヘツド、１２は演算増幅器Ａ２、抵抗Ｒ２〜Ｒ
５、及びコンデンサＣ３，Ｃ４により構成された
初段の増幅回路、１３はピーク検出回路である。
このピーク検出回路１３はコンデンサＣ５及び抵
抗Ｒ６よりなる微分回路と、演算増幅器よりなる
反転増幅器Ａ３、抵抗Ｒ７，Ｒ８、ダイオードＤ
３〜Ｄ６、コンデンサＣ６，Ｃ７により構成され
ている。ダイオード３，Ｄ４及びコンデンサＣ６
の並列回路とダイオードＤ５，Ｄ６及びコンデン
サＣ７の並列回路は反転増幅器Ａ３の出力端子と
反転入力端との間に直列に接続され、それらの並
列回路の接続点、反転増幅器Ａ３の反転入力端と
上記微分回路の出力端との各間に抵抗Ｒ７，Ｒ８
が接続されている。ダイオードＤ３とＤ４、Ｄ５
とＤ６はそれぞれ逆並列に接続され、反転増幅器
Ａ３の非反転入力端には基準電圧が与えられる。
ここに抵抗Ｒ７は抵抗Ｒ８の約100倍に設定され、
コンデンサＣ７はコンデンサＣ６の約10倍に設定
されている。 FIG. 6 shows an embodiment of the present invention, in which 11 is a magnetic head for reading data from a recording medium such as a magnetic card, 12 is an operational amplifier A2, and resistors R2 to R2.
5 and a first stage amplifier circuit constituted by capacitors C3 and C4, and 13 a peak detection circuit.
This peak detection circuit 13 includes a differentiating circuit consisting of a capacitor C5 and a resistor R6, an inverting amplifier A3 consisting of an operational amplifier, resistors R7 and R8, and a diode D.
3 to D6, and capacitors C6 and C7. Diode 3, D4 and capacitor C6
A parallel circuit of diodes D5, D6 and a capacitor C7 is connected in series between the output terminal and the inverting input terminal of the inverting amplifier A3, and the connection point of these parallel circuits is connected to the inverting input terminal of the inverting amplifier A3. Resistors R7 and R8 are connected to the output terminal of the above differentiation circuit.
is connected. Diodes D3 and D4, D5
and D6 are connected in antiparallel to each other, and a reference voltage is applied to the non-inverting input terminal of the inverting amplifier A3.
Here, the resistor R7 is set to about 100 times the resistor R8,
Capacitor C7 is set approximately 10 times as large as capacitor C6.
この実施例では磁気カード等に記録されている
データが磁気ヘツド１１により読み取られ、その
読み取り信号が増幅回路１２を介してピーク検出
回路１３に入力される。ピーク検出回路１３にお
いては入力信号ＡをコンデンサＣ５及び抵抗Ｒ６
よりなる微分回路で微分してクランプすることに
よりピーク検出を行うが、入力信号Ａが比較的小
さい時にはクランプ用ダイオードＤ３〜Ｄ６が入
力信号にとつて大きな抵抗として作用するために
上記微分回路の出力信号は抵抗Ｒ８を通らずに抵
抗Ｒ７と、クランプ用ダイオードＤ３，Ｄ４及び
コンデンサＣ６の並列回路よりなるクランプ回路
を通つて出力端に出力されることにより電圧＋
V5，−V6でクランプされる（第７図の右側部分
参照）。このときクランプ用ダイオードが１段Ｄ
３，Ｄ４だけ働くから入力信号Ａが小さくてもピ
ーク検出が正確に行なわれる。一方、入力信号Ａ
が大きい時には入力信号にとつてダイオードＤ３
〜Ｄ６が小さな抵抗として作用するために微分回
路の出力信号が小さい抵抗Ｒ８とクランプ用ダイ
オードＤ３〜Ｄ６及びコンデンサＣ６，Ｃ７を介
して出力端に出力され、つまり反転増幅器Ａ３、
抵抗Ｒ８、ダイオードＤ３〜Ｄ６及びコンデンサ
Ｃ６，Ｃ７よりなる回路で電圧＋V7，−V8にク
ランプされる（第７図の左側部分参照）。このと
きクランプ用ダイオードが２段Ｄ３〜Ｄ６働くか
ら入力信号Ａが大きくても正確なピーク検出が行
なわれる。 In this embodiment, data recorded on a magnetic card or the like is read by a magnetic head 11, and the read signal is input to a peak detection circuit 13 via an amplifier circuit 12. In the peak detection circuit 13, the input signal A is connected to a capacitor C5 and a resistor R6.
Peak detection is performed by differentiating and clamping with a differentiating circuit, but when the input signal A is relatively small, the clamping diodes D3 to D6 act as large resistances to the input signal, so the output of the differentiating circuit is The signal does not pass through resistor R8, but passes through a clamp circuit consisting of resistor R7, clamping diodes D3, D4, and capacitor C6 in parallel, and is output to the output terminal, so that the voltage +
It is clamped at V5 and -V6 (see the right part of Figure 7). At this time, the clamp diode is 1 stage D
3 and D4, peak detection can be performed accurately even if the input signal A is small. On the other hand, input signal A
When the input signal is large, the diode D3
~D6 acts as a small resistance, so the output signal of the differentiating circuit is outputted to the output terminal via the small resistance R8, clamping diodes D3 to D6, and capacitors C6 and C7, that is, the inverting amplifier A3,
It is clamped to voltages +V7 and -V8 by a circuit consisting of resistor R8, diodes D3 to D6, and capacitors C6 and C7 (see the left part of FIG. 7). At this time, since two stages of clamping diodes D3 to D6 operate, accurate peak detection can be performed even if the input signal A is large.
この実施例においてコンデンサＣ６，Ｃ７の容
量の設定によりクランプ用ダイオードが２段働い
ているときと１段だけ働いているときとで周波数
特性を変えることができる。即ちクランプ用ダイ
オードが２段働いているときに入力信号Ａにおけ
るデータの基本周波数帯よりわずかに高い周波数
以上でゲインが落ち込むようにコンデンサＣ７の
容量を設定してノイズをカツトすることが可能と
なり、ノイズによる誤読の可能性をさらに低くす
ることができる。またクランプ用ダイオードが１
段だけ働いているときに入力信号におけるデータ
の基本周波数帯よりある程度高い周波数までゲイ
ンが伸びる（落ちない）ようにコンデンサＣ６の
容量を設定しておけばノイズ成分に近い微小なピ
ークも拾うことができ、より正確なピーク検出を
行うことができる。 In this embodiment, by setting the capacitances of the capacitors C6 and C7, the frequency characteristics can be changed between when the clamping diodes are working in two stages and when only one stage is working. In other words, when the two stages of clamping diodes are working, it is possible to cut noise by setting the capacitance of the capacitor C7 so that the gain drops at a frequency slightly higher than the fundamental frequency band of the data in the input signal A. The possibility of misreading due to noise can be further reduced. Also, the clamp diode is 1
If the capacitance of capacitor C6 is set so that the gain extends (does not fall) to a frequency somewhat higher than the fundamental frequency band of the data in the input signal when only the stage is working, it is possible to pick up minute peaks close to noise components. This allows for more accurate peak detection.
以上のように本発明によればピーク検出回路に
おいて大きな入力信号に対しては複数段のクラン
プ用ダイオードが働き、小さな入力信号に対して
はクランプ用ダイオードが１段だけ働くようにし
たので、ピーク検出回路の入力信号が大きくても
小さくてもそのピーク検出を安定して行うことが
できる。 As described above, according to the present invention, in the peak detection circuit, multiple stages of clamping diodes work for large input signals, and only one stage of clamping diodes works for small input signals. Regardless of whether the input signal to the detection circuit is large or small, its peak can be detected stably.
第１図イ，ロは従来のデータ再生回路における
ピーク検出回路の各例を示す回路図、第２図〜第
５図は同ピーク検出回路の入出力波形を示す波形
図、第６図は本発明は本発明の一実施例を示す回
路図、第７図は同実施例の入出力波形を示す波形
図である。
Ａ３……反転増幅器、Ｄ３〜Ｄ６……クランプ
用ダイオード、Ｃ５〜Ｃ７……コンデンサ、Ｒ６
〜Ｒ８……抵抗。
Figures 1A and 1B are circuit diagrams showing examples of peak detection circuits in conventional data reproducing circuits. Figures 2 to 5 are waveform diagrams showing input and output waveforms of the same peak detection circuits. The present invention is a circuit diagram showing one embodiment of the present invention, and FIG. 7 is a waveform diagram showing input and output waveforms of the same embodiment. A3...Inverting amplifier, D3-D6...Clamp diode, C5-C7...Capacitor, R6
~R8...Resistance.
Claims (1)
介してピーク検出回路に送り上記読み取り信号の
ピーク検出を行なつて記録データの再生を行なう
ようになされたデータ再生回路において、前記増
幅回路の出力信号が入力される微分回路と、この
微分回路の出力信号が反転入力端に入力される反
転増幅器と、この反転増幅器の出力端と反転入力
端との間に直列に接続された複数組の、コンデン
サと並列に１対の逆並列なダイオードを接続した
並列回路と、この複数組の並列回路の接続点と前
記微分回路の出力端との間に接続された抵抗とを
用いて前記ピーク検出回路を構成したことを特徴
とするデータ再生回路。1. In a data reproducing circuit configured to send a read signal from a magnetic head to a peak detection circuit via an amplifier circuit, detect the peak of the read signal, and reproduce recorded data, the output signal of the amplifier circuit is A differentiating circuit to be inputted, an inverting amplifier to which the output signal of this differentiating circuit is inputted to an inverting input terminal, and a plurality of sets of capacitors connected in series between the output terminal of this inverting amplifier and the inverting input terminal. The peak detection circuit is configured using a parallel circuit in which a pair of anti-parallel diodes are connected in parallel, and a resistor connected between the connection point of the plurality of parallel circuits and the output end of the differentiation circuit. A data reproducing circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18216783A JPS6076056A (en) | 1983-09-30 | 1983-09-30 | Data reproducing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18216783A JPS6076056A (en) | 1983-09-30 | 1983-09-30 | Data reproducing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6076056A JPS6076056A (en) | 1985-04-30 |
| JPH0456365B2 true JPH0456365B2 (en) | 1992-09-08 |
Family
ID=16113516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18216783A Granted JPS6076056A (en) | 1983-09-30 | 1983-09-30 | Data reproducing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6076056A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6218118A (en) * | 1985-07-17 | 1987-01-27 | Matsushita Electric Ind Co Ltd | Viterbi decoder |
| JP2007324200A (en) * | 2006-05-30 | 2007-12-13 | Yazaki Corp | Circuit board and electrical connection box equipped therewith |
-
1983
- 1983-09-30 JP JP18216783A patent/JPS6076056A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6076056A (en) | 1985-04-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |