JPH0685165A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0685165A
JPH0685165A JP23382592A JP23382592A JPH0685165A JP H0685165 A JPH0685165 A JP H0685165A JP 23382592 A JP23382592 A JP 23382592A JP 23382592 A JP23382592 A JP 23382592A JP H0685165 A JPH0685165 A JP H0685165A
Authority
JP
Japan
Prior art keywords
semiconductor device
external
main body
lead
external lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23382592A
Other languages
Japanese (ja)
Inventor
Akitoshi Hara
明稔 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP23382592A priority Critical patent/JPH0685165A/en
Publication of JPH0685165A publication Critical patent/JPH0685165A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To manufacture a semiconductor device of high heat dissipation without increasing the mounting area, by connecting the outer lead or the outer connection part of an upper semiconductor device with the outer lead or the outer connection part of a lower semiconductor device, and applying an individual part member of high thermal conductivity like metal and ceramic to a positioning part. CONSTITUTION:The outer lead 6 of an upper semiconductor device is so formed that a terminal thereof which is to be electrically connected with a lower electrode comes into contact with the tip side position viewed from the inner lead of the outer lead 19 for connection use of a lower semiconductor device. A recessed part is formed on the lower surface of a main body 5 of the upper semiconductor device, and a recessed part is formed on the upper surface of a main body 15 of the lower semiconductor device which surface corresponds with the lower surface of the main body 5. A part member 20 of high thermal conductivity like metal and ceramic is arranged as an individual part number for positioning which is comformable to the recessed parts of the upper semiconductor device and the lower semiconductor device. The outer lead 6 of the upper semiconductor device and the outer lead 19 for connection use of the lower semiconductor device are fixed by soldering or caulking or with conductive adhesive agent.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、複数の半導体素子を搭
載した半導体装置の構造およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device having a plurality of semiconductor elements mounted thereon and a manufacturing method thereof.

【０００２】[0002]

【従来の技術】従来の半導体装置の代表例を単数の半導
体素子を搭載した時の構造は図３に、複数の半導体素子
を搭載した時の構造は図４に示す。2. Description of the Related Art A typical example of a conventional semiconductor device is shown in FIG. 3 when a single semiconductor element is mounted, and in FIG. 4 when a plurality of semiconductor elements are mounted.

【０００３】まず、単数の半導体素子を搭載した時の構
造は図３に示すように半導体素子載置部１に熱硬化性樹
脂や共晶合金，溶融金属等によって半導体素子２を載置
・固定し、その半導体素子２の電極と内部リード部３は
金で構成されたワイヤー４によって接続されている。さ
らに、内部リード部３の延長上で封止部５より外部の外
部リード部６の表面を半田により鍍金し、セラミックや
樹脂の積層基板・プリント基板に接続するパターン等に
半田付けしやすいようなリード形状としている。次に封
止部５の表面にインクやレーザーでの刻印などを行いそ
の半導体装置の製品名や特徴を表示する。First, as shown in FIG. 3, the structure when a single semiconductor element is mounted is such that the semiconductor element 2 is mounted / fixed on the semiconductor element mounting portion 1 with a thermosetting resin, a eutectic alloy, a molten metal or the like. Then, the electrode of the semiconductor element 2 and the internal lead portion 3 are connected by a wire 4 made of gold. Further, the surface of the external lead portion 6 outside the sealing portion 5 is plated with solder as the extension of the internal lead portion 3 so that it can be easily soldered to a pattern or the like to be connected to a ceramic or resin laminated substrate or a printed circuit board. It has a lead shape. Next, marking on the surface of the sealing portion 5 with ink or laser is performed to display the product name and characteristics of the semiconductor device.

【０００４】次に、複数の半導体素子を搭載した時の構
造は図４に示すように半導体素子載置部１に内部配線７
をし、半導体素子２及び１２を載置・固定し、前記単数
の半導体素子を搭載の場合と同様な構造をしている。こ
のような半導体装置の構造がよく知られていた。Next, as shown in FIG. 4, the structure when a plurality of semiconductor elements are mounted is shown in FIG.
Then, the semiconductor elements 2 and 12 are placed and fixed, and the structure is the same as the case where the single semiconductor element is mounted. The structure of such a semiconductor device has been well known.

【０００５】[0005]

【発明が解決しようとする課題】しかし、従来の半導体
装置の構造では半導体装置に対する高機能化への要求が
高まり、半導体素子の高集積化・高性能化が進み半導体
素子の大型化が進み、さらに半導体素子の入出力端子数
の数が飛躍的に多くなっている中、従来の半導体装置の
構造では次のような問題が起きる。However, in the structure of the conventional semiconductor device, there is an increasing demand for higher functionality of the semiconductor device, the higher integration and higher performance of the semiconductor element, and the larger semiconductor element. Further, while the number of input / output terminals of the semiconductor element has increased dramatically, the following problems occur in the structure of the conventional semiconductor device.

【０００６】複数の半導体素子を搭載した時の構造図４
において、半導体素子の高機能化・高性能化が進み半導
体素子２を大型化することにより、それらを保護する封
止部５も半導体素子の大型化につれてますます大型化す
る。また、半導体装置の高機能化への要求により搭載半
導体の数もますます多数になり、その事により封止部５
も前記と同様にますます大型化する。Structure diagram when mounting a plurality of semiconductor elements 4
In the above, as the function and performance of the semiconductor element increase, and the semiconductor element 2 increases in size, the encapsulating portion 5 for protecting them also increases in size as the semiconductor element increases in size. In addition, the number of mounted semiconductors is increasing more and more due to the demand for higher functionality of semiconductor devices.
Will also become larger and larger as mentioned above.

【０００７】前記のように大型化した場合、その分半導
体装置の反りやねじれ等が大きくなり、また半導体装置
が取り付けられるセラミックや樹脂の積層基板・プリン
ト基板の変形も大きくなれば変位量も多くなり、基板に
半導体装置を取り付ける時の事故が発生する。When the size is increased as described above, the warp or twist of the semiconductor device is correspondingly increased, and the larger the deformation of the ceramic or resin laminated substrate / printed circuit board to which the semiconductor device is attached, the greater the amount of displacement. Therefore, an accident occurs when the semiconductor device is attached to the board.

【０００８】また、封止部５の大型化を防ごうとすれ
ば、半導体素子の細密化において飛躍的な高い技術が必
要とされる。Further, in order to prevent the encapsulation portion 5 from increasing in size, a drastically high technique is required in the miniaturization of semiconductor elements.

【０００９】さらに、製造工程の中ではそれぞれの半導
体素子はウエハー状態で電気特性が測られ、良品のみ半
導体装置に搭載されるが、その半導体装置の組立工程の
中で不良が発生する場合がある。その時、たとえば１個
の半導体素子当たりの良品歩留りが９０パーセントとす
ると、３個の半導体素子を搭載した半導体装置では、９
０パーセント×９０パーセント×９０パーセント＝７
２．９パーセントの良品歩留りとなり、非常に不経済の
結果となる。Further, in the manufacturing process, the electrical characteristics of each semiconductor element are measured in a wafer state, and only good products are mounted on the semiconductor device. However, defects may occur during the assembly process of the semiconductor device. . At that time, assuming that the yield of non-defective products per semiconductor element is 90%, for example, a semiconductor device having three semiconductor elements has a yield of 9%.
0% x 90% x 90% = 7
The yield of non-defective products is 2.9%, which is very uneconomical.

【００１０】そこで、本発明の目的は複数の半導体素子
を搭載した半導体装置の平面的な大きさを半導体装置が
高機能化しても変えないで商品化し、それが基板取付時
での取付不良を低減することにある。Therefore, an object of the present invention is to commercialize a semiconductor device having a plurality of semiconductor elements mounted thereon without changing the planar size of the semiconductor device even if the semiconductor device is highly functionalized. To reduce.

【００１１】[0011]

【課題を解決するための手段】上記目的は、半導体装置
において、外部リードまたは外部接続部を有する上部半
導体装置と外部リードまたは外部接続部を有する下部半
導体装置が外部リードまたは外部接続部で接続している
ことで達成される。SUMMARY OF THE INVENTION In a semiconductor device, the above object is to connect an upper semiconductor device having an external lead or an external connecting portion and a lower semiconductor device having an external lead or an external connecting portion with the external lead or the external connecting portion. It is achieved by

【００１２】[0012]

【実施例】以下、本発明の実施例を図１・図２により説
明する。Embodiments of the present invention will be described below with reference to FIGS.

【００１３】図１において、上部半導体装置の半導体素
子載置部１に熱硬化性樹脂によって上部半導体装置の半
導体素子２を載置・固定し、その半導体素子２の電極と
上部半導体装置の内部リード部３は金で構成されたワイ
ヤー４によって接続されている。さらに、上部半導体装
置の内部リード部３の延長上で上部半導体装置の封止樹
脂部５より外部の上部半導体装置の外部リード部６の表
面は半田により鍍金されている。また、下部半導体装置
の半導体素子載置部１１に熱硬化性樹脂によって下部半
導体装置の半導体素子１２を載置・固定し、その半導体
素子１２の電極と下部半導体装置の内部リード部１３は
金で構成されたワイヤー１４によって接続されている。
さらに、下部半導体装置の内部リード部１３の延長上で
下部半導体装置の封止樹脂部１５より外部の下部半導体
装置の外部リード部１６と接続用外部リード部１９の表
面は半田により鍍金されている。In FIG. 1, the semiconductor element 2 of the upper semiconductor device is mounted and fixed on the semiconductor element mounting portion 1 of the upper semiconductor device by a thermosetting resin, and the electrode of the semiconductor element 2 and the internal lead of the upper semiconductor device. The parts 3 are connected by a wire 4 made of gold. Further, on the extension of the internal lead portion 3 of the upper semiconductor device, the surface of the external lead portion 6 of the upper semiconductor device outside the sealing resin portion 5 of the upper semiconductor device is plated with solder. Further, the semiconductor element 12 of the lower semiconductor device is mounted and fixed on the semiconductor element mounting portion 11 of the lower semiconductor device with a thermosetting resin, and the electrode of the semiconductor element 12 and the inner lead portion 13 of the lower semiconductor device are made of gold. It is connected by the constructed wire 14.
Further, on the extension of the inner lead portion 13 of the lower semiconductor device, the surfaces of the outer lead portion 16 of the lower semiconductor device and the connecting outer lead portion 19 outside the encapsulating resin portion 15 of the lower semiconductor device are plated with solder. .

【００１４】上部半導体装置と下部半導体装置はそれぞ
れ別々に製造され、それぞれ完成後に電気特性を測定し
良品のみを接合する。その接合方法は、上部半導体装置
の本体下面に凹部８を設け、それに対応して下部半導体
装置の本体上面に凸部１８を設ける。この上部半導体装
置下面の凹部８と下部半導体装置上面の凸部１８は、下
部半導体装置に対し上部半導体装置の位置決めの為に用
いる。その位置決めは、上部半導体装置の下部半導体装
置へ電気的に接続が必要とされる端子を下部半導体装置
の接続用外部リード部１９の内部リードからみて、先端
側の位置に接触するように上部半導体装置の外部リード
６を成形する。このようにして、上部半導体装置が下部
半導体装置に載置されるとき下部半導体装置の上面に樹
脂接着剤にて仮どめしておくと作業性がよい。最後に、
上部半導体装置の外部リード６と下部半導体装置の接続
用外部リード１９を半田付け及び固定し、最終電気特性
を測る。したがって、本発明の半導体装置を基板に実装
する時は下部半導体装置の外部リード１６を用いる。The upper semiconductor device and the lower semiconductor device are manufactured separately, and after completion of each, the electrical characteristics are measured and only good products are bonded. In the joining method, the concave portion 8 is provided on the lower surface of the main body of the upper semiconductor device, and the convex portion 18 is correspondingly provided on the upper surface of the main body of the lower semiconductor device. The concave portion 8 on the lower surface of the upper semiconductor device and the convex portion 18 on the upper surface of the lower semiconductor device are used for positioning the upper semiconductor device with respect to the lower semiconductor device. The positioning is performed such that the terminal of the upper semiconductor device, which is required to be electrically connected to the lower semiconductor device, is in contact with the position on the tip side when viewed from the internal lead of the external connecting lead portion 19 of the lower semiconductor device. The outer leads 6 of the device are molded. In this way, when the upper semiconductor device is mounted on the lower semiconductor device, it is preferable to temporarily fix it to the upper surface of the lower semiconductor device with a resin adhesive. Finally,
The outer leads 6 of the upper semiconductor device and the connecting outer leads 19 of the lower semiconductor device are soldered and fixed, and the final electrical characteristics are measured. Therefore, when the semiconductor device of the present invention is mounted on the substrate, the external leads 16 of the lower semiconductor device are used.

【００１５】この位置決めは、上部半導体装置の本体下
面に凹部、それに対応した下部半導体装置の本体上面に
凸部を設けるのみでなく、その反対に上部半導体装置の
本体下面に凸部、それに対応した下部半導体装置の本体
上面に凹部を設けることでも同様の効果がある。In this positioning, not only the concave portion is provided on the lower surface of the main body of the upper semiconductor device, and the corresponding convex portion is provided on the upper surface of the lower semiconductor device, but the convex portion is provided on the lower surface of the main body of the upper semiconductor device. The same effect can be obtained by providing a recess on the upper surface of the lower semiconductor device body.

【００１６】また、この位置決めに放熱効果を付加した
発明が図２であり以下に説明する。図２において、図１
と同様に上部半導体装置の半導体素子載置部１に熱硬化
性樹脂によって上部半導体装置の半導体素子２を載置・
固定し、その半導体素子２の電極と上部半導体装置の内
部リード部３は金で構成されたワイヤー４によって接続
され、上部半導体装置の内部リード部３の延長上で上部
半導体装置の封止樹脂部５より外部の上部半導体装置の
外部リード部６の表面は半田により鍍金されている。ま
た、下部半導体装置の半導体素子載置部１１に熱硬化性
樹脂によって下部半導体装置の半導体素子１２を載置・
固定し、その半導体素子１２の電極と下部半導体装置の
内部リード部１３は金で構成されたワイヤー１４によっ
て接続されている。さらに、下部半導体装置の内部リー
ド部１３の延長上で下部半導体装置の封止樹脂部１５よ
り外部の下部半導体装置の外部リード部１６の表面は半
田により鍍金されている。さらに、上部半導体装置の本
体下面に凹部、それに対応した下部半導体装置の本体上
面に凹部を設け、その上部半導体装置と下部半導体装置
のそれぞれの凹部に合うような位置合わせ用の別部材と
して金属やセラミックなどの熱伝導性の高い部材２０を
用いる。そして、図１と同様に上部半導体装置の外部リ
ード６と下部半導体装置の接続用外部リード１９を半田
付け・固定し、最終電気特性を測る。An invention in which a heat radiation effect is added to this positioning is shown in FIG. 2 and will be described below. In FIG. 2, FIG.
Similarly, the semiconductor element 2 of the upper semiconductor device is mounted on the semiconductor element mounting portion 1 of the upper semiconductor device by thermosetting resin.
The electrode of the semiconductor element 2 is fixed and the inner lead portion 3 of the upper semiconductor device is connected by a wire 4 made of gold, and the encapsulating resin portion of the upper semiconductor device is extended on the extension of the inner lead portion 3 of the upper semiconductor device. The surface of the outer lead portion 6 of the upper semiconductor device outside 5 is plated with solder. Also, the semiconductor element 12 of the lower semiconductor device is mounted on the semiconductor element mounting portion 11 of the lower semiconductor device by thermosetting resin.
After being fixed, the electrode of the semiconductor element 12 and the internal lead portion 13 of the lower semiconductor device are connected by a wire 14 made of gold. Further, on the extension of the inner lead portion 13 of the lower semiconductor device, the surface of the outer lead portion 16 of the lower semiconductor device outside the sealing resin portion 15 of the lower semiconductor device is plated with solder. Further, a concave portion is provided on the lower surface of the main body of the upper semiconductor device and a concave portion is provided on the upper surface of the lower semiconductor device corresponding to the concave portion. A member 20 having high thermal conductivity such as ceramic is used. Then, as in FIG. 1, the external leads 6 of the upper semiconductor device and the connecting external leads 19 of the lower semiconductor device are soldered and fixed, and the final electrical characteristics are measured.

【００１７】また、上部半導体装置の外部リード６と下
部半導体装置の外部リード１９の接続は外部リードどう
しのかしめや導伝性接着剤・炭素付着などによって行っ
てもよい。Further, the external leads 6 of the upper semiconductor device and the external leads 19 of the lower semiconductor device may be connected by caulking the external leads or by using a conductive adhesive or carbon.

【００１８】以上のごとく上部半導体装置の外部リード
または外部接続部と下部半導体装置の外部リードまたは
外部接続部で接続していることにより、さらに位置決め
用の上部半導体装置の本体下面に凹部凸部、それに対応
した下部半導体装置の本体上面に凸部凹部を設けている
ことにより、または位置決め用に金属やセラミックなど
の熱伝導性の高い別部材を用いることにより、複数の半
導体素子を搭載した半導体装置が実装面積を大きくせず
に製造可能となり、それは半導体装置として放熱性を兼
ね備えることが出来る。By connecting the external lead or external connecting portion of the upper semiconductor device to the external lead or external connecting portion of the lower semiconductor device as described above, a concave convex portion is further formed on the lower surface of the main body of the upper semiconductor device for positioning. A semiconductor device having a plurality of semiconductor elements mounted therein is provided with a convex concave portion on the upper surface of the lower semiconductor device corresponding thereto or by using another member having a high thermal conductivity such as metal or ceramic for positioning. Can be manufactured without increasing the mounting area, and it can have heat dissipation as a semiconductor device.

【００１９】[0019]

【発明の効果】本発明によれば、従来の技術で複数の半
導体素子を搭載した半導体装置を製造することが出来、
それは従来の半導体装置の製造歩留まりとほぼ同等とな
り、その半導体装置の実装面積を拡大せずにすみ、高熱
伝導性の位置決め部材により高放熱半導体装置の製造が
可能となる。本発明の半導体装置を使用することによ
り、電子機器の小型化・高性能化・低価格化ができる効
果がある。According to the present invention, a semiconductor device having a plurality of semiconductor elements mounted therein can be manufactured by the conventional technique,
That is almost the same as the manufacturing yield of the conventional semiconductor device, the mounting area of the semiconductor device is not required to be increased, and the highly heat-dissipating semiconductor device can be manufactured by the positioning member having high thermal conductivity. By using the semiconductor device of the present invention, it is possible to reduce the size, improve the performance, and reduce the price of electronic equipment.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の実施例の上部半導体装置の外部リー
ドと下部半導体装置の外部リードを接続し、本体の一部
に凹部凸部を持った半導体装置図である。FIG. 1 is a diagram of a semiconductor device in which an external lead of an upper semiconductor device and an external lead of a lower semiconductor device of an embodiment of the present invention are connected to each other and a convex portion of a main body has a concave portion.

【図２】 本発明の実施例の上部半導体装置の外部リー
ドと下部半導体装置の外部リードを接続し、位置決めに
別部材を使用した半導体装置図である。FIG. 2 is a semiconductor device diagram in which the external lead of the upper semiconductor device and the external lead of the lower semiconductor device of the embodiment of the present invention are connected and another member is used for positioning.

【図３】 従来の単数の半導体を搭載した半導体装置図
である。FIG. 3 is a diagram of a conventional semiconductor device mounting a single semiconductor.

【図４】 従来の複数の半導体を搭載した半導体装置図
である。FIG. 4 is a diagram of a conventional semiconductor device mounting a plurality of semiconductors.

【符号の説明】[Explanation of symbols]

１，１１ 半導体素子載置部 ２，１２ 半導体素子 ３，１３ 内部リード部 ４，１４ ワイヤー ５，１５ 封止樹脂部 ６，１６ 外部リード部 ７ 内部配線 ８ 上部半導体装置下面の凹部 １８ 下部半導体装置上面の凸部 １９ 接続用外部リード部 ２０ 位置決め部材 1, 11 Semiconductor element mounting portion 2, 12 Semiconductor element 3, 13 Internal lead portion 4, 14 Wire 5, 15 Sealing resin portion 6, 16 External lead portion 7 Internal wiring 8 Recessed portion of lower surface of upper semiconductor device 18 Lower semiconductor device Upper surface convex portion 19 External lead portion for connection 20 Positioning member

Claims (11)

【特許請求の範囲】[Claims] 【請求項１】 複数個の半導体素子を有する半導体装置
において外部リードまたは外部接続部を有する上部半導
体装置と外部リードまたは外部接続部を有する下部半導
体装置が外部リードまたは外部接続部で接続して複合し
てなることを特徴とする半導体装置。1. In a semiconductor device having a plurality of semiconductor elements, an upper semiconductor device having an external lead or an external connecting portion and a lower semiconductor device having an external lead or an external connecting portion are connected by the external lead or the external connecting portion to form a composite. A semiconductor device characterized by the following. 【請求項２】 複数個の半導体素子を有する半導体装置
において外部リードまたは外部接続部を有する上部半導
体装置と外部リードまたは外部接続部を有する下部半導
体装置が外部リードまたは外部接続部で接続して複合し
てなることを特徴とする半導体装置の製造方法。2. In a semiconductor device having a plurality of semiconductor elements, an upper semiconductor device having an external lead or an external connecting portion and a lower semiconductor device having an external lead or an external connecting portion are connected by the external lead or the external connecting portion to form a composite. A method of manufacturing a semiconductor device, comprising: 【請求項３】 請求項１記載の上部半導体装置の外部リ
ードまたは外部接続部と下部半導体装置外部リードまた
は外部接続部の接続は合金や溶融金属による金属結合と
することを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the external lead or the external connecting portion of the upper semiconductor device and the lower semiconductor device external lead or the external connecting portion are connected by metal bonding with an alloy or a molten metal. 【請求項４】 請求項１記載の上部半導体装置の外部リ
ードまたは外部接続部と下部半導体装置外部リードまた
は外部接続部の接続は外部リードまたは外部接続部どう
しのかしめなどによる圧着とすることを特徴とする半導
体装置。4. The external lead or the external connecting portion of the upper semiconductor device according to claim 1 and the lower semiconductor device external lead or the external connecting portion are connected by crimping by crimping the external lead or the external connecting portion. Semiconductor device. 【請求項５】 請求項１記載の上部半導体装置の外部リ
ードまたは外部接続部と下部半導体装置外部リードまた
は外部接続部の接続は導伝性接着剤や炭素付着による非
金属結合とすることを特徴とする半導体装置。5. The connection between the external lead or external connection portion of the upper semiconductor device and the external lead or external connection portion of the lower semiconductor device according to claim 1, is performed by non-metal bonding by conductive adhesive or carbon deposition. Semiconductor device. 【請求項６】 請求項１記載の上部半導体装置の本体下
面に凸部を有し、それに対応して下部半導体装置の本体
上面に凹部を有することを特徴とする半導体装置。6. The semiconductor device according to claim 1, wherein the upper semiconductor device has a convex portion on the lower surface of the main body, and the lower semiconductor device has a concave portion on the upper surface of the main body corresponding to the convex portion. 【請求項７】 請求項１記載の上部半導体装置の本体下
面に凸部を有し、それに対応して下部半導体装置の本体
上面に凹部を有することを特徴とする半導体装置の製造
方法。7. A method of manufacturing a semiconductor device according to claim 1, wherein the upper semiconductor device has a convex portion on the lower surface of the main body, and the lower semiconductor device has a concave portion on the upper surface of the main body corresponding to the convex portion. 【請求項８】 請求項１記載の上部半導体装置の本体下
面に凹部を有し、それに対応して下部半導体装置の本体
上面に凸部を有することを特徴とする半導体装置。8. A semiconductor device according to claim 1, wherein a lower surface of the main body of the upper semiconductor device has a concave portion, and a lower surface of the lower semiconductor device has a convex portion corresponding to the concave portion. 【請求項９】 請求項１記載の上部半導体装置の本体下
面に凹部を有し、それに対応して下部半導体装置の本体
上面に凹部を有すし、その凹部と凹部を合わせる別の部
品を有することを特徴とする半導体装置。9. The upper semiconductor device according to claim 1, wherein the lower surface of the main body of the upper semiconductor device has a recess, the upper surface of the lower semiconductor device has a recess corresponding to the recess, and another component for aligning the recess with the recess. A semiconductor device characterized by: 【請求項１０】 請求項９記載の凹部と凹部を合わせる
別の部品が金属やセラミックなどの熱伝導性の高い部材
とすることを特徴とする半導体装置。10. A semiconductor device, wherein the recess and the other component for fitting the recess are members having high thermal conductivity such as metal and ceramics. 【請求項１１】 請求項９記載の凹部と凹部を合わせる
別の部品が金属やセラミックなどの熱伝導性の高い部材
とすることを特徴とする半導体装置の製造方法。11. A method for manufacturing a semiconductor device, characterized in that the recess and the other component for matching the recess are members having high thermal conductivity such as metal and ceramics.
JP23382592A 1992-09-01 1992-09-01 Semiconductor device and manufacture thereof Pending JPH0685165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23382592A JPH0685165A (en) 1992-09-01 1992-09-01 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23382592A JPH0685165A (en) 1992-09-01 1992-09-01 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0685165A true JPH0685165A (en) 1994-03-25

Family

ID=16961156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23382592A Pending JPH0685165A (en) 1992-09-01 1992-09-01 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0685165A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015132595A (en) * 2014-01-13 2015-07-23 マイクロナス ゲー・エム・ベー・ハー Sensor device
JP2016076727A (en) * 2015-12-24 2016-05-12 トヨタ自動車株式会社 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015132595A (en) * 2014-01-13 2015-07-23 マイクロナス ゲー・エム・ベー・ハー Sensor device
US9632148B2 (en) 2014-01-13 2017-04-25 Micronas Gmbh Sensor device
JP2016076727A (en) * 2015-12-24 2016-05-12 トヨタ自動車株式会社 Semiconductor device

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