JPH04357729A - Phase synchronization circuit - Google Patents
Phase synchronization circuitInfo
- Publication number
- JPH04357729A JPH04357729A JP3131378A JP13137891A JPH04357729A JP H04357729 A JPH04357729 A JP H04357729A JP 3131378 A JP3131378 A JP 3131378A JP 13137891 A JP13137891 A JP 13137891A JP H04357729 A JPH04357729 A JP H04357729A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- phase
- switching
- output
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 230000003247 decreasing effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000004904 shortening Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Superheterodyne Receivers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、周波数シンセサイザ、
位相同期形変調器等に利用される位相同期回路に関する
ものである。[Industrial Application Field] The present invention relates to a frequency synthesizer,
This invention relates to a phase-locked circuit used in phase-locked modulators and the like.
【０００２】0002
【従来の技術】位相同期回路（ＰＬＬ；フェーズ・ロッ
ク・ループ回路）は、周波数シンセサイザをはじめ各種
機器・装置に広く利用されている。特に、電池動作の移
動無線機においてはチャンネル間引き込み特性の高速化
と、低消費電力化が重要な課題となる。2. Description of the Related Art Phase-locked loop circuits (PLLs) are widely used in various devices and devices including frequency synthesizers. In particular, in battery-operated mobile radio equipment, high-speed inter-channel pull-in characteristics and low power consumption are important issues.
【０００３】以下、従来の位相同期回路について説明す
る。図４は従来の位相同期回路の構成を示すものである
。図４において１は電圧制御発振器（ＶＣＯ）、２は高
周波出力端子、３はＶＣＯ１の出力を分周する分周器、
４は位相比較器（通常デジタル形の位相・周波数比較器
（ＰＦＣ））である。５は基準発振器（通常温度補償水
晶発振器（ＴＣＸＯ）が用いられる）で、その出力を分
周器６で分周してＰＦＣ４に入力する。ＰＦＣ４の出力
は分周器３の出力と分周器６の出力の位相差成分であり
、チャージポンプ７を通し、ループフィルタ（低域通過
フィルタ）８により高域成分を除去した後、ＶＣＯ１に
帰還する。位相同期回路出力周波数は、分周器３に設定
される周波数指定信号９により切替られる。[0003] A conventional phase locked circuit will be explained below. FIG. 4 shows the configuration of a conventional phase locked circuit. In FIG. 4, 1 is a voltage controlled oscillator (VCO), 2 is a high frequency output terminal, 3 is a frequency divider that divides the output of VCO 1,
4 is a phase comparator (usually a digital phase/frequency comparator (PFC)). 5 is a reference oscillator (usually a temperature compensated crystal oscillator (TCXO) is used), the output of which is divided by a frequency divider 6 and input to the PFC 4; The output of PFC4 is a phase difference component between the output of frequency divider 3 and the output of frequency divider 6, and after passing through charge pump 7 and removing high-frequency components by loop filter (low-pass filter) 8, it is sent to VCO1. Return. The phase locked circuit output frequency is switched by a frequency designation signal 9 set in the frequency divider 3.
【０００４】以上のように構成された位相同期回路につ
いて、以下その動作について説明する。The operation of the phase synchronized circuit configured as described above will be explained below.
【０００５】無線機の低消費電力化のため不要時に電源
を切ることが考えられ、一般に間欠動作と呼んでいる。
間欠動作では電源切断時に、所望周波数に対応する制御
電圧をループフィルタ８で保持する。この時チャージポ
ンプ７の状態によってはループフィルタ８で保持される
電荷が変動することが考えられる。そのためチャージポ
ンプ７とループフィルタ８との間にループスイッチ１０
を入れ、電源切断時にループスイッチ１０を開放する。
さらに、電源投入時には周波数は同じでも位相が違うた
めＰＦＣ４の出力が発生する事があり、周波数変動が生
じ周波数安定に時間を要する。この対策として、分周器
３と分周器６との出力状態をＰＦＣ４の出力の位相差信
号で判定し、１１、１２のゲート回路により分周器３と
分周器６とを同相状態にしてループを形成する方式をと
る。１３は制御回路でこれらのタイミング制御等を行な
う。[0005] In order to reduce the power consumption of radio equipment, it is considered to turn off the power when it is not needed, and this is generally called intermittent operation. In intermittent operation, the loop filter 8 holds the control voltage corresponding to the desired frequency when the power is turned off. At this time, depending on the state of the charge pump 7, the charge held by the loop filter 8 may vary. Therefore, a loop switch 10 is inserted between the charge pump 7 and the loop filter 8.
is turned on, and the loop switch 10 is opened when the power is turned off. Furthermore, when the power is turned on, even if the frequency is the same, the phase is different, so an output from the PFC 4 may be generated, causing frequency fluctuations and requiring time to stabilize the frequency. As a countermeasure for this, the output states of the frequency divider 3 and the frequency divider 6 are determined by the phase difference signal of the output of the PFC 4, and the frequency divider 3 and the frequency divider 6 are brought into the same phase state by the gate circuits 11 and 12. This method is used to form a loop. A control circuit 13 performs timing control and the like.
【０００６】上記のように、間欠動作時に位相整合動作
を行なうことにより、高速に目的周波数へ引き込むこと
ができる。As described above, by performing the phase matching operation during intermittent operation, it is possible to quickly pull into the target frequency.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、位相同
期回路の引き込み過程には、目標周波数の近傍に引き込
む迄の周波数引き込みモード、それ以降最終周波数に引
き込むまでの位相引き込みモードという２つの状態が存
在し、チャンネル切替時の周波数変化幅が大きい場合位
相同期回路は周波数引き込みモードであるため、図５に
示す例のように、チャンネル切替前後の周波数が大きく
異なる状態で強制的に位相整合を行なってもチャンネル
間引き込み時間の短縮が図れないという課題を有してい
た。[Problem to be Solved by the Invention] However, in the pull-in process of a phase-locked circuit, there are two states: a frequency pull-in mode until it pulls into the vicinity of the target frequency, and a phase pull-in mode after that until it pulls in to the final frequency. If the frequency change width at the time of channel switching is large, the phase synchronized circuit is in frequency pull-in mode, so even if forced phase matching is performed when the frequencies before and after channel switching are significantly different, as in the example shown in Figure 5. The problem was that it was not possible to shorten the time required to pull in between channels.
【０００８】本発明は上記従来技術の課題を解決するも
ので、間欠動作時の高速引き込み特性を維持したまま、
チャンネル間引き込み特性の高速化を同時に実現した位
相同期回路を提供することを目的とする。The present invention solves the above problems of the prior art, and maintains high-speed pull-in characteristics during intermittent operation.
An object of the present invention is to provide a phase synchronized circuit that simultaneously achieves high-speed interchannel pull-in characteristics.
【０００９】[0009]
【課題を解決するための手段】この目的を達成するため
に本発明は、多チャンネル周波数シンセサイザにおいて
、チャンネル切替時の周波数切替幅が大きい場合、目的
とする周波数とは異なりかつ位相同期回路が位相引き込
み動作範囲以内に入るように分周数を順次設定する構成
を有している。[Means for Solving the Problems] In order to achieve this object, the present invention provides a multi-channel frequency synthesizer in which, when the frequency switching width at the time of channel switching is large, the frequency differs from the target frequency and the phase synchronization circuit is out of phase. It has a configuration in which the frequency division number is sequentially set so as to fall within the pull-in operation range.
【００１０】0010
【作用】本発明は上記構成によって、１段毎の周波数変
化幅を小さくし、位相同期回路が位相引き込みモードの
条件を満足する設定を行なうことで、チャンネル間周波
数切替時間の短縮を実現することができる。[Operation] With the above configuration, the present invention reduces the frequency change width for each stage and sets the phase synchronization circuit so that it satisfies the conditions of the phase pull-in mode, thereby shortening the inter-channel frequency switching time. Can be done.
【００１１】[0011]
【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【００１２】図１は本発明の一実施例における位相同期
回路の構成図である。図１において１〜１３の番号を付
している構成要素は図４と同一のものなので説明は略す
。図１において図４の構成と異なるとる点は、分周数制
御器１４を設けた点であり、であり、分周数制御器１４
は分周数を順次設定する分周数多段設定機能を有する。
図２は分周数制御器１４による位相同期回路のチャンネ
ル切替図である。FIG. 1 is a block diagram of a phase locked circuit according to an embodiment of the present invention. Components numbered 1 to 13 in FIG. 1 are the same as those in FIG. 4, so their description will be omitted. 1 differs from the configuration in FIG. 4 in that a frequency division number controller 14 is provided.
has a multi-step frequency division number setting function that sequentially sets the frequency division number. FIG. 2 is a diagram showing channel switching of the phase synchronized circuit by the frequency division number controller 14.
【００１３】図２において、ｆ１は切替前のチャンネル
周波数、ｆ２は周波数切替過程１段目の周波数、ｆｎは
周波数 切替過程ｎ−１段目の周波数、ｆｎ＋１は切
替後チャンネル周波数である。In FIG. 2, f1 is the channel frequency before switching, f2 is the frequency at the first stage of the frequency switching process, fn is the frequency at the n-1st stage of the frequency switching process, and fn+1 is the channel frequency after switching.
【００１４】以上のように構成された周波数シンセサイ
ザの動作を説明するが、基本的な動作は図４の動作と同
じであり、図４と異なる点のみについて説明する。The operation of the frequency synthesizer configured as described above will be explained.The basic operation is the same as that shown in FIG. 4, and only the points that are different from FIG. 4 will be explained.
【００１５】なお、ここで、ｆ０とｆｎ＋１の切替周波
数幅は＋２５ＭＨｚ、目標周波数との周波数差が１ＭＨ
ｚの範囲で位相同期回路は周波数引き込みモードから位
相引き込みモードに切り替わるとすると、ｎを２５以上
に設定することで、各段の引き込み動作は位相引き込み
モードのみとなる。まずｆ１よりｆ２へ周波数切替を行
なうが、この切替は位相引き込みモードであるため、位
相整合動作を行なうことで高速に周波数引き込みを完了
する。同様にして、ｆ２からｆ３、・・・、ｆｎからｆ
ｎ＋１への周波数切替すべて位相引き込みモードである
ため、高速周波数切替を達成する。この操作は分周数制
御器１４により順次切替られるものであり、直接ｆ１か
らｆｎ＋１へ周波数を切替える場合と比較して高速に周
波数切替を行なうことが可能となる。位相整合を行なっ
たときの周波数切替幅と引き込み時間の特性はＶＣＯ感
度、リファレンス周波数等回路条件によって異なり、多
段とした時の最適分割周波数幅はシステムに用いられる
位相同期回路により決定される固有のものである。[0015] Here, the switching frequency width of f0 and fn+1 is +25 MHz, and the frequency difference from the target frequency is 1 MHz.
Assuming that the phase locked circuit switches from the frequency pull-in mode to the phase pull-in mode in the range of z, by setting n to 25 or more, the pull-in operation of each stage becomes only the phase pull-in mode. First, the frequency is switched from f1 to f2, but since this switching is in the phase pull-in mode, the frequency pull-in is completed quickly by performing a phase matching operation. Similarly, f2 to f3,..., fn to f
Frequency switching to n+1 is all in phase pull mode, thus achieving fast frequency switching. This operation is sequentially switched by the frequency division number controller 14, and it is possible to switch the frequency faster than when directly switching the frequency from f1 to fn+1. The characteristics of the frequency switching width and pull-in time when performing phase matching vary depending on circuit conditions such as VCO sensitivity and reference frequency. It is something.
【００１６】チャンネル切替周波数幅が大きい場合の本
実施例による位相同期回路周波数切替時間特性と従来の
位相同期回路の周波数切替時間特性を図３に比較して示
す。FIG. 3 shows a comparison between the frequency switching time characteristics of the phase-locked circuit according to this embodiment and the frequency switching time characteristics of the conventional phase-locked circuit when the channel switching frequency width is large.
【００１７】この図３から明らかなように、チャンネル
切替周波数幅が大きい場合の本実施例による位相同期回
路周波数切替時間は、各段の引き込み過程が位相引き込
みモードのみとなる最適分割周波数幅を設定し、多段に
周波数切替を行なうことで、チャンネル周波数切替時間
の短縮という点で優れた効果が得られる。As is clear from FIG. 3, when the channel switching frequency width is large, the frequency switching time of the phase-locked circuit according to this embodiment is set to an optimal divided frequency width such that the pull-in process of each stage is only in the phase pull-in mode. However, by performing frequency switching in multiple stages, an excellent effect can be obtained in terms of shortening the channel frequency switching time.
【００１８】以上のように本実施例によれば、多チャン
ネル周波数シンセサイザにおいて、チャンネル切替時の
周波数切替幅が大きい場合、目的とする周波数とは異な
りかつ位相同期回路が位相引き込み動作範囲以内に入る
ように分周数を順次設定することにより、チャンネル切
替周波数幅が大きい場合の周波数切替の高速化を実現す
ることができる。As described above, according to this embodiment, in a multi-channel frequency synthesizer, when the frequency switching width at the time of channel switching is large, the frequency differs from the target frequency and the phase locking circuit falls within the phase locking operation range. By sequentially setting the frequency division numbers in this way, it is possible to realize faster frequency switching when the channel switching frequency width is large.
【００１９】なお本実施例においては、切替後の周波数
が切替前に対して高い場合についてのみ記述しているが
、切替後の周波数が切替前に対して低い場合も同様の技
術が適用できることは説明するまでもない。Although this embodiment describes only the case where the frequency after switching is higher than before switching, the same technique can also be applied when the frequency after switching is lower than before switching. There's no need to explain.
【００２０】[0020]
【発明の効果】以上のように本発明は、多チャンネル周
波数シンセサイザにおいて、チャンネル切替時の周波数
切替幅が大きい場合、目的とする周波数とは異なりかつ
位相同期回路が位相引き込み動作範囲以内に入るように
分周数を順次設定することにより、間欠動作時の高速引
き込み特性を維持したまま、チャンネル切替周波数幅が
大きい場合の周波数切替の高速化を可能とする優れた位
相同期回路を実現できるものである。As described above, the present invention provides a multi-channel frequency synthesizer in which, when the frequency switching width at the time of channel switching is large, the frequency is different from the target frequency and the phase synchronized circuit is within the phase locking operation range. By sequentially setting the frequency division numbers, it is possible to realize an excellent phase-locked circuit that enables high-speed frequency switching when the channel switching frequency width is large while maintaining high-speed pull-in characteristics during intermittent operation. be.
【図１】本発明の一実施例における位相同期回路のブロ
ック結線図FIG. 1 is a block diagram of a phase-locked circuit according to an embodiment of the present invention.
【図２】同実施例における位相同期回路のチャンネル周
波数切替の波形図[Figure 2] Waveform diagram of channel frequency switching of the phase locked circuit in the same embodiment
【図３】同実施例における位相同期回路の切替時間の特
性図[Figure 3] Characteristic diagram of switching time of the phase locked circuit in the same example
【図４】従来の位相同期回路のブロック結線図[Figure 4] Block wiring diagram of a conventional phase-locked circuit
【図５】
同回路の切替周波数幅と引き込み時間の相関図[Figure 5]
Correlation diagram of switching frequency width and pull-in time of the same circuit
１ 電圧制御発振器 ２ 高周波出力端子 ３ 分周器 ４ 位相比較器 ５ 基準発振器 ６ 分周器 ７ チャージポンプ ８ ループフィルタ ９ 周波数指定信号 １０ ループスイッチ １１ ゲート回路 １２ ゲート回路 １３ 制御回路 １４ 分周数制御器 1 Voltage controlled oscillator 2 High frequency output terminal 3 Frequency divider 4 Phase comparator 5 Reference oscillator 6 Frequency divider 7 Charge pump 8 Loop filter 9 Frequency specification signal 10 Loop switch 11 Gate circuit 12 Gate circuit 13 Control circuit 14 Frequency division number controller
Claims (3)
の分周器と、基準発振器の出力を分周する第２の分周器
と、前記第１、第２の分周器の出力位相を検出する位相
比較器と、前記位相比較器の出力を変換し、積分器の駆
動信号とするチャージポンプと、前記チャージポンプの
出力の高域成分を除去して前記電圧制御発振器に帰還す
るループフィルタと、前記電圧制御発振器と第１の分周
器との間に設けた第１のゲート回路と、前記基準発振器
と第２の分周器との間に設けた第２のゲート回路と、前
記第１、第２の分周器出力と周波数シンセサイザ制御信
号とを入力とし、第１、第２のゲート回路を制御する制
御回路と、前記ループフィルタに電荷を保持するスイッ
チとを具備するとともに、チャンネル切替により、目的
とする周波数とは異なりかつ位相引き込み動作範囲以内
に入るように分周数を順次設定する分周数多段設定器と
を設けた位相同期回路。[Claim 1] A first circuit for dividing the output of the voltage controlled oscillator.
a second frequency divider that divides the output of the reference oscillator, a phase comparator that detects the output phases of the first and second frequency dividers, and a second frequency divider that divides the output of the reference oscillator; a charge pump that converts the output into a driving signal for an integrator, a loop filter that removes a high frequency component of the output of the charge pump and feeds it back to the voltage controlled oscillator, the voltage controlled oscillator and a first frequency divider; a first gate circuit provided between the reference oscillator and the second frequency divider, a second gate circuit provided between the reference oscillator and the second frequency divider, and the first and second frequency divider outputs and frequency synthesizer control. The control circuit includes a control circuit that receives a signal as an input and controls the first and second gate circuits, and a switch that holds charge in the loop filter. A phase synchronized circuit equipped with a multi-stage division number setter that sequentially sets the division number so that it falls within the operating range.
して高い場合、位相引き込み動作となる範囲内で分周数
を順次増加させることを特徴とした請求項１記載の位相
同期回路。2. The phase synchronized circuit according to claim 1, wherein when the frequency after switching is higher than the frequency before switching, the frequency division number is sequentially increased within a range in which a phase pull-in operation is performed.
して低い場合、位相引き込み動作となる範囲内で分周数
を順次減少させることを特徴とした請求項１記載の位相
同期回路。3. The phase-locked circuit according to claim 1, wherein when the frequency after switching is lower than the frequency before switching, the frequency division number is sequentially decreased within a range in which a phase pull-in operation is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3131378A JPH04357729A (en) | 1991-06-03 | 1991-06-03 | Phase synchronization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3131378A JPH04357729A (en) | 1991-06-03 | 1991-06-03 | Phase synchronization circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04357729A true JPH04357729A (en) | 1992-12-10 |
Family
ID=15056550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3131378A Pending JPH04357729A (en) | 1991-06-03 | 1991-06-03 | Phase synchronization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04357729A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006339858A (en) * | 2005-05-31 | 2006-12-14 | Toshiba Corp | Data sampling circuit and semiconductor integrated circuit |
-
1991
- 1991-06-03 JP JP3131378A patent/JPH04357729A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006339858A (en) * | 2005-05-31 | 2006-12-14 | Toshiba Corp | Data sampling circuit and semiconductor integrated circuit |
| JP4607666B2 (en) * | 2005-05-31 | 2011-01-05 | 株式会社東芝 | Data sampling circuit and semiconductor integrated circuit |
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