JPH04356821A - Phase locked loop circuit - Google Patents
Phase locked loop circuitInfo
- Publication number
- JPH04356821A JPH04356821A JP3130898A JP13089891A JPH04356821A JP H04356821 A JPH04356821 A JP H04356821A JP 3130898 A JP3130898 A JP 3130898A JP 13089891 A JP13089891 A JP 13089891A JP H04356821 A JPH04356821 A JP H04356821A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- switching
- division number
- phase
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、周波数シンセサイザ、
位相同期形変調器等に利用される位相同期回路に関する
ものである。[Industrial Application Field] The present invention relates to a frequency synthesizer,
This invention relates to a phase-locked circuit used in phase-locked modulators and the like.
【０００２】0002
【従来の技術】位相同期回路（ＰＬＬ：フェーズ・ロッ
ク・ループ）は、周波数シンセサイザをはじめ各種機器
・装置に広く利用されている。高周波回路においては、
電圧制御発振器、分周器、基準発振器、位相比較器、ル
ープフィルタ（低域通過フィルタ）で構成される。2. Description of the Related Art Phase-locked loops (PLLs) are widely used in various devices and devices including frequency synthesizers. In high frequency circuits,
Consists of a voltage controlled oscillator, frequency divider, reference oscillator, phase comparator, and loop filter (low pass filter).
【０００３】以下、従来の位相同期回路について説明す
る。図６は従来の位相同期回路の構成を示すものである
。図６において、１は電圧制御発振器（ＶＣＯ）、２は
高周波出力端子、３はＶＣＯ１の出力を分周する分周器
、４は位相比較器（通常は、デジタル形の位相・周波数
比較器（ＰＦＣ））である。５は基準発振器（通常、温
度補償水晶発振器（ＴＣＸＯ）が用いられる）で、その
出力を分周器６で分周してＰＦＣ４に入力する。ＰＦＣ
４は分周器３の出力、分周器６の出力の２つの出力位相
を検出して、その出力をループフィルタ７を通して広域
成分を除去してＶＣＯ１に帰還する。位相同期回路出力
周波数は、分周数指定器８より分周器３に設定される信
号により切替られる。[0003] A conventional phase locked circuit will be explained below. FIG. 6 shows the configuration of a conventional phase locked circuit. In FIG. 6, 1 is a voltage controlled oscillator (VCO), 2 is a high frequency output terminal, 3 is a frequency divider that divides the output of VCO 1, and 4 is a phase comparator (usually a digital phase/frequency comparator ( PFC)). 5 is a reference oscillator (usually a temperature compensated crystal oscillator (TCXO) is used), the output of which is divided by a frequency divider 6 and input to the PFC 4; PFC
4 detects the two output phases of the output of the frequency divider 3 and the output of the frequency divider 6, passes the output through a loop filter 7, removes wide-range components, and feeds it back to the VCO 1. The phase locked circuit output frequency is switched by a signal set to the frequency divider 3 by the frequency division number designator 8.
【０００４】0004
【発明が解決しようとする課題】しかしながら従来のＰ
ＦＣを用いた位相同期回路では、近傍の周波数切替を行
なった場合に引き込み時間が大幅に長くなるという課題
を有していた。この原因は、図７に示すようにＰＦＣに
おいては２つの入力位相がロック状態（ＰＬＬが安定と
なっている状態）において一致している場合、出力が高
インピーダンス状態となっているが、この領域では不感
帯、すなわち２つの入力位相がわずかにくずれても出力
が変化せず高インピーダンス状態を継続する領域が存在
することにあり、チャンネル数が多く、分周比が大きい
場合に顕著となる。[Problem to be solved by the invention] However, the conventional P
A phase-locked circuit using FC has a problem in that the pull-in time becomes significantly longer when nearby frequencies are switched. The reason for this is that, as shown in Figure 7, in PFC, when the two input phases match in the locked state (PLL is stable), the output is in a high impedance state. In this case, there is a dead zone, that is, a region where the output does not change even if the two input phases are slightly shifted and the high impedance state continues, and this becomes noticeable when the number of channels is large and the frequency division ratio is large.
【０００５】本発明は上記従来技術の課題を解決するも
ので、近傍周波数のチャンネル切替時間の高速化を実現
することを目的とする。[0005] The present invention solves the above-mentioned problems of the prior art, and aims to realize faster channel switching times for nearby frequencies.
【０００６】[0006]
【課題を解決するための手段】この目的を達成するため
に本発明は、多チャンネル周波数シンセサイザにおいて
、周波数切替幅が小さい場合、切替時に目的とする周波
数切替幅以上の分周数を設定した後、最終目標の分周数
を設定する構成を有している。[Means for Solving the Problems] In order to achieve this object, the present invention provides a multi-channel frequency synthesizer in which, when the frequency switching width is small, after setting a frequency division number greater than or equal to the desired frequency switching width at the time of switching, , has a configuration for setting the final target frequency division number.
【０００７】[0007]
【作用】本発明は上記構成によって、ＰＦＣの不感帯の
影響を受けない最適チャンネル切替幅を選択し、周波数
切替を行なうことで、周波数切替時間の短縮を実現する
ことができる。[Function] With the above configuration, the present invention can shorten the frequency switching time by selecting the optimum channel switching width that is not affected by the dead zone of the PFC and performing frequency switching.
【０００８】[0008]
【実施例】以下、本発明の第１の実施例について、図面
を参照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.
【０００９】図１は本発明の一実施例における位相同期
回路の構成図である。図１において、１〜８の番号を付
している構成要素の機能は図６と同一のものなので説明
は略す。図１において図６と異なる点は、分周数制御器
９を設けた点であり、切替時に目的とする周波数切替幅
以上の分周数を設定した後、最終目標の分周数を設定す
る機能を有する。図２に、１０００分周のチャンネルか
ら１００１分周のチャンネルへ周波数を切替る場合の分
周数制御器９の分周数設定動作例を従来例とともに示す
。また、上記操作による位相同期回路近傍周波数切替図
を図３に示す。図３において、ｆ０は切替前のチャンネ
ル周波数、ｆ１は切替後チャンネル周波数、ｆ２は高速
切替用チャンネル周波数である。FIG. 1 is a block diagram of a phase locked circuit according to an embodiment of the present invention. In FIG. 1, the functions of the components numbered 1 to 8 are the same as those in FIG. 6, and therefore the description thereof will be omitted. The difference between FIG. 1 and FIG. 6 is that a frequency division number controller 9 is provided, and after setting a frequency division number greater than or equal to the desired frequency switching width at the time of switching, the final target frequency division number is set. Has a function. FIG. 2 shows an example of the frequency division number setting operation of the frequency division number controller 9 when switching the frequency from a frequency divided channel of 1000 to a frequency divided channel of 1001, together with a conventional example. FIG. 3 shows a diagram of frequency switching near the phase-locked circuit according to the above operation. In FIG. 3, f0 is the channel frequency before switching, f1 is the channel frequency after switching, and f2 is the channel frequency for high-speed switching.
【００１０】以上のように構成された位相同期回路につ
いて、図４に示す切替チャンネル数（切替周波数幅）と
引き込み時間の実施例を用いてその動作を説明する。こ
こで、ｆ０とｆ１の切替周波数幅は＋１チャンネルとす
る。The operation of the phase-locked circuit configured as described above will be explained using an example of the number of switching channels (switching frequency width) and pull-in time shown in FIG. Here, the switching frequency width of f0 and f1 is +1 channel.
【００１１】まず、ｆ０より最短切替時間となるｆ２（
ｆ０＋１０チャンネル）へ一旦周波数切替を行なう。
その後、最終目標周波数であるｆ１（ｆ２−９チャンネ
ル）へ周波数切替を行なう。この操作により、直接ｆ０
からｆ１へ周波数を切替る場合と比較して高速に周波数
切替を行なうことが可能となる。切替周波数幅と引き込
み時間の特性はチャンネル周波数間隔、ＶＣＯ感度、リ
ファレンス周波数等回路条件によって異なり、最適切替
幅はシステムに用いられる位相同期回路固有のものであ
る。First, f2(
f0+10 channel). Thereafter, the frequency is switched to f1 (f2-9 channel), which is the final target frequency. With this operation, directly f0
Compared to the case where the frequency is switched from f1 to f1, it is possible to switch the frequency faster. The characteristics of the switching frequency width and pull-in time vary depending on circuit conditions such as channel frequency spacing, VCO sensitivity, reference frequency, etc., and the optimum switching width is unique to the phase locked circuit used in the system.
【００１２】本実施例による位相同期回路の近傍周波数
切替時間特性と従来の位相同期回路の近傍周波数切替時
間特性を図５に比較して示す。FIG. 5 shows a comparison of the near frequency switching time characteristics of the phase locked circuit according to this embodiment and the near frequency switching time characteristics of the conventional phase locked circuit.
【００１３】この図５から明らかなように、本実施例に
よる位相同期回路の近傍周波数切替時間は、ＰＦＣの不
感帯の影響を受けない最適チャンネル切替幅を選択し周
波数切替を行なうことで、周波数切替時間の短縮という
点で優れた効果が得られる。As is clear from FIG. 5, the neighboring frequency switching time of the phase-locked circuit according to the present embodiment is determined by selecting the optimum channel switching width that is not affected by the dead zone of the PFC and performing frequency switching. An excellent effect can be obtained in terms of time reduction.
【００１４】以上のように本実施例によれば、多チャン
ネル周波数シンセサイザにおいて、周波数切替幅が小さ
い場合、切替時に目的とする周波数切替幅以上の分周数
を設定した後、最終目標の分周数を設定することにより
、近傍周波数切替の高速化を実現することができる。As described above, according to this embodiment, when the frequency switching width is small in a multi-channel frequency synthesizer, after setting a frequency division number that is greater than or equal to the desired frequency switching width at the time of switching, the final target frequency division is performed. By setting the number, it is possible to realize faster switching of neighboring frequencies.
【００１５】なお本実施例においては、切替後の周波数
が切替前に対して高い場合についてのみ記述しているが
、切替後の周波数が切替前に対して低い場合も同様の技
術が適用できることは説明するまでもない。Although this embodiment describes only the case where the frequency after switching is higher than before switching, the same technique can be applied even when the frequency after switching is lower than before switching. There's no need to explain.
【００１６】[0016]
【発明の効果】以上のように本発明は多チャンネル周波
数シンセサイザにおいて、周波数切替幅が小さい場合、
切替時に目的とする周波数切替幅以上の分周数を設定し
た後、最終目標の分周数を設定することにより、ＰＦＣ
の不感帯の影響を受けない高速周波数切替を可能とする
優れた位相同期回路を実現できるものである。[Effects of the Invention] As described above, the present invention provides a multi-channel frequency synthesizer in which when the frequency switching width is small,
After setting a frequency division number greater than or equal to the desired frequency switching width during switching, by setting the final target frequency division number, PFC
This makes it possible to realize an excellent phase-locked circuit that enables high-speed frequency switching without being affected by dead zones.
【図１】本発明の一実施例における位相同期回路のブロ
ック結線図FIG. 1 is a block diagram of a phase-locked circuit according to an embodiment of the present invention.
【図２】同位相同期回路の要部における分周数制御器の
分周数設定動作例を示す図[Figure 2] A diagram showing an example of the frequency division number setting operation of the frequency division number controller in the main part of the in-phase synchronized circuit.
【図３】同位相同期回路における近傍周波数切替の波形
図[Figure 3] Waveform diagram of neighboring frequency switching in in-phase synchronized circuit
【図４】同位相同期回路における切替チャンネル数と引
き込み時間の相関図[Figure 4] Correlation diagram between the number of switching channels and pull-in time in an in-phase synchronized circuit
【図５】同位相同期回路における近傍周波数切替時間の
特性図[Figure 5] Characteristic diagram of neighboring frequency switching time in in-phase synchronized circuit
【図６】従来の位相同期回路のブロック結線図[Figure 6] Block wiring diagram of a conventional phase-locked circuit
【図７】
従来の位相比較器の特性図[Figure 7]
Characteristic diagram of conventional phase comparator
１ 電圧制御発振器 ２ 高周波出力端子 ３ 分周器 ４ 位相比較器 ５ 基準発振器 ６ 分周器 ７ ループフィルタ ８ 分周数指定器 ９ 分周数制御器 1 Voltage controlled oscillator 2 High frequency output terminal 3 Frequency divider 4 Phase comparator 5 Reference oscillator 6 Frequency divider 7 Loop filter 8 Dividing number designator 9 Frequency division number controller
Claims (4)
の分周器と、基準発振器の出力を分周する第２の分周器
と、前記第１、第２の分周器の出力位相を検出する位相
比較器と、前記位相比較器の出力の高域成分を除去して
前記電圧制御発振器に帰還するループフィルタとを具備
するとともに、切替時に目的とする周波数切替幅以上の
分周数を設定した後、最終目標の分周数を設定する分周
数設定手段を設けた位相同期回路。[Claim 1] A first circuit for dividing the output of the voltage controlled oscillator.
a second frequency divider that divides the output of the reference oscillator, a phase comparator that detects the output phases of the first and second frequency dividers, and a second frequency divider that divides the output of the reference oscillator; and a loop filter that removes high-frequency components and feeds back to the voltage controlled oscillator, and after setting a frequency division number greater than or equal to the desired frequency switching width at the time of switching, a frequency division number that is set to the final target frequency switching width is set. A phase synchronized circuit equipped with frequency setting means.
して高い場合、切替時に切替後の周波数より高く分周数
を設定した後、最終目標の分周数を設定することを特徴
とした請求項１記載の位相同期回路。[Claim 2] If the frequency after switching is higher than the frequency before switching, the frequency division number is set higher than the frequency after switching at the time of switching, and then the final target frequency division number is set. The phase locked circuit according to claim 1.
して低い場合、切替時に切替後の周波数より低く分周数
を設定した後、最終目標の分周数を設定することを特徴
とした請求項１記載の位相同期回路。[Claim 3] If the frequency after switching is lower than the frequency before switching, the frequency division number is set lower than the frequency after switching at the time of switching, and then the final target frequency division number is set. The phase locked circuit according to claim 1.
数を多段に設定した後、最終目標の分周数を設定するこ
とを特徴とした請求項１記載の位相同期回路。4. The phase locked circuit according to claim 1, wherein the final target frequency division number is set after setting frequency division numbers other than the target frequency in multiple stages at the time of switching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3130898A JPH04356821A (en) | 1991-06-03 | 1991-06-03 | Phase locked loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3130898A JPH04356821A (en) | 1991-06-03 | 1991-06-03 | Phase locked loop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04356821A true JPH04356821A (en) | 1992-12-10 |
Family
ID=15045300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3130898A Pending JPH04356821A (en) | 1991-06-03 | 1991-06-03 | Phase locked loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04356821A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012109780A (en) * | 2010-11-17 | 2012-06-07 | Asahi Kasei Electronics Co Ltd | Pll circuit |
-
1991
- 1991-06-03 JP JP3130898A patent/JPH04356821A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012109780A (en) * | 2010-11-17 | 2012-06-07 | Asahi Kasei Electronics Co Ltd | Pll circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0500516A2 (en) | Broad band frequency synthesizer for quick frequency retuning | |
| JPH04356821A (en) | Phase locked loop circuit | |
| JPH08149000A (en) | Pll circuit | |
| JPH0786930A (en) | Phase locked loop circuit | |
| JP2738103B2 (en) | PLL synthesizer | |
| JP2000148281A (en) | Clock selecting circuit | |
| JPH04357729A (en) | Phase synchronization circuit | |
| JP2790564B2 (en) | Frequency synthesizer | |
| JP2892886B2 (en) | Frequency synthesizer | |
| JPH06291644A (en) | Pll circuit | |
| JPH09307432A (en) | Pll circuit | |
| JP2601096B2 (en) | Frequency synthesizer | |
| JPS5846586Y2 (en) | Circuit with phase locked loop | |
| JPH07154252A (en) | Phase locked loop circuit | |
| JPH02246423A (en) | Phase locked loop frequency synthesizer | |
| JPH0638116A (en) | Phase locked loop circuit | |
| JPH08307255A (en) | Phase synchronization oscillator | |
| JPH03198424A (en) | Frequency synthesizer | |
| JPH06244719A (en) | Frequency synthesizer | |
| JPH04271520A (en) | Multi-pll synthesizer | |
| JPH03101311A (en) | Phase locked loop oscillation circuit | |
| JPH042217A (en) | Pll frequency synthesizer | |
| JPH02131019A (en) | Phase locked loop circuit | |
| JPH0354917A (en) | Phase locked loop type frequency synthesizer | |
| JPH04284025A (en) | Clock reproducing circuit |