JPH04355994A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH04355994A JPH04355994A JP18256391A JP18256391A JPH04355994A JP H04355994 A JPH04355994 A JP H04355994A JP 18256391 A JP18256391 A JP 18256391A JP 18256391 A JP18256391 A JP 18256391A JP H04355994 A JPH04355994 A JP H04355994A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- layer
- circuit pattern
- surface mounting
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 229910000679 solder Inorganic materials 0.000 claims abstract description 64
- 238000007747 plating Methods 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000004020 conductor Substances 0.000 claims description 9
- 230000000873 masking effect Effects 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 17
- 229910052802 copper Inorganic materials 0.000 abstract description 13
- 239000010949 copper Substances 0.000 abstract description 13
- 239000011889 copper foil Substances 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 238000009713 electroplating Methods 0.000 abstract 4
- 229910015900 BF3 Inorganic materials 0.000 abstract 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 55
- 238000005476 soldering Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はプリント配線板の製造方
法に係り、特に表面実装用パッドを有するプリント配線
板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a printed wiring board, and more particularly to a method of manufacturing a printed wiring board having surface mounting pads.
【０００２】0002
【従来の技術】電子機器類の軽量化ないしコンパクト化
を目的として、回路機構の小形化なども図られている。
すなわち、プリント配線板面に所要の電子部品を実装し
て成る実装回路装置（実装回路ユニット）が、各種の電
子機器類で広く実用に供されつつあり、またこのために
、高密度プリント配線板の開発も進められている。2. Description of the Related Art In order to make electronic equipment lighter and more compact, attempts have been made to make circuit mechanisms smaller. In other words, mounted circuit devices (mounted circuit units), which are formed by mounting necessary electronic components on the surface of a printed wiring board, are being widely put into practical use in various electronic devices, and for this purpose, high-density printed wiring boards Development is also progressing.
【０００３】ところで、前記表面実装用の高密度プリン
ト配線板の製造方法としては、次のような手段が知られ
ている。By the way, the following method is known as a method of manufacturing the high-density printed wiring board for surface mounting.
【０００４】（ａ） エッチングレジストとして、電解
半田めっき層を用いて選択エッチングを行い、表面実装
用パッドを含む導体回路全体を、銅（下地層）およびめ
っきされた半田（上層）の２層構造に形成する半田めっ
きプリント配線板の製造方法。(a) Selective etching is performed using an electrolytic solder plating layer as an etching resist, and the entire conductor circuit including surface mounting pads is formed into a two-layer structure of copper (base layer) and plated solder (upper layer). A method for manufacturing a solder-plated printed wiring board.
【０００５】（ｂ） 表面実装用パッド領域以外の導体
回路パターン上に、ソルダーレジストをコーティングし
、その後ホットエアーレベリングによって、前記表面実
装用パッド領域面上に選択的に半田層を形成するホット
エアーレベリングプリント配線板の製造方法。(b) Hot air coating of a conductive circuit pattern other than the surface mounting pad area with a solder resist, and then hot air leveling to selectively form a solder layer on the surface of the surface mounting pad area. A method for manufacturing a leveling printed wiring board.
【０００６】（ｃ） 表面実装用パッドを含む導体回路
パターンの形成を、エッチングレジストパターンの被着
、選択エッチングおよびエッチングレジストパターンの
剥離によって、前記導体回路パターンを銅の１層構造と
し、ソルダーレジスト非被覆面にプリフラックスをコー
ティングするプリフラックスプリント配線板の製造方法
。
（ｄ） 選択エッチングによって表面実装用パッドを含
む導体回路パターン形成し、さらにソルダーレジストを
コーティングした後、所要の表面実装用パッドから給電
用めっきリードを引き出し、前記所要の表面実装用パッ
ド面上にのみ選択的に電解半田層を析出させる部分電解
半田めっきプリント配線板の製造方法。(c) Formation of a conductive circuit pattern including surface mounting pads by applying an etching resist pattern, selective etching, and peeling off the etching resist pattern to form the conductive circuit pattern into a single layer structure of copper, and solder resist. A method for manufacturing a preflux printed wiring board in which an uncoated surface is coated with preflux. (d) After forming a conductive circuit pattern including surface mounting pads by selective etching and further coating with solder resist, pull out the plated leads for power supply from the required surface mounting pads and place them on the surface of the required surface mounting pads. A method for manufacturing a partially electrolytic solder plated printed wiring board in which an electrolytic solder layer is selectively deposited.
【０００７】[0007]
【発明が解決しようとする課題】しかし、上記表面実装
用プリント配線板の製造方法には、実用上次のような問
題がある。[Problems to be Solved by the Invention] However, the above-mentioned method of manufacturing a printed wiring board for surface mounting has the following practical problems.
【０００８】先ず、（ａ） の半田めっきプリント配線
板の製造方法で得られるプリント配線板の場合は、導体
回路の細密化（配線の高密度化）に伴い、実装部品を半
田付けする際、ソルダーレジストで覆われた導体回路（
パターン）部分において、半田ブリッジを起こし易いと
いう不都合がある。First, in the case of a printed wiring board obtained by the method (a) for manufacturing a solder-plated printed wiring board, due to the miniaturization of conductor circuits (higher wiring density), when soldering mounted components, Conductor circuit covered with solder resist (
There is an inconvenience that solder bridges are likely to occur in the pattern portion.
【０００９】（ｂ） のホットエアーレベリングプリン
ト配線板の製造方法で得られるプリント配線板の場合は
、被半田付け部以外がソルダーレジストで被覆されてい
るため、半田ブリッジの起生は回避されるが、ホットエ
アーレベリングされた半田（上層）の厚さが均一でない
ため（均一な厚さに被着するのは事実上至難）、実装部
品の半田付け不良が起こり易いという不都合がある。[0009] In the case of the printed wiring board obtained by the hot air leveling printed wiring board manufacturing method of (b), the parts other than the parts to be soldered are covered with solder resist, so the occurrence of solder bridges is avoided. However, since the thickness of the hot air leveled solder (upper layer) is not uniform (it is virtually impossible to adhere to a uniform thickness), there is a disadvantage that soldering defects of mounted components are likely to occur.
【００１０】（ｃ） のプリフラックスプリント配線板
の製造方法で得られるプリント配線板の場合も、被半田
付け部以外がソルダーレジスト３で被覆されているため
、半田ブリッジの起生は回避されるが、所要の電子部品
を実装するに先立って、表面実装用パッド面に印刷法な
どによって、半田ペーストを被着する必要があり、表面
実装用パッドが０．５ｍｍ 程度以下に狭ピッチ化して
くると、印刷による半田ペーストの被着が困難となって
量産に不適となる。[0010] Also in the case of the printed wiring board obtained by the preflux printed wiring board manufacturing method of (c), since the parts other than the parts to be soldered are covered with the solder resist 3, the occurrence of solder bridges is avoided. However, before mounting the required electronic components, it is necessary to apply solder paste to the surface of the surface mounting pad using a printing method, and the pitch of the surface mounting pad becomes narrower to about 0.5 mm or less. This makes it difficult to apply solder paste by printing, making it unsuitable for mass production.
【００１１】（ｄ） の部分電解半田めっきプリント配
線板の製造方法の場合は、電解半田めっき層を被覆する
表面実装用パッドごとに、給電用めっきリードを引き出
す必要があるため、回路パターンの配線密度が必然的に
低下するという問題がある。In the case of the manufacturing method of the partial electrolytic solder plated printed wiring board (d), it is necessary to pull out the power supply plated lead for each surface mounting pad covering the electrolytic solder plated layer, so the wiring of the circuit pattern is The problem is that the density necessarily decreases.
【００１２】本発明は上記事情に対処してなされたもの
で、配線密度を低下させることなく、電子部品の実装に
当たって印刷による半田ペーストの被着なども不要で、
表面実装用に好適するプリント配線板を容易に得ること
ができるプリント配線板の製造方法の提供を目的とする
。The present invention has been made in response to the above-mentioned circumstances, and does not require the application of solder paste by printing when mounting electronic components without reducing the wiring density.
An object of the present invention is to provide a method for manufacturing a printed wiring board that can easily produce a printed wiring board suitable for surface mounting.
【００１３】[0013]
【課題を解決するための手段】本発明に係るプリント配
線板の製造方法は、絶縁性基板の主面に一体的に配設さ
れた導体層面にを表面実装用パッドを含む所要の回路パ
ターンをパターンニングする工程と、前記形成した回路
パターンニングした面に電解半田めっき層を被着形成す
る工程と、前記被着形成した電解半田めっき層をエッチ
ングレジストとして露出している導体層を選択エッチン
グして表面実装用パッドを含む所要の回路パターンを形
成する工程と、前記形成した少なくとも表面実装用パッ
ドを含む所定の回路パターン部にマスキングする工程と
、前記マスキングした領域以外の露出する電解半田めっ
き層を除去する工程とを具備して成ることを特徴とする
。[Means for Solving the Problems] A method for manufacturing a printed wiring board according to the present invention includes forming a required circuit pattern including surface mounting pads on a conductor layer surface integrally provided on the main surface of an insulating substrate. a step of patterning, a step of depositing an electrolytic solder plating layer on the surface patterned with the formed circuit, and a step of selectively etching the exposed conductor layer using the deposited electrolytic solder plating layer as an etching resist. a step of forming a required circuit pattern including a surface mounting pad, a step of masking the formed predetermined circuit pattern portion including at least the surface mounting pad, and an exposed electrolytic solder plating layer other than the masked area. The method is characterized by comprising a step of removing.
【００１４】[0014]
【作用】本発明に係るプリント配線板の製造方法におい
ては、少なくとも表面実装用パッドを含む所要の回路パ
ターンを形成する段階に先立って、この回路パターン用
の導体層を共通の給電用リードとして利用し、回路パタ
ーンの全面に選択的に電解半田めっき層を被着形成した
後、回路パターン形成に用いたレジストを剥離・除去す
る。その後、電解半田めっき層で被覆されていない導体
層を選択的にエッチングしてから、少なくとも表面実装
用パッド面（領域）をマスキングして、不要な部分（領
域）の半田めっき層を選択除去する。つまり、将来電子
部品を搭載・実装するため露出させておくパッド面やス
ルホールに、対応する給電用リードを各別に取り出す必
要もなく、所要の電解半田めっき層が選択的に被着形成
される。したがって、配線密度を低下させることなく、
また表面実装用パッドが０．３ｍｍ 程度の狭ピッチの
場合でも、所要の半田層が設けられたプリント配線板を
容易に得ることができる。[Operation] In the method for manufacturing a printed wiring board according to the present invention, prior to the step of forming a required circuit pattern including at least surface mounting pads, the conductor layer for the circuit pattern is used as a common power supply lead. After selectively forming an electrolytic solder plating layer on the entire surface of the circuit pattern, the resist used for forming the circuit pattern is peeled off and removed. After that, the conductor layer that is not covered with the electrolytic solder plating layer is selectively etched, and at least the surface mounting pad surface (area) is masked, and the solder plating layer in unnecessary parts (areas) is selectively removed. . In other words, the required electrolytic solder plating layer can be selectively deposited on the pad surface or through-hole that will be exposed in order to mount and mount electronic components in the future, without the need to separately take out the corresponding power supply leads. Therefore, without reducing wiring density,
Further, even when the surface mounting pads have a narrow pitch of about 0.3 mm, a printed wiring board provided with the required solder layer can be easily obtained.
【００１５】[0015]
【実施例】以下図１（ａ） 〜（ｉ） を参照して本発
明の実施例を説明する。Embodiments Embodiments of the present invention will be described below with reference to FIGS. 1(a) to 1(i).
【００１６】第１図（ａ） 〜（ｉ） は本発明に係る
プリント配線板の製造方法の実施態様例を模式的に示し
た断面図である。先ず、主面に銅箔層１が一体的に配設
されたプリント配線板用の積層板２を用意し、所要の箇
所（位置）に孔明け加工を施して電気的な接続用の孔３
を形設する。次いで、前記孔明け加工した積層板２の銅
箔層１面上に、要すれば厚付け化学銅めっき（ ２μｍ
程度）や薄付けの化学銅めっき後のパネル銅めっき層
（１０μｍ程度）を形成してから、ドライフィルムをラ
ミネートして露光、現像を行うことによりパターンマス
キング４し、パターン銅めっき処理を施して接続用の孔
３の内壁面を含む露出面に厚さ２５μｍｍ程度の銅めっ
き層５を被着・形成する（図１（ａ） ）。FIGS. 1(a) to 1(i) are sectional views schematically showing an embodiment of the method for manufacturing a printed wiring board according to the present invention. First, a laminate 2 for a printed wiring board having a copper foil layer 1 integrally disposed on its main surface is prepared, and holes 3 for electrical connection are formed by drilling holes at required locations (positions).
form. Next, if necessary, thick chemical copper plating (2 μm
After forming a copper plating layer (approximately 10 μm) after thin chemical copper plating, pattern masking 4 is performed by laminating a dry film, exposure and development, and pattern copper plating treatment is performed. A copper plating layer 5 having a thickness of about 25 μmm is deposited and formed on the exposed surface including the inner wall surface of the connection hole 3 (FIG. 1(a)).
【００１７】その後、前記銅めっき層５を被着・形成し
た積層板２を、たとえばホウフッ酸系半田めっき浴に浸
漬し、前記積層板２の銅箔層１を給電用リードとして、
電解半田めっき処理を行い露出している面に厚さ１０μ
ｍｍ程度以上の半田めっき層６を被着形成した（図１（
ｂ） ）。次いで、前記パターンマスク４を剥離、除去
し（図１（ｃ） ）、常套の手段によって所要の回路パ
ターンを形成した。つまり、前記電解半田めっき層６を
エッチングレジストとして、パターンマスク４の除去に
よって露出した銅箔層１を選択的にエッチング除去して
表面実装用パッドなど含む回路パターンを形成する（図
１（ｄ））。Thereafter, the laminate 2 on which the copper plating layer 5 has been deposited and formed is immersed in, for example, a borofluoric acid solder plating bath, and the copper foil layer 1 of the laminate 2 is used as a power supply lead.
Electrolytic solder plating is applied to the exposed surface to a thickness of 10μ.
A solder plating layer 6 with a thickness of about mm or more was deposited (Fig. 1 (
b) ). Next, the pattern mask 4 was peeled off and removed (FIG. 1(c)), and a desired circuit pattern was formed by conventional means. That is, using the electrolytic solder plating layer 6 as an etching resist, the copper foil layer 1 exposed by removing the pattern mask 4 is selectively etched away to form a circuit pattern including surface mounting pads (FIG. 1(d)). ).
【００１８】上記により表面実装用パッドなど含む回路
パターンを形成した後、たとえばドライフィルムのよう
な感光性材料を真空ラミネータなどを用いてラミネート
し、前記電解半田めっき層６の被着形成されている回路
パターン中、電解半田めっき層６を残しておきたい領域
、すなわち表面実装用パッド面上やスルホール（接続用
の孔）３領域面上を、感光性材料層でマスキング７する
ように露光−現像し（図１（ｅ） ）、露出している部
分（領域）の電解半田めっき層６を選択的に除去する（
図１（ｆ） ）。次いで、前記感光性のマスク７を剥離
・除去（図１（ｇ） ）してからフュージング処理を行
なう。なお、このフュージング処理において、電解半田
めっき層６の流出を防止するため、電解半田めっき層６
の近傍などにソルダーレジスト８を印刷、被着した後（
図１（ｈ） ）、いわゆるフュージング処理を行い、前
記ソルダーレジスト８を流動化ないし軟化させて一様化
する（図１（ｉ） ）。前記フュージング処理後、所要
の外形加工、電気検査を行って所望の表面実装用に適す
るプリント配線板が得られる。After forming a circuit pattern including surface mounting pads as described above, a photosensitive material such as a dry film is laminated using a vacuum laminator, and the electrolytic solder plating layer 6 is formed. In the circuit pattern, the areas where the electrolytic solder plating layer 6 is desired to remain, that is, the surface of the surface mounting pad and the surface of the three through holes (holes for connection) are exposed and developed so as to be masked 7 with a photosensitive material layer. (FIG. 1(e)), and selectively removes the exposed portion (region) of the electrolytic solder plating layer 6 (FIG. 1(e)).
Figure 1(f)). Next, the photosensitive mask 7 is peeled off and removed (FIG. 1(g)), and then a fusing process is performed. In addition, in this fusing process, in order to prevent the electrolytic solder plating layer 6 from flowing out, the electrolytic solder plating layer 6
After printing and applying the solder resist 8 near the (
1(h)), a so-called fusing process is performed to fluidize or soften the solder resist 8 and make it uniform (FIG. 1(i)). After the fusing treatment, required external processing and electrical inspection are performed to obtain a printed wiring board suitable for desired surface mounting.
【００１９】なお、上記においては回路パターンを銅箔
層の選択的なエッチングによって形成したが、他の導電
性金属層の選択的なエッチングによって形成してもよく
、さらに片面型もしくは多層配線型であっても勿論よい
。Although the circuit pattern is formed by selectively etching the copper foil layer in the above example, it may also be formed by selectively etching other conductive metal layers. Of course it's fine.
【００２０】また、上記実施例では表面実装用パッド面
上およびスルホール（接続用の孔）領域に、選択的に電
解半田めっき層６を設けた構成を例示したが、たとえば
接続用の孔を電子部品のリード端子接続に利用しない場
合など、接続用の孔領域には電解半田めっき層６を設け
ない構成としてもよく、あるいは表面実装用パッドを含
む回路パターン中、表面実装用パッド部とともに表面実
装用パッド以外の領域に電解半田めっき層６を設けた構
成としてもよい。Further, in the above embodiment, the electrolytic solder plating layer 6 is selectively provided on the surface mounting pad surface and in the through-hole (connection hole) region, but for example, the connection hole is In cases where the electrolytic solder plating layer 6 is not provided in the connection hole area, such as when not used for connecting lead terminals of components, the electrolytic solder plating layer 6 may not be provided in the connection hole area, or if the electrolytic solder plating layer 6 is not provided in the connection hole area, or in a circuit pattern that includes surface mounting pads, surface mounting It is also possible to have a structure in which the electrolytic solder plating layer 6 is provided in a region other than the pad for use.
【００２１】[0021]
【発明の効果】上記したように本発明に係るプリント配
線板の製造方法によれば、繁雑な操作を要せずに高密度
の実装が可能で、かつ配線密度も高いプリント配線板を
容易に得ることができる。すなわち、選択エッチングに
よる回路パターン形成に先立って、被選択エッチング導
電金属層を給電用リードとし、少なくとも表面実装用パ
ッド面に、電解半田めっき層を形成する方式を採ってい
るため、給電用リードを別設する必要もなくなり操作が
簡略化する。また、給電用リードを不要とする分、配線
密度の低下も回避される。しかして、表面実装用パッド
をたとえば０．３ｍｍ以下の狭ピッチに設定することが
可能で、またその場合でも厚さ１０μｍ 以上で、かつ
厚さもほぼ一様な電解半田めっき層が被着形成されるた
め、実装に当たっての半田付け機能を十分に保持・発揮
する。[Effects of the Invention] As described above, according to the method of manufacturing a printed wiring board according to the present invention, a printed wiring board that can be mounted at a high density without requiring complicated operations and has a high wiring density can be easily produced. Obtainable. That is, prior to forming a circuit pattern by selective etching, the conductive metal layer to be selectively etched is used as a power supply lead, and an electrolytic solder plating layer is formed at least on the surface of the surface mounting pad. There is no need to install it separately, which simplifies the operation. Further, since a power supply lead is not required, a decrease in wiring density is also avoided. Therefore, it is possible to set the surface mounting pads at a narrow pitch of, for example, 0.3 mm or less, and even in that case, an electrolytic solder plating layer with a thickness of 10 μm or more and a substantially uniform thickness can be formed. Therefore, the soldering function is sufficiently maintained and exerted during mounting.
【図１】図１（ａ） 〜（ｉ） は本発明に係るプリン
ト配線板の製造方法の実施態様を模式的に示すもので、
（ａ） は接続用孔を穿設した銅箔張積層板面に選択的
に銅めっき層を設けた状態を示す断面図、（ｂ） は選
択的に設けた銅めっき層上に電解半田層を設けた状態を
示す断面図、（ｃ） は銅めっき層および電解半田層を
選択的に設ける際用いたパターンマスクを剥離・除去し
た状態を示す断面図、（ｄ） は選択エッチングして表
面実装用パッドを含む回路パターンを形成した状態を示
す断面図、（ｅ） は電解半田層を選択的に除去するた
めマスキングした状態を示す断面図、（ｆ）は電解半田
層を選択的に除去した状態を示す断面図、（ｇ） 電解
半田層の選択的な除去後マスキングを剥離・除去した状
態を示す断面図、（ｈ） は被着残存している電解半田
層の近傍にソルダレジスト層を設けた状態を示す断面図
、（ｉ） は被着残存している電解半田層を流動一様化
した状態を示す断面図。1(a) to 1(i) schematically show an embodiment of a method for manufacturing a printed wiring board according to the present invention,
(a) is a cross-sectional view showing a state in which a copper plating layer is selectively provided on the surface of a copper foil-clad laminate with connection holes, and (b) is an electrolytic solder layer on the selectively provided copper plating layer. (c) is a cross-sectional view showing the state where the pattern mask used to selectively provide the copper plating layer and electrolytic solder layer has been peeled off and removed; (d) is the surface after selective etching. A cross-sectional view showing a state in which a circuit pattern including mounting pads is formed, (e) a cross-sectional view showing a state in which the electrolytic solder layer is masked to selectively remove it, and (f) a cross-sectional view showing a state in which the electrolytic solder layer is selectively removed. (g) is a cross-sectional view showing the state where the masking has been peeled off and removed after selectively removing the electrolytic solder layer; (h) is a solder resist layer near the remaining electrolytic solder layer. (i) is a cross-sectional view showing a state in which the remaining electrolytic solder layer has been made to flow uniformly;
Claims (1)
た導体層面に表面実装用パッドを含む所要の回路パター
ンをパターンニングする工程と、前記回路パターンニン
グした面に電解半田めっき層を被着形成する工程と、前
記被着形成した電解半田めっき層をエッチングレジスト
として露出している導体層を選択エッチングして表面実
装用パッドを含む所要の回路パターンを形成する工程と
、前記形成した少なくとも表面実装用パッドを含む所定
の回路パターン部にマスキングする工程と、前記マスキ
ングした領域以外の露出する電解半田めっき層を除去す
る工程とを具備して成ることを特徴とするプリント配線
板の製造方法。1. A step of patterning a required circuit pattern including surface mounting pads on a conductor layer surface integrally provided on the main surface of an insulating substrate, and forming an electrolytic solder plating layer on the circuit patterned surface. a step of selectively etching the exposed conductor layer using the electrolytic solder plating layer formed as an etching resist to form a required circuit pattern including a surface mounting pad; A printed wiring board comprising the steps of: masking a predetermined circuit pattern portion including at least a surface mounting pad; and removing an exposed electrolytic solder plating layer other than the masked area. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18256391A JPH04355994A (en) | 1990-11-30 | 1991-07-23 | Manufacture of printed wiring board |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2-335587 | 1990-11-30 | ||
| JP33558790 | 1990-11-30 | ||
| JP18256391A JPH04355994A (en) | 1990-11-30 | 1991-07-23 | Manufacture of printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04355994A true JPH04355994A (en) | 1992-12-09 |
Family
ID=26501314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18256391A Withdrawn JPH04355994A (en) | 1990-11-30 | 1991-07-23 | Manufacture of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04355994A (en) |
-
1991
- 1991-07-23 JP JP18256391A patent/JPH04355994A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981008 |