JPH01295489A - Manufacture of printed wiring board and wiring board obtained by this manufacturing method - Google Patents
Manufacture of printed wiring board and wiring board obtained by this manufacturing methodInfo
- Publication number
- JPH01295489A JPH01295489A JP12665488A JP12665488A JPH01295489A JP H01295489 A JPH01295489 A JP H01295489A JP 12665488 A JP12665488 A JP 12665488A JP 12665488 A JP12665488 A JP 12665488A JP H01295489 A JPH01295489 A JP H01295489A
- Authority
- JP
- Japan
- Prior art keywords
- solder resist
- wiring board
- circuit
- insulating resin
- ink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910000679 solder Inorganic materials 0.000 claims abstract description 41
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 16
- 229920005989 resin Polymers 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 238000000034 method Methods 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 13
- 238000007747 plating Methods 0.000 description 13
- 238000007639 printing Methods 0.000 description 11
- 238000009413 insulation Methods 0.000 description 8
- 239000000126 substance Substances 0.000 description 5
- 230000035939 shock Effects 0.000 description 4
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ソルダーレジストを使用した印刷配線板の製
造法とその製造法によって得られる配線板に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a printed wiring board using a solder resist and a wiring board obtained by the manufacturing method.
（従来の技術）
通常行われている印刷配線板の製造法として、銅張り積
層板に穴明は後全面に化学銅メツキを施してから、感光
性樹脂フィルムをラミネートし、回路となる部分、パッ
ドとなる部分及びスルーホールの両側部分を残して現像
し、この残ったフィルムをエツチングレジストとして、
回路以外の不要部分の銅を除去し、ソフトエツチング又
はジ−グライド研磨等の前処理を行ない印刷法によりソ
ルダーレジストを形成し印刷配線板とする方法がある。(Prior art) As a common method for manufacturing printed wiring boards, after drilling holes in a copper-clad laminate, chemical copper plating is applied to the entire surface, and then a photosensitive resin film is laminated to form the circuit parts. Develop it leaving the part that will become the pad and the parts on both sides of the through hole, and use the remaining film as an etching resist.
There is a method of removing copper from unnecessary parts other than the circuit, performing pre-treatment such as soft etching or ziglide polishing, and forming a solder resist by a printing method to form a printed wiring board.
（発明が解決しようとする課題）
印刷法によりソルダーレジストを形成する場合、配線板
の回路導体のうち接続に必要とされるランド部周辺にお
いては、ソルダーレジストのパターン形状をランド部へ
のレジストの付着を避けるためそのランド部より印刷位
置ズレ等を考慮した分大きく逃げたパターンとすること
が一般的であり、ソルダーレジストを形成したランド部
周辺には必ず基材表面が露出する部分が現れる。この露
出した基材表面は、銅箔粗化形状が基材に転写され非常
に複雑な表面状態となっており、印刷配線板に電子部品
を搭載した時に付着した汚れ例えばフラックス残渣等を
完全に除去することが困難であるために、絶縁不良等が
発生する場合がある。(Problem to be Solved by the Invention) When forming a solder resist by a printing method, the pattern shape of the solder resist is changed to the shape of the resist to the land in the vicinity of the land required for connection among the circuit conductors of the wiring board. In order to avoid adhesion, it is common to create a pattern that is far away from the land portion by taking into consideration printing position deviation, etc., and there will always be a portion where the surface of the base material is exposed around the land portion where the solder resist is formed. This exposed surface of the base material has a very complex surface condition due to the roughened copper foil shape being transferred to the base material, and dirt such as flux residue that adheres when electronic components are mounted on the printed wiring board is completely removed. Since it is difficult to remove, insulation defects may occur.
更に、露出した基材表面は、基材に使用されている樹脂
が比較的吸湿性の高い材料であるため、吸湿による絶縁
劣化の原因になり、また、はんだ付は等の熱衝撃により
基材中の水分の急激な体積の増加によって基材にクラン
クが発生するという問題がある。Furthermore, since the resin used for the base material is a relatively highly hygroscopic material, the exposed surface of the base material may cause insulation deterioration due to moisture absorption, and the base material may be damaged due to thermal shock during soldering. There is a problem in that cranks occur in the base material due to a sudden increase in the volume of moisture inside.
本発明は、このような問題を解決し、接続に必要なラン
ド部へのソルダーレジストの付着がなく絶縁特性及び吸
湿特性に優れた配線板の製造法を提供するものである。The present invention solves these problems and provides a method for manufacturing a wiring board that is free from adhesion of solder resist to land portions necessary for connection and has excellent insulation properties and moisture absorption properties.
（課題を解決するための手段）
本発明は、低粘度のソルダーレジストインクを回路導体
の無い部分に適当量塗布すると、その低粘度のために回
路導体の無い部分を覆うように流れ、回路導体が堰とな
って回路導体の表面に付着しないという知見に基づいて
なされたものであり、回路導体及びスルーホールを形成
した絶縁樹脂基板の回路パターン以外の部分に、低粘度
のソルダーレジスト用インクを塗布し、回路パターン以
外の部分にそのソルダーレジストインクが露出した絶縁
樹脂基板の表面を覆った後、接続に必要なランド部を除
いてソルダーレジストを形成することを特徴とする印刷
配線板の製造法と、その製造法によって得られる回路導
体及びスルーホールを形成した絶縁樹脂基板において、
接続に必要なランド部以外が全てソルダーレジストに覆
われた印刷配線板である。(Means for Solving the Problems) The present invention provides that when an appropriate amount of low-viscosity solder resist ink is applied to a part without a circuit conductor, the low viscosity causes it to flow to cover the part without a circuit conductor. This was done based on the knowledge that the ink acts as a dam and does not adhere to the surface of the circuit conductor, and low viscosity solder resist ink is applied to the parts other than the circuit pattern of the insulating resin board where the circuit conductor and through holes are formed. After applying the solder resist ink to the exposed surface of the insulating resin substrate in areas other than the circuit pattern, a solder resist is formed except for the land areas necessary for connection. method and an insulating resin substrate with circuit conductors and through holes formed by the manufacturing method,
This is a printed wiring board in which everything except the land areas necessary for connection is covered with solder resist.
本発明において用いることのできる回路導体及びスルー
ホールを形成した絶縁樹脂基板は、絶縁樹脂基板の両面
に銅箔を貼り合わせた両面銅張積層板にスルーホールと
なる孔をあけその孔内及びその積層板の表面の全面に化
学銅めっき及び電気銅めっきを行い必要な部分のみを残
して他の部分をエツチング除去する方法（以下サブトラ
クティブ法という、）、又は、絶縁樹脂基板にスルーホ
ールとなる孔をあけ必要な部分にのみ化学銅めっき又は
化学銅めっきと電気銅めっきを行い導体回路を形成する
方法（以下アディティブ法という。The insulating resin substrate on which circuit conductors and through holes are formed can be used in the present invention by forming holes to serve as through holes in a double-sided copper-clad laminate made by laminating copper foil on both sides of the insulating resin substrate. A method in which chemical copper plating and electrolytic copper plating is applied to the entire surface of the laminate, leaving only the necessary parts and etching away the other parts (hereinafter referred to as the subtractive method), or through-holes are formed in the insulating resin substrate. A method in which a conductor circuit is formed by drilling holes and performing chemical copper plating or chemical copper plating and electrolytic copper plating only on the necessary areas (hereinafter referred to as the additive method).
）によって得られる配線板であって、導体回路と絶縁樹
脂基板とに段差があるものであればどのようなものでも
よい、低粘度のソルダーレジストインクを回路導体の無
い部分に適当量塗布する方法としては、通常のスクリー
ン印刷法を用いることができ、回路導体の表面にソルダ
ーレジストが付着しないようにするためには、塗布する
範囲を印刷時のズレ量を考慮しその分大きく逃げたパタ
ーンに印刷するようにスクリーンのパターン形状を設計
し、また、流れたソルダーレジストが導体回路上に載ら
ないようにするためにソルダーレジストインクの量を導
体回路の厚さより薄く塗布する。) A method of applying an appropriate amount of low-viscosity solder resist ink to the areas where there are no circuit conductors, as long as there is a step between the conductor circuit and the insulating resin board. In order to prevent the solder resist from adhering to the surface of the circuit conductor, the area to be coated should be designed with a pattern that takes into account the amount of misalignment during printing. The pattern shape of the screen is designed to be printed, and the amount of solder resist ink is applied thinner than the thickness of the conductor circuit in order to prevent the flowing solder resist from being placed on the conductor circuit.
このソルダーレジストインクの塗布量は、通常スクリー
ン印刷法において行われるように、印刷するときのソル
ダーレジストインクの量を調節するとともにスキージの
移動速度、スクリーンと被印刷物との間隔等によって調
節する。また、回路導体の無い絶縁基板の表面を覆うた
めに必要な流れ量をえるために、ソルダーレジストイン
クの粘度は１０．０００ｃｐｓ以上好ましくは２０，０
００〜１００．０００ｃｐｓとする。 １００，０ＯＯ
ｃｐｓ以上とすると、流れ量が大きくなり過ぎソルダー
レジストの厚さが薄くなってソルダーレジストとしての
絶縁特性が損なわれるとともに、乾燥するに時間がかか
り過ぎて経済的でなくなる。The amount of solder resist ink applied is adjusted by adjusting the amount of solder resist ink during printing, the moving speed of the squeegee, the distance between the screen and the printing material, etc., as is normally done in screen printing. In addition, in order to obtain the flow rate necessary to cover the surface of an insulating substrate without circuit conductors, the viscosity of the solder resist ink is 10.000 cps or more, preferably 20.0 cps or more.
00 to 100.000 cps. 100,0OO
If it exceeds cps, the flow rate becomes too large and the thickness of the solder resist becomes thin, impairing the insulation properties as a solder resist, and it takes too much time to dry, making it uneconomical.
（作用）
このようにして得られた配線板は、接続に必要なランド
部以外が全てソルダーレジストに覆われているので、ソ
ルダーレジストを形成したランド部周辺に基材表面が露
出する部分がなく、印刷配線板に電子部品を搭載した時
に付着した汚れ例えばフラックス残渣等をほぼ完全に除
去することができるため、絶縁不良が発生することがな
い。(Function) In the wiring board obtained in this way, all areas other than the lands necessary for connection are covered with solder resist, so there is no exposed part of the base material surface around the lands where solder resist is formed. Since it is possible to almost completely remove dirt, such as flux residue, etc. that adheres when electronic components are mounted on a printed wiring board, no insulation defects occur.
更に、吸湿による絶縁劣化を避けることができ、はんだ
付は等の熱衝撃によっても基材中に水分が残らないので
基材にクラックが発生することがない。Furthermore, insulation deterioration due to moisture absorption can be avoided, and no cracks will occur in the base material because no moisture remains in the base material even when subjected to thermal shock during soldering.
（実施例）
第１図に示すように、絶縁樹脂基板Ｅ−６７（日立化成
工業株式会社、商品名）に数値制御ドリルマシンによっ
て所望の位置にスルーホールとなる孔をあけ、化学銅め
っき液であるＣＣ−４１めっき液（日立化成工業株式会
社、商品名）に浸漬して約２０μｍの厚さの銅めっき層
を形成する。(Example) As shown in Fig. 1, through-holes are drilled at desired positions on an insulating resin board E-67 (Hitachi Chemical Co., Ltd., trade name) using a numerically controlled drill machine, and then a chemical copper plating solution is applied. A copper plating layer with a thickness of about 20 μm is formed by immersing the copper plating solution in CC-41 plating solution (trade name, Hitachi Chemical Co., Ltd.).
この銅めっき層を形成した基板の銅めっき層を、第２図
に示すように、サブトラクト法により所定のパターンに
形成し導体回路３を得る。The copper plating layer of the substrate on which this copper plating layer has been formed is formed into a predetermined pattern by the subtract method, as shown in FIG. 2, to obtain a conductor circuit 3.
次に、第３図に示すように、導体回路３の無い部分に、
導体回路３より印刷のズレ盟約０．３ｍｍだけ大きく逃
げたパターンに印刷できる版を用いてソルダーレジスト
インクである５Ｒ−３０００（太陽インク株式会社、商
品名）を印刷塗布する。Next, as shown in FIG. 3, in the part where there is no conductor circuit 3,
Solder resist ink 5R-3000 (trade name, Taiyo Ink Co., Ltd.) is applied by printing using a printing plate capable of printing a pattern with a print deviation of about 0.3 mm larger than that of the conductor circuit 3.
この時、ソルダーレジストインクの粘度を２０．０００
ＣＰＳ程度の低粘度にするために溶剤メチルエチルケト
ンで希釈した。At this time, the viscosity of the solder resist ink was set to 20.000.
It was diluted with the solvent methyl ethyl ketone to make the viscosity as low as CPS.
その後所定の温度でソルダーレジストインキを硬化させ
ソルダーレジスト４を形成する。Thereafter, the solder resist ink is cured at a predetermined temperature to form the solder resist 4.
最後に、第４図に示すように、所定のパターンのスクリ
ーンを用い、ランド部以外の導体回路３を被覆するため
にソルダーレジストインクである５Ｒ−３０００（太陽
インク株式会社、商品名）を印刷塗布し、加熱硬化して
配線板とした。このソルダーレジストインクの粘度は約
３，０ＯＯｃｐｓとした。Finally, as shown in Fig. 4, using a screen with a predetermined pattern, solder resist ink 5R-3000 (trade name, Taiyo Ink Co., Ltd.) is printed to cover the conductor circuit 3 other than the land portion. It was coated and cured by heating to form a wiring board. The viscosity of this solder resist ink was approximately 3,000 cps.
比較例
実施例と同様にして得られた第２図に示す構造の導体回
路３を有する絶縁基板に、第３図で用いた印刷版を用い
て、ランド部から印刷時のズレ盟約０．３ｍｍだけ大き
い部分以外の導体回路３及び露出した絶縁基板の表面を
被覆するためにソルダーレジストインクである５Ｒ−３
０００（太陽インク株式会社、商品名）の粘度を約３．
０ＯＯｃｐｓとしたものを印刷塗布し、加熱硬化して配
線板とした。Comparative Example The printing plate used in FIG. 3 was used on an insulating substrate having a conductive circuit 3 having the structure shown in FIG. 5R-3, which is a solder resist ink, is used to cover the conductor circuit 3 and the exposed surface of the insulating substrate except for the large portion.
The viscosity of 000 (Taiyo Ink Co., Ltd., trade name) is approximately 3.
0OOcps was applied by printing and cured by heating to form a wiring board.
以上のようにして得られた配線板の絶縁抵抗値は、比較
例に比べ約５０〜１００分の１となり、また、２８０℃
のはんだ槽浸漬に１分浮かべる熱衝撃試験においても、
比較例の配線板において全試験片の約２％にクランクが
発生したのに比べ本発明の実施例による配線板はクラッ
クが発生しなかった。The insulation resistance value of the wiring board obtained as described above is about 50 to 100 times lower than that of the comparative example, and
In a thermal shock test of floating in a solder bath for 1 minute,
Cracks occurred in about 2% of all test pieces in the wiring board of the comparative example, but no cracks occurred in the wiring board according to the example of the present invention.
（発明の効果）
以上に説明したように、低粘度のソルダーレジストを用
いることにより、ランド部周辺の基材表面の露出をなく
すことができる印刷配線板の製造法を提供することがで
き、この製造法によって、絶縁特性や熱衝撃に対し高倍
転性の配線板を提供することができる。(Effects of the Invention) As explained above, by using a low viscosity solder resist, it is possible to provide a method for manufacturing a printed wiring board that can eliminate exposure of the base material surface around the land portions. Depending on the manufacturing method, it is possible to provide a wiring board with high insulation properties and high thermal shock resistance.
第１図から第４図は本発明の一実施例を示す配線板の製
造工程を説明する断面図である。
符号の説明
１、絶縁樹脂基板 ２．銅めっき層３、導体回路
４、低粘度のソルダーレジスト
第１図
第２図
第３図
、５
第４図1 to 4 are cross-sectional views illustrating the manufacturing process of a wiring board according to an embodiment of the present invention. Explanation of symbols 1. Insulating resin substrate 2. Copper plating layer 3, conductor circuit 4, low viscosity solder resist Fig. 1 Fig. 2 Fig. 3, 5 Fig. 4
Claims (2)
の回路パターン以外の部分に、低粘度のソルダーレジス
ト用インクを塗布し、回路パターン以外の部分にそのソ
ルダーレジストインクが露出した絶縁樹脂基板の表面を
覆った後、接続に必要なランド部を除いてソルダーレジ
ストを形成することを特徴とする印刷配線板の製造法。1. A low-viscosity solder resist ink is applied to the parts of the insulating resin board on which circuit conductors and through holes are formed other than the circuit pattern, and the solder resist ink covers the exposed surface of the insulating resin board in the parts other than the circuit pattern. After that, a solder resist is formed except for land areas necessary for connection.
において、接続に必要なランド部以外が全てソルダーレ
ジストに覆われた請求項１記載の製造法によって得られ
る印刷配線板。2. 2. A printed wiring board obtained by the manufacturing method according to claim 1, wherein in the insulating resin substrate on which circuit conductors and through holes are formed, all areas other than land portions necessary for connection are covered with a solder resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12665488A JPH01295489A (en) | 1988-05-24 | 1988-05-24 | Manufacture of printed wiring board and wiring board obtained by this manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12665488A JPH01295489A (en) | 1988-05-24 | 1988-05-24 | Manufacture of printed wiring board and wiring board obtained by this manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01295489A true JPH01295489A (en) | 1989-11-29 |
Family
ID=14940567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12665488A Pending JPH01295489A (en) | 1988-05-24 | 1988-05-24 | Manufacture of printed wiring board and wiring board obtained by this manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01295489A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1481575A2 (en) * | 2002-03-04 | 2004-12-01 | Printar Ltd. | Digital application of protective soldermask to printed circuit boards |
| JP2010050271A (en) * | 2008-08-21 | 2010-03-04 | Seiko Instruments Inc | Circuit board |
-
1988
- 1988-05-24 JP JP12665488A patent/JPH01295489A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1481575A2 (en) * | 2002-03-04 | 2004-12-01 | Printar Ltd. | Digital application of protective soldermask to printed circuit boards |
| EP1481575A4 (en) * | 2002-03-04 | 2007-11-28 | Printar Ltd | Digital application of protective soldermask to printed circuit boards |
| US7451699B2 (en) | 2002-03-04 | 2008-11-18 | Printar Ltd. | Digital application of protective soldermask to printed circuit boards |
| JP2010050271A (en) * | 2008-08-21 | 2010-03-04 | Seiko Instruments Inc | Circuit board |
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