JPH04318922A - Growth method for compound semiconductor crystal - Google Patents
Growth method for compound semiconductor crystalInfo
- Publication number
- JPH04318922A JPH04318922A JP8531391A JP8531391A JPH04318922A JP H04318922 A JPH04318922 A JP H04318922A JP 8531391 A JP8531391 A JP 8531391A JP 8531391 A JP8531391 A JP 8531391A JP H04318922 A JPH04318922 A JP H04318922A
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- compound semiconductor
- silicon substrate
- layer
- crystal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 150000001875 compounds Chemical class 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 239000013078 crystal Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 239000010703 silicon Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 40
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 238000002048 anodisation reaction Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 12
- 238000006243 chemical reaction Methods 0.000 description 10
- 239000007789 gas Substances 0.000 description 8
- 239000002994 raw material Substances 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910021426 porous silicon Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 125000002524 organometallic group Chemical group 0.000 description 2
- 238000005424 photoluminescence Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 210000002969 egg yolk Anatomy 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、シリコン基板上に化
合物半導体層、特にＩＩＩ−Ｖ族化合物半導体層および
／またはＩＩ−ＶＩ族化合物半導体層を成長させる方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for growing a compound semiconductor layer, particularly a III-V compound semiconductor layer and/or a II-VI compound semiconductor layer, on a silicon substrate.
【０００２】0002
【従来の技術】シリコン基板上に単一の成長温度で、Ｇ
ａＡｓ等の化合物半導体層を成長させても、多くの場合
、多結晶層しか成長させることができない。格子定数、
熱膨張係数および極性などの物性において、シリコンと
異なる化合物半導体をシリコン基板上に成長させて、良
好なエピタキシャル成長層を得るためには、通常のエピ
タキシャル成長方法とは異なった条件および手法が必要
となる。[Prior Art] G
Even if a compound semiconductor layer such as aAs is grown, in many cases only a polycrystalline layer can be grown. lattice constant,
In order to grow a compound semiconductor on a silicon substrate, which has physical properties different from silicon in terms of thermal expansion coefficient and polarity, and obtain a good epitaxial growth layer, conditions and techniques different from those of normal epitaxial growth methods are required.
【０００３】そこで、たとえば、図４に示すような温度
プロフィルで化合物半導体層を形成させる２段階成長法
が、従来、行なわれてきた。この方法では、まず、８０
０〜１０００℃の高温で、シリコン基板表面の清浄化を
行なう。次に、４００〜５００℃程度の低温で、たとえ
ば気相成長法により、厚さが数百堯以下の化合物半導体
層を形成する。最後に、通常の成長温度まで昇温して、
化合物半導体層を形成する。このように低温および通常
の温度の２段階でシリコン基板上に結晶成長させれば、
低温で形成された層が中間層として働き、中間層上に結
晶方位が揃った成長層を形成することができる。[0003] Therefore, a two-step growth method has conventionally been used in which a compound semiconductor layer is formed using a temperature profile as shown in FIG. 4, for example. In this method, first, 80
The silicon substrate surface is cleaned at a high temperature of 0 to 1000°C. Next, at a low temperature of about 400 to 500[deg.] C., a compound semiconductor layer having a thickness of several hundred yolks or less is formed by, for example, vapor phase growth. Finally, raise the temperature to the normal growth temperature,
Form a compound semiconductor layer. If crystals are grown on a silicon substrate in two stages: low temperature and normal temperature,
The layer formed at a low temperature acts as an intermediate layer, and a grown layer with uniform crystal orientation can be formed on the intermediate layer.
【０００４】しかし、上記２段階成長法による場合、中
間層の厚みを精度よく制御することが困難であった。こ
のため、中間層が薄くなって、その上に成長させる成長
層の表面が粗くなったり、逆に中間層が厚くなってしま
い、その後の成長層の形成において原子の並び換えが十
分に行なわれず、良好なエピタキシャル層を得ることが
できなかった。However, when using the above two-step growth method, it is difficult to accurately control the thickness of the intermediate layer. For this reason, the intermediate layer becomes thin, and the surface of the growth layer grown on it becomes rough, or conversely, the intermediate layer becomes thick, and atoms are not rearranged sufficiently in the formation of the subsequent growth layer. , it was not possible to obtain a good epitaxial layer.
【０００５】秋山らによる特開平１−２９０２２０には
、上記方法の問題を解決すべく、シリコン基板上に図５
に示すような温度プロフィルで、結晶層を形成する方法
が開示されている。この方法では、まず、シリコン基板
を９００〜１０００℃の温度で加熱処理した後、４００
〜４５０℃程度の低温でシリコン基板上に化合物半導体
からなる第１の中間層を形成する。次に、５５０〜６０
０℃の温度で、第１の中間層の上に化合物半導体の第２
の中間層をさらに成長させた後、６５０〜７５０℃の通
常の成長温度で、化合物半導体層を形成させる。このよ
うに３段階で結晶層を形成させることによって、第１の
中間層の厚みにばらつきがあったとしても、第２の中間
層の形成により結晶方位を揃え、かつ成長層の表面を平
滑にすることを可能にしている。[0005] To solve the problems of the above method, Akiyama et al. disclosed in Japanese Patent Application Laid-Open No. 1-290220 that a film of FIG.
A method of forming a crystalline layer with a temperature profile as shown in is disclosed. In this method, first, a silicon substrate is heat-treated at a temperature of 900 to 1000°C, and then heated to a temperature of 400°C.
A first intermediate layer made of a compound semiconductor is formed on a silicon substrate at a low temperature of about 450°C. Next, 550-60
A second intermediate layer of compound semiconductor is deposited on top of the first intermediate layer at a temperature of 0°C.
After further growth of the intermediate layer, a compound semiconductor layer is formed at a typical growth temperature of 650-750<0>C. By forming the crystal layer in three stages in this way, even if there is variation in the thickness of the first intermediate layer, the crystal orientation can be aligned by forming the second intermediate layer, and the surface of the growth layer can be smoothed. making it possible to do so.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、以上述
べてきた従来法は、シリコンと化合物半導体の間で熱膨
張係数が大きく異なる問題に対して、何ら効果的な対策
を講じたものではなかった。熱膨脹率の違いのために、
シリコン基板とその上に形成された化合物半導体層の間
には、歪が発生した。この歪は、化合物半導体層に残留
応力を生じさせ、転位を発生させやすくした。[Problems to be Solved by the Invention] However, the conventional methods described above have not taken any effective measures against the problem of large differences in thermal expansion coefficients between silicon and compound semiconductors. Due to the difference in coefficient of thermal expansion,
Strain occurred between the silicon substrate and the compound semiconductor layer formed thereon. This strain caused residual stress in the compound semiconductor layer, making it easier to generate dislocations.
【０００７】この発明の目的は、上述した熱膨張係数の
差による歪の影響を低減させて、転位密度のより低い化
合物半導体層をシリコン基板上に形成することができる
化合物半導体結晶の成長方法を提供することにある。An object of the present invention is to provide a method for growing compound semiconductor crystals that can reduce the influence of strain caused by the difference in thermal expansion coefficients mentioned above and form a compound semiconductor layer with a lower dislocation density on a silicon substrate. It is about providing.
【０００８】[0008]
【課題を解決するための手段】この発明に従う化合物半
導体結晶の成長方法は、シリコン基板上に化合物半導体
の結晶層を形成させる方法であって、シリコン基板の表
面を多孔質化する多孔質化工程と、多孔質化された表面
に、第１の温度で化合物半導体の第１の結晶層を成長さ
せる工程と、第１の結晶層上に第１の温度より高い第２
の温度で、化合物半導体の第２の結晶層を成長させる工
程と、第２の結晶層上に第２の温度より高い第３の温度
で、化合物半導体の第３の結晶層を成長させる工程とを
備えている。[Means for Solving the Problems] A method for growing a compound semiconductor crystal according to the present invention is a method for forming a crystal layer of a compound semiconductor on a silicon substrate, the method comprising a porous step of making the surface of the silicon substrate porous. a step of growing a first crystal layer of a compound semiconductor at a first temperature on the porous surface; and a step of growing a second crystal layer of a compound semiconductor at a temperature higher than the first temperature on the first crystal layer.
a step of growing a second crystal layer of the compound semiconductor at a temperature of , and a step of growing a third crystal layer of the compound semiconductor on the second crystal layer at a third temperature higher than the second temperature. It is equipped with
【０００９】シリコン基板の表面を多孔質化する方法と
しては、たとえば弗酸溶液中で陽極化成法によりシリコ
ン基板表面を多孔質化する方法を挙げることができる。
陽極化成法では、シリコン基板自身を陽極とし、一方、
たとえば白金電極を陰極として、これらを電解液に漬け
、電極間に所定の電流を流すことによりシリコン基板表
面を電気分解エッチングする。このような多孔質化シリ
コンの形成方法は、シリコン基板の電解研磨の研究過程
で発見されたものであり、比較的低電流の領域において
多孔質化の現象が起こる。文献（たとえば、伊藤利道，
加藤剛久：応用物理５７（１９８８）１７１０）等にお
いて、一般的に用いられている電流密度は、５〜２００
ｍＡ／ｃｍ２ である。また、多孔質化する層の厚みは
、特に限定されるものではないが、たとえば０．数μｍ
から数百μｍの厚みで形成させることができる。また多
孔質化した部分の孔径は、たとえば２０〜３００堯程度
の大きさとなる。この孔は、透過型電子顕微鏡（ＴＥＭ
）での観察結果などにより、縦方向に枝別れした樹枝状
に形成されていることが分かっている。[0009] As a method of making the surface of a silicon substrate porous, for example, there is a method of making the surface of a silicon substrate porous by anodization in a hydrofluoric acid solution. In the anodization method, the silicon substrate itself is used as the anode;
For example, using a platinum electrode as a cathode, the silicon substrate surface is electrolytically etched by immersing them in an electrolytic solution and passing a predetermined current between the electrodes. This method of forming porous silicon was discovered in the course of research on electrolytic polishing of silicon substrates, and the phenomenon of porosity occurs in a relatively low current region. Literature (e.g. Toshimichi Ito,
Takehisa Kato: Applied Physics 57 (1988) 1710), etc., the current density generally used is 5 to 200
mA/cm2. Further, the thickness of the layer to be made porous is not particularly limited, but for example, 0. A few μm
It can be formed with a thickness of several hundred μm. Further, the pore diameter of the porous portion is, for example, about 20 to 300 square meters. This hole can be seen under a transmission electron microscope (TEM).
), it is known that it is formed in a dendritic shape with vertical branches.
【００１０】この発明に従って結晶層を成長させるため
の望ましい温度は、たとえば、第１の温度について約２
００〜約５００℃の範囲、第２の温度について、第１の
温度より高く、かつ約４００〜約７００℃の範囲、第３
の温度について、第２の温度より高く、かつ約５００℃
〜約９００℃の範囲とすることができる。[0010] A desirable temperature for growing a crystalline layer in accordance with the present invention is, for example, about 2
00 to about 500°C, the second temperature is higher than the first temperature, and the third temperature is in the range of about 400 to about 700°C.
higher than the second temperature and about 500°C
to about 900°C.
【００１１】シリコン基板の上に堆積させる化合物半導
体は、ＩＩＩ−Ｖ族化合物半導体およびＩＩ−ＶＩ族化
合物半導体の少なくともいずれかとすることができ、よ
り詳細には、たとえば、ＧａＡｓ、ＧａＰおよびＩｎＰ
などのような２元系のＩＩＩ−Ｖ族化合物半導体または
、ＡｌＧａＡｓ、ＡｌＧａＰ、ＩｎＡｌＡｓ、ＩｎＡｌ
Ｐ、ＧａＡｓＰおよびＧａＩｎＰなどのような３元系の
ＩＩＩ−Ｖ族化合物半導体、さらには、ＺｎＳおよびＺ
ｎＳｅのようなＩＩ−ＶＩ族化合物半導体などから選ぶ
ことができる。また、複数種の化合物半導体の層をこの
発明に従ってシリコン基板上に堆積させることもできる
。[0011] The compound semiconductor deposited on the silicon substrate can be at least one of a III-V compound semiconductor and a II-VI compound semiconductor, and more specifically, for example, GaAs, GaP and InP.
Binary III-V compound semiconductors such as AlGaAs, AlGaP, InAlAs, InAl
Ternary group III-V compound semiconductors such as P, GaAsP and GaInP, as well as ZnS and Z
It can be selected from II-VI group compound semiconductors such as nSe. Also, layers of multiple compound semiconductors can be deposited on a silicon substrate according to the present invention.
【００１２】0012
【作用】多孔質化されたシリコン基板の上に化合物半導
体を成長させると、格子不整合による歪を緩和しながら
成長させることができるので、ミスフィット転位の発生
を防止できる。さらに多孔質化されたシリコンは通常の
シリコンに比べ、ヤング率が約１０分の１というように
柔軟性に富んでいる。したがって、ＩＩＩ−Ｖ族化合物
半導体とシリコンという熱膨張係数が大きく異なる組合
せであっても、２つの物質間の歪を多孔質部分で吸収さ
せることができるため、化合物半導体層における残留応
力および転位の発生を抑制することができる。このよう
に、この発明では、多孔質シリコンの特徴を活かすこと
によって、上述した問題点を解決している。[Operation] When a compound semiconductor is grown on a porous silicon substrate, the growth can be done while alleviating the strain caused by lattice mismatch, thereby preventing the occurrence of misfit dislocations. Furthermore, porous silicon has a Young's modulus that is approximately one-tenth that of normal silicon, making it highly flexible. Therefore, even if the combination of III-V compound semiconductor and silicon have significantly different coefficients of thermal expansion, the strain between the two materials can be absorbed by the porous portion, reducing residual stress and dislocation in the compound semiconductor layer. The occurrence can be suppressed. In this way, the present invention solves the above-mentioned problems by taking advantage of the characteristics of porous silicon.
【００１３】また、この発明では第１の温度で成長した
化合物半導体層の上に、第１の温度より高く、第１の結
晶層を構成する原子が十分に再配列して単一のドメイン
となる温度で、しかも通常の成長温度より低い第２の温
度で第２の化合物半導体層を成長させる。次に、この第
２の層の上に第２の温度より高い第３の温度で化合物半
導体層を成長させる。第１の結晶層と第３の結晶層の間
に第２の結晶層を成長させることにより、第１の結晶層
の厚みおよび成長速度等の成長条件のばらつきが補完さ
れ、第３の結晶層として、結晶方位の揃った十分に高品
質の化合物半導体層を形成させることができる。[0013] Further, in the present invention, the atoms constituting the first crystal layer are sufficiently rearranged to form a single domain at a temperature higher than the first temperature on the compound semiconductor layer grown at the first temperature. The second compound semiconductor layer is grown at a second temperature that is lower than the normal growth temperature. Next, a compound semiconductor layer is grown on this second layer at a third temperature higher than the second temperature. By growing the second crystal layer between the first crystal layer and the third crystal layer, variations in growth conditions such as the thickness and growth rate of the first crystal layer are compensated for, and the third crystal layer As a result, a sufficiently high quality compound semiconductor layer with uniform crystal orientation can be formed.
【００１４】[0014]
【実施例】この実施例ではシリコン基板の表面を多孔質
化し、その上に化合物半導体としてＧａＡｓ結晶を成長
させる場合について説明する。EXAMPLE In this example, a case will be explained in which the surface of a silicon substrate is made porous and GaAs crystal is grown thereon as a compound semiconductor.
【００１５】この実施例では、まず、シリコン基板を陽
極とし、白金電極を陰極として、５０％弗酸水溶液中、
電流密度２０ｍＡ／ｃｍ２ において、室温で２０分間
、電気分解を行なった。このようにして表面を多孔質化
したシリコン基板をエピタキシャル成長工程に供した。
エピタキシャル成長は、原料ガスとしてトリメチルガリ
ウム（Ｇａ（ＣＨ３ ）３ ）およびアルシン（ＡｓＨ
３ ）、キャリアガスとして水素（Ｈ２ ）を用いる有
機金属気相成長法によって行なった。成長を行なうため
の装置は通常一般的に用いられているものである。成長
時の温度プロフィルは、図１に示すとおりであった。図
において、横軸は時間、縦軸は温度を示している。図１
を参照して、まず、表面を多孔質化したシリコン基板を
装置の反応室に載置し、反応室の温度を４２０℃まで昇
温した後、原料ガスを反応室内に導入して、厚みが約１
５０堯となるまでＧａＡｓ層をシリコン基板上に成長さ
せた。
次に、原料ガスの導入を停止し、反応室の温度を５５０
℃まで昇温させた。この温度で、再び反応室内に原料ガ
スを導入して、第２のＧａＡｓ層を形成させた。次に、
原料ガスの導入を再び停止した後、反応室内を６５０℃
まで昇温し、再度原料ガスを導入して第３のＧａＡｓ層
を約２．５μｍの厚さで第２の結晶層上に形成させた。In this example, first, a silicon substrate was used as an anode and a platinum electrode was used as a cathode in a 50% hydrofluoric acid aqueous solution.
Electrolysis was carried out at a current density of 20 mA/cm2 at room temperature for 20 minutes. The silicon substrate whose surface was thus made porous was subjected to an epitaxial growth process. Epitaxial growth uses trimethylgallium (Ga(CH3)3) and arsine (AsH) as source gases.
3), was carried out by organometallic vapor phase epitaxy using hydrogen (H2) as a carrier gas. The equipment for carrying out the growth is generally of the type commonly used. The temperature profile during growth was as shown in FIG. In the figure, the horizontal axis represents time and the vertical axis represents temperature. Figure 1
First, a silicon substrate with a porous surface was placed in the reaction chamber of the device, and after raising the temperature of the reaction chamber to 420°C, raw material gas was introduced into the reaction chamber to increase the thickness. Approximately 1
A GaAs layer was grown on the silicon substrate to a thickness of 50 mm. Next, the introduction of the raw material gas is stopped, and the temperature of the reaction chamber is set to 550°C.
The temperature was raised to ℃. At this temperature, the raw material gas was again introduced into the reaction chamber to form a second GaAs layer. next,
After stopping the introduction of raw material gas again, the inside of the reaction chamber was heated to 650°C.
The temperature was raised to 2.5 μm, and the raw material gas was introduced again to form a third GaAs layer with a thickness of about 2.5 μm on the second crystal layer.
【００１６】比較として、図２および図３に示す温度プ
ロフィルを用いて結晶成長を行なった。結晶成長は上記
と同様にして有機金属気相成長法によって行なった。図
２に示す温度プロフィルを用いる方法では、多孔質化を
行なっていないシリコン基板を用いた。この方法におい
て、まず、シリコン基板を載置した反応室の温度を１０
００℃まで昇温し、シリコン基板表面の清浄化を行なっ
た。次に、成長室を４２０℃まで降温した後、上記と同
様にして厚さが約１５０堯のＧａＡｓ層をシリコン基板
上に形成した。次に、原料ガスの供給を停止して、反応
室内を６５０℃に昇温した後、さらにＧａＡｓ層を約２
．５μｍの厚さで堆積した。図３に示す温度プロフィル
を用いた方法では、上述したように表面を多孔質化した
シリコン基板を用いた。この方法において、まず、シリ
コン基板を載置した反応室の温度を４２０℃に昇温した
後、上記と同様にして約１５０堯の厚さのＧａＡｓ層を
形成させた。次に、原料ガスの供給を停止した後、反応
室を６５０℃まで昇温して、上記と同様にして約２．５
μｍの厚さのＧａＡｓ層を堆積した。For comparison, crystal growth was performed using the temperature profiles shown in FIGS. 2 and 3. Crystal growth was performed by organometallic vapor phase epitaxy in the same manner as above. In the method using the temperature profile shown in FIG. 2, a silicon substrate that was not made porous was used. In this method, first, the temperature of the reaction chamber in which the silicon substrate is placed is increased to 10
The temperature was raised to 00° C., and the surface of the silicon substrate was cleaned. Next, after lowering the temperature of the growth chamber to 420° C., a GaAs layer having a thickness of about 150 μm was formed on the silicon substrate in the same manner as above. Next, after stopping the supply of raw material gas and raising the temperature inside the reaction chamber to 650°C, the GaAs layer was
．． A thickness of 5 μm was deposited. In the method using the temperature profile shown in FIG. 3, a silicon substrate whose surface was made porous as described above was used. In this method, first, the temperature of the reaction chamber in which the silicon substrate was placed was raised to 420° C., and then a GaAs layer with a thickness of about 150 μm was formed in the same manner as above. Next, after stopping the supply of raw material gas, the temperature of the reaction chamber was raised to 650°C, and the temperature was increased to about 2.5°C in the same manner as above.
A μm thick GaAs layer was deposited.
【００１７】上記３つの方法（この発明に従う実施例お
よび２つの比較例）により作成したＧａＡｓ層をフォト
ルミネッセンスにより評価した。フォトルミネッセンス
で得られたピーク強度の比較の結果、図１に示す温度プ
ロフィルの方法により得られたＧａＡｓ層は、図２に示
す比較例に対して約２倍、図３に示す比較例に対して約
１０倍のピーク強度を示した。このことより、この発明
に従った図１の方法は、比較例よりも品質が改善された
結晶層を提供することが明らかになった。GaAs layers prepared by the above three methods (an example according to the present invention and two comparative examples) were evaluated by photoluminescence. As a result of comparing the peak intensities obtained by photoluminescence, the GaAs layer obtained by the temperature profile method shown in FIG. 1 was approximately twice as strong as the comparative example shown in FIG. The peak intensity was about 10 times that of the previous one. This reveals that the method of FIG. 1 according to the invention provides a crystalline layer with improved quality compared to the comparative example.
【００１８】なお、この発明は上述した実施例にのみ限
定されるものではなく、この発明に従って多くの変形ま
たは変更を行なうことができる。たとえば、成長させる
化合物半導体層については、上記ＧａＡｓのほかに、Ｇ
ａＰおよびＩｎＰなどのような２元系のＩＩＩ−Ｖ族化
合物半導体、ＡｌＧａＡｓ、ＡｌＧａＰ、ＩｎＡｌＡｓ
、ＩｎＡｌＰ、ＧａＡｓＰおよびＧａＩｎＰなどのよう
な３元系のＩＩＩ−Ｖ族化合物半導体、さらにはＺｎＳ
およびＺｎＳｅのようなＩＩ−ＶＩ族化合物半導体など
から選ぶことができるほか、これらの複数種の化合物半
導体層を積層させることもできる。また、成長層を形成
させるための方法は、上記有機金属気相成長法に限定さ
れず、その他の成長法を用いることができる。It should be noted that the present invention is not limited only to the embodiments described above, and many modifications and changes can be made in accordance with the present invention. For example, as for the compound semiconductor layer to be grown, in addition to the above-mentioned GaAs, G
Binary III-V compound semiconductors such as aP and InP, AlGaAs, AlGaP, InAlAs
, InAlP, GaAsP, GaInP, and other ternary group III-V compound semiconductors, as well as ZnS.
In addition to being able to select from group II-VI compound semiconductors such as and ZnSe, it is also possible to stack a plurality of these compound semiconductor layers. Further, the method for forming the growth layer is not limited to the metal organic vapor phase epitaxy method described above, and other growth methods can be used.
【００１９】[0019]
【発明の効果】以上説明してきたように、この発明に従
えば、シリコン基板とその上に形成される化合物半導体
との熱膨張率の差による歪の影響を低減させて、転位密
度のより低い化合物半導体層をシリコン基板上に形成す
ることができる。したがって、この発明の方法は、シリ
コン基板上により良質のヘテロエピタキシャル成長層を
形成するために効果的である。[Effects of the Invention] As explained above, according to the present invention, the influence of strain due to the difference in thermal expansion coefficient between a silicon substrate and a compound semiconductor formed thereon can be reduced, and dislocation density can be lowered. A compound semiconductor layer can be formed on a silicon substrate. Therefore, the method of the present invention is effective for forming a higher quality heteroepitaxial growth layer on a silicon substrate.
【図１】この発明に従う実施例において、結晶成長層を
形成するための温度プロフィルを示す図である。FIG. 1 is a diagram showing a temperature profile for forming a crystal growth layer in an embodiment according to the invention.
【図２】比較例において用いられた温度プロフィルを示
す図である。FIG. 2 is a diagram showing a temperature profile used in a comparative example.
【図３】他の比較例において用いられた温度プロフィル
を示す図である。FIG. 3 is a diagram showing a temperature profile used in another comparative example.
【図４】従来法において用いられる温度プロフィルを示
す図である。FIG. 4 is a diagram showing a temperature profile used in a conventional method.
【図５】他の従来法において用いられる温度プロフィル
を示す図である。FIG. 5 is a diagram showing a temperature profile used in another conventional method.
Claims (4)
晶層を形成させる方法であって、前記シリコン基板の表
面を多孔質化する多孔質化工程と、多孔質化された前記
表面に、第１の温度で前記化合物半導体の第１の結晶層
を成長させる工程と、前記第１の結晶層上に、前記第１
の温度より高い第２の温度で、前記化合物半導体の第２
の結晶層を成長させる工程と、前記第２の結晶層上に、
前記第２の温度より高い第３の温度で、前記化合物半導
体の第３の結晶層を成長させる工程とを備える化合物半
導体結晶の成長方法。1. A method for forming a crystal layer of a compound semiconductor on a silicon substrate, the method comprising: making the surface of the silicon substrate porous; and adding a first layer to the porous surface. growing a first crystal layer of the compound semiconductor at a temperature of
of the compound semiconductor at a second temperature higher than the temperature of
a step of growing a crystal layer on the second crystal layer;
and growing a third crystal layer of the compound semiconductor at a third temperature higher than the second temperature.
極化成法により、前記シリコン基板表面を多孔質化する
工程を含む請求項１の化合物半導体結晶の成長方法。2. The method for growing a compound semiconductor crystal according to claim 1, wherein the step of making the silicon substrate porous includes the step of making the surface of the silicon substrate porous by an anodization method in a hydrofluoric acid solution.
０℃の範囲、前記第２の温度が約４００℃〜約７００℃
の範囲、前記第３の温度が約５００℃〜約９００℃の範
囲より設定される請求項１の化合物半導体結晶の成長方
法。3. The first temperature is about 200°C to about 50°C.
in the range of 0°C, and the second temperature is about 400°C to about 700°C
2. The method for growing a compound semiconductor crystal according to claim 1, wherein the third temperature is set in a range of about 500°C to about 900°C.
合物半導体およびＩＩ−ＶＩ族化合物半導体の少なくと
もいずれかである請求項１の化合物半導体結晶の成長方
法。4. The method for growing a compound semiconductor crystal according to claim 1, wherein the compound semiconductor is at least one of a III-V group compound semiconductor and a II-VI group compound semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8531391A JPH04318922A (en) | 1991-04-17 | 1991-04-17 | Growth method for compound semiconductor crystal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8531391A JPH04318922A (en) | 1991-04-17 | 1991-04-17 | Growth method for compound semiconductor crystal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04318922A true JPH04318922A (en) | 1992-11-10 |
Family
ID=13855121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8531391A Withdrawn JPH04318922A (en) | 1991-04-17 | 1991-04-17 | Growth method for compound semiconductor crystal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04318922A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5712187A (en) * | 1995-11-09 | 1998-01-27 | Midwest Research Institute | Variable temperature semiconductor film deposition |
| JP2010212705A (en) * | 2002-05-07 | 2010-09-24 | Univ Claude Bernard Lyon 1 | Process for varying characteristic of thin film layer, and substrate for applying same process thereto |
-
1991
- 1991-04-17 JP JP8531391A patent/JPH04318922A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5712187A (en) * | 1995-11-09 | 1998-01-27 | Midwest Research Institute | Variable temperature semiconductor film deposition |
| JP2010212705A (en) * | 2002-05-07 | 2010-09-24 | Univ Claude Bernard Lyon 1 | Process for varying characteristic of thin film layer, and substrate for applying same process thereto |
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