JP2003218031A - Method of manufacturing semiconductor wafer - Google Patents
Method of manufacturing semiconductor waferInfo
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- JP2003218031A JP2003218031A JP2002017875A JP2002017875A JP2003218031A JP 2003218031 A JP2003218031 A JP 2003218031A JP 2002017875 A JP2002017875 A JP 2002017875A JP 2002017875 A JP2002017875 A JP 2002017875A JP 2003218031 A JP2003218031 A JP 2003218031A
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、Ｓｉ基板とＳｉＣ
またはＧａＮ膜を有する半導体ウェーハの製造方法に関
するものである。TECHNICAL FIELD The present invention relates to a Si substrate and a SiC.
Alternatively, the present invention relates to a method for manufacturing a semiconductor wafer having a GaN film.
【０００２】[0002]
【従来の技術】Ｓｉ基板上へのＳｉＣ膜の作成法として
は、各種ＣＶＤ法、スパッタリング法、各種ＭＢＥ法等
が公知である。2. Description of the Related Art Various CVD methods, sputtering methods, various MBE methods and the like are known as methods for forming an SiC film on a Si substrate.
【０００３】従来のＳｉＣ膜の形成法は、すべて６００
〜１２００℃以上にＳｉ基板を加熱することを必要とす
る。これはＳｉ−Ｃ間の結合が共有結合であるため、化
学結合形成エネルギーと、エピタキシャル結晶成長のた
めの拡散エネルギーの両方が、大きなものとなるためで
ある。The conventional method for forming a SiC film is 600
It is necessary to heat the Si substrate to ˜1200 ° C. or higher. This is because the bond between Si and C is a covalent bond, and therefore both the chemical bond formation energy and the diffusion energy for epitaxial crystal growth become large.
【０００４】しかし、ＳｉＣとＳｉの格子定数には約２
０％の違い（格子ミスマッチ）があり、かつその線熱膨
脹係数にも約８％の違いがある。そのため、高温でのＳ
ｉＣの薄膜形成後の冷却過程において、熱ひずみが生
じ、素子特性の劣化、反りの発生、機械的破損などを招
く。However, the lattice constant of SiC and Si is about 2
There is a 0% difference (lattice mismatch), and the linear thermal expansion coefficient also has a difference of about 8%. Therefore, S at high temperature
In the cooling process after forming the iC thin film, thermal strain occurs, which causes deterioration of element characteristics, warpage, mechanical damage, and the like.
【０００５】このような反りを防止する方法として、従
来は、反りの発生方向と逆向きに反った形状のＳｉ基板
を使用したり、あるいは、基板の表裏面の両方に成長さ
せたりして、製造時に反りの相殺を図っていた。As a method of preventing such warpage, conventionally, a Si substrate having a shape warped in the direction opposite to the direction of the warpage is used, or the Si substrate is grown on both the front and back surfaces of the substrate. It was trying to offset the warpage during manufacturing.
【０００６】[0006]
【発明が解決しようとする課題】前述のようにＳｉ基板
を特別な形状にする場合は、製造コストが大幅にアップ
する。If the Si substrate is made into a special shape as described above, the manufacturing cost will be greatly increased.
【０００７】また、Ｓｉ基板の表裏両面での成長方法
は、通常の設備では実施できない。Further, the growth method on both the front and back surfaces of the Si substrate cannot be carried out by ordinary equipment.
【０００８】本発明の目的は、反りの防止を容易に達成
できる、Ｓｉ基板とＳｉＣまたはＧａＮ膜を有する半導
体ウェーハの製造方法を提供することである。An object of the present invention is to provide a method for manufacturing a semiconductor wafer having a Si substrate and a SiC or GaN film, which can easily prevent warpage.
【０００９】[0009]
【課題を解決するための手段】本発明の解決手段を例示
すると、次のとおりである。The solution means of the present invention is exemplified as follows.
【００１０】（１）Ｓｉ基板の表面にＳｉＣまたはＧａ
Ｎ膜がエピタキシャル成長により形成され、さらに、そ
のＳｉＣまたはＧａＮ膜の表面にＳｉＯ2膜が形成され
ることを特徴とする半導体ウェーハの製造方法。(1) SiC or Ga on the surface of the Si substrate
A method for manufacturing a semiconductor wafer, wherein an N film is formed by epitaxial growth, and a SiO 2 film is further formed on the surface of the SiC or GaN film.
【００１１】（２）Ｓｉ基板にバッファー膜を介してＳ
ｉＣまたはＧａＮ膜が形成されることを特徴とする前述
の半導体ウェーハの製造方法。(2) S on the Si substrate via a buffer film
The method for manufacturing a semiconductor wafer as described above, wherein an iC or GaN film is formed.
【００１２】（３）ＳｉＯ2膜の膜厚がＳｉＣ膜の膜厚
の２〜４倍であることを特徴とする前述の半導体ウェー
ハの製造方法。(3) The method for manufacturing a semiconductor wafer as described above, wherein the thickness of the SiO 2 film is 2 to 4 times the thickness of the SiC film.
【００１３】（４）Ｓｉ基板の表面にＳｉＣまたはＧａ
Ｎ膜がエピタキシャル成長により形成され、かつ、Ｓｉ
基板の裏面にＳｉ3Ｎ4膜が形成されることを特徴とする
半導体ウェーハの製造方法。(4) SiC or Ga on the surface of the Si substrate
N film is formed by epitaxial growth and Si
A method for manufacturing a semiconductor wafer, wherein a Si 3 N 4 film is formed on the back surface of the substrate.
【００１４】（５）Ｓｉ基板にバッファー膜を介してＳ
ｉＣまたはＧａＮ膜が形成されることを特徴とする前述
の半導体ウェーハの製造方法。(5) S on the Si substrate via a buffer film
The method for manufacturing a semiconductor wafer as described above, wherein an iC or GaN film is formed.
【００１５】（６）ＳｉＣ膜の膜厚がＳｉ3Ｎ4の膜厚と
ほぼ同じであることを特徴とする前述の半導体ウェーハ
の製造方法。(6) The method for manufacturing a semiconductor wafer as described above, wherein the film thickness of the SiC film is substantially the same as the film thickness of Si 3 N 4 .
【００１６】[0016]
【発明の実施の形態】この発明は、Ｓｉに比べて半導体
機能として優れた性能を持つＳｉＣまたはＧａＮ膜を有
する半導体ウェーハの製造方法を提供するものである。BEST MODE FOR CARRYING OUT THE INVENTION The present invention provides a method for manufacturing a semiconductor wafer having a SiC or GaN film having a semiconductor function superior to that of Si.
【００１７】まず、ＳｉＣ膜について述べると、ＳｉＣ
半導体とくに３Ｃ−ＳｉＣ半導体は、主にＳｉ（シリコ
ン）基板上に３Ｃ−ＳｉＣ膜をエピタキシャル成長させ
ることにより製造される。First, the SiC film will be described.
Semiconductors, especially 3C-SiC semiconductors, are manufactured mainly by epitaxially growing a 3C-SiC film on a Si (silicon) substrate.
【００１８】図１に示すように、Ｓｉ基板２の表面に３
Ｃ−ＳｉＣ膜１を成長温度（８００〜１２００℃）でエ
ピタキシャル成長させ、所定の膜厚にしてから、室温に
冷却すると、ＳｉとＳｉＣの熱膨張係数の違いによる反
りが生じる。基板となるＳｉと成長させるＳｉＣとの間
には８％程度の熱膨張係数の違いがあり、そのため、成
長後にエピタキシャル膜には圧縮応力がかかり、３Ｃ−
ＳｉＣ膜１とＳｉ基板２が反ってしまう。この反りはデ
バイス作成時の課題となることが予測される。また、膜
１の剥離や割れを発生する原因ともなる。したがって、
その反り量を抑制することが重要となる。As shown in FIG. 1, 3 is formed on the surface of the Si substrate 2.
When the C—SiC film 1 is epitaxially grown at a growth temperature (800 to 1200 ° C.) to a predetermined film thickness and then cooled to room temperature, warpage occurs due to the difference in thermal expansion coefficient between Si and SiC. There is a difference in thermal expansion coefficient of about 8% between Si that serves as a substrate and SiC that is grown. Therefore, after the growth, compressive stress is applied to the epitaxial film and 3C-
The SiC film 1 and the Si substrate 2 are warped. It is predicted that this warpage will be a problem when creating a device. It also causes the peeling and cracking of the film 1. Therefore,
It is important to suppress the warp amount.
【００１９】図２に示すように、Ｓｉ基板２の表面にＳ
ｉＯ2膜３を成長温度（６００〜９００℃）で成長させ
て所定の膜厚を得てから、室温に冷却すると、ＳｉとＳ
ｉＯ 2の熱膨張係数の違いによる反りが図１とは逆の方
向に生じる。As shown in FIG. 2, S is formed on the surface of the Si substrate 2.
iO2The film 3 is grown at the growth temperature (600 to 900 ° C.)
After obtaining the desired film thickness by cooling to room temperature, Si and S
iO 2The warpage due to the difference in the coefficient of thermal expansion is opposite to that in Fig. 1.
Occurs in the opposite direction.
【００２０】本発明は、図１と図２の反りを効果的に活
用して互いに相殺し、３Ｃ−ＳｉＣ膜１の反りを防止す
るものである。Ｓｉ基板５の表面に３Ｃ−ＳｉＣ膜６を
エピタキシャル成長させ、ついで、温度を大幅に下げな
いまま、ＳｉＯ2膜７を成長させることにより、反り量
をコントロールして、３Ｃ−ＳｉＣ／Ｓｉ基板を得る。The present invention effectively utilizes the warpages of FIGS. 1 and 2 to cancel each other out and prevent the warpage of the 3C-SiC film 1. A 3C-SiC film 6 is epitaxially grown on the surface of the Si substrate 5, and then a SiO 2 film 7 is grown without significantly lowering the temperature to control the amount of warpage and obtain a 3C-SiC / Si substrate. .
【００２１】たとえば、図３に示すように、Ｓｉ基板２
の表面に３Ｃ−ＳｉＣ膜１を所定の成長温度（８００℃
〜１２００℃）でエピタキシャル成長させて所定の膜厚
（５〜１０μｍ）にし、そのまま温度を大幅に下げず
に、その３Ｃ−ＳｉＣ膜６の表面に、ＳｉやＳｉＣと比
べて熱膨張係数の低いＳｉＯ2膜７を成長させる。これ
により、半導体ウェーハを室温に冷却したとき、図１の
反りと図２の反りが互いに相殺して、全体の反りが低減
される。For example, as shown in FIG.
The 3C-SiC film 1 is formed on the surface of the substrate at a predetermined growth temperature (800 °
˜1200 ° C.) to obtain a predetermined film thickness (5 to 10 μm) by epitaxial growth, and the temperature of the 3C—SiC film 6 is not lowered significantly. 2 The film 7 is grown. As a result, when the semiconductor wafer is cooled to room temperature, the warpage in FIG. 1 and the warpage in FIG. 2 cancel each other out, and the overall warpage is reduced.
【００２２】アモルファスであるＳｉＯ2膜７の熱膨張
係数はＳｉやＳｉＣのそれと比較して５分の１程度にす
ぎず、極めて低い値を示す。それゆえ、好ましくは、Ｓ
ｉＯ 2膜７の膜厚はエピタキシャル成長したＳｉＣ膜６
の２から４倍程度とする。Amorphous SiO2Thermal expansion of membrane 7
Coefficient should be about one fifth of that of Si and SiC
As expected, it shows an extremely low value. Therefore, preferably S
iO 2The film thickness of the film 7 is the SiC film 6 epitaxially grown.
2 to 4 times.
【００２３】ＳｉＯ2は電気的に絶縁体であるので、デ
バイスにするときには、ＳｉＯ2膜を局所的にエッチン
グして電極物質を成膜すればよい。Since SiO 2 is an electrically insulating material, when a device is formed, the SiO 2 film may be locally etched to form an electrode material.
【００２４】上記と同様な効果を得るために、図４に示
すように、Ｓｉ基板５の裏面にＳｉＣ膜７と同等な熱膨
張係数を有するＳｉ3Ｎ4膜８をＳｉＣ膜７の膜厚と同程
度に成膜してもよい。In order to obtain the same effect as described above, as shown in FIG. 4, a Si 3 N 4 film 8 having a thermal expansion coefficient equivalent to that of the SiC film 7 is formed on the back surface of the Si substrate 5. The film may be formed to the same extent as.
【００２５】なお、エピタキシャル成長においては、Ｓ
ｉ基板５の結晶性を成長膜が受け継ぐ。それゆえ、良質
な結晶を得る上でＳｉ基板５の荒れは避けた方がよい。
そのため、Ｓｉ基板５の荒れをもたらさないように、適
当な物質によるバッファー膜を設けることが好ましい。In the epitaxial growth, S
The growth film inherits the crystallinity of the i substrate 5. Therefore, it is better to avoid the roughening of the Si substrate 5 in order to obtain a good quality crystal.
Therefore, it is preferable to provide a buffer film made of an appropriate substance so as not to cause the roughness of the Si substrate 5.
【００２６】たとえば、Ｓｉ基板５となるＳｉウェーハ
上に３Ｃ−ＳｉＣ単結晶をエピタキシャル成長させる際
に、閃亜鉛鉱型単結晶のＢＰ（リン化ホウ素）をバッフ
ァー膜として用いることにより、結晶欠陥を減少させ
る。閃亜鉛鉱型結晶であるＢＰ（リン化ホウ素）の格子
定数は、４．５３８オングストロームであり、３Ｃ−Ｓ
ｉＣの４．３５８オングストロームとほぼ同等であり、
格子不整合によるミスフィット転位を抑制できる。ま
た、熱膨脹率もほぼ同等である。また、ＢＰは、Ｓｉと
格子定数にして１６．４％の違いがあるものの、ＢＰは
Ｓｉ上にヘテロエピタキシャル成長できるものである。
まず、Ｓｉ基板上にＢＰをエピタキシャル成長させ、続
いて、３Ｃ−ＳｉＣ単結晶を成長させることにより、ミ
スフィット転位を抑制した結晶を得ることができる。For example, when epitaxially growing a 3C-SiC single crystal on a Si wafer which becomes the Si substrate 5, BP (boron phosphide) of a zinc blende type single crystal is used as a buffer film to reduce crystal defects. Let The lattice constant of BP (boron phosphide), which is a zinc blende type crystal, is 4.538 angstroms and is 3C-S.
It is almost equivalent to iC's 4.358 angstroms,
Misfit dislocations due to lattice mismatch can be suppressed. Also, the coefficient of thermal expansion is almost the same. Further, although BP has a lattice constant difference of 16.4% from Si, BP can be heteroepitaxially grown on Si.
First, a crystal in which misfit dislocations are suppressed can be obtained by epitaxially growing BP on a Si substrate and subsequently growing a 3C-SiC single crystal.
【００２７】以下に、好適な実施例１を説明する。A preferred first embodiment will be described below.
【００２８】＜実施例１＞
（１）Ｓｉ基板のＳｉ（１００）もしくは（１１１）を
水素雰囲気中で１０００℃以上に加熱することにより、
Ｓｉ基板の自然酸化膜を除去する。Example 1 (1) By heating Si (100) or (111) of a Si substrate to 1000 ° C. or higher in a hydrogen atmosphere,
The native oxide film on the Si substrate is removed.
【００２９】（２）キャリアガスを水素として、Ｂ原料
のＢＣｌ3とＰ原料のＰＣｌ3を反応管に流し、低温成長
を約２００〜５００℃で３０分程度行う。[0029] As hydrogen (2) carrier gas, flowing BCl 3 and PCl 3 in P raw material B material in the reaction tube, for about 30 minutes at about 200 to 500 ° C. The low temperature growth.
【００３０】（３）低温成長終了時にＢＰの原料供給を
止め、ＢＰの結晶成長温度である９００〜１２００℃ま
で昇温する。(3) At the end of the low temperature growth, the supply of the BP raw material is stopped, and the temperature is raised to 900 to 1200 ° C. which is the BP crystal growth temperature.
【００３１】（４）９００〜１２００℃の成長温度にな
ったら、ＢＰの原料供給を開始し、そのまま３０分以上
保持し、ＢＰ膜を１〜５μｍ程度成膜する。(4) When the growth temperature reaches 900 to 1200 ° C., the supply of the BP raw material is started and kept for 30 minutes or longer to form a BP film of about 1 to 5 μm.
【００３２】（５）所定の結晶成長を終えたのち、ＢＰ
の原料供給を停止し、その温度のまま３０分程度保持す
る。(5) After completing the predetermined crystal growth, BP
The raw material supply is stopped and the temperature is maintained for about 30 minutes.
【００３３】（６）ついで、ＳｉＣの低温成長温度であ
る２００〜５００℃まで温度を低下させ、原料であるメ
チルシランの供給を開始し、１０分程度保持する。(6) Next, the temperature is lowered to a low temperature growth temperature of SiC of 200 to 500 ° C., the supply of methylsilane as a raw material is started, and the temperature is maintained for about 10 minutes.
【００３４】（７）再び３Ｃ−ＳｉＣの結晶成長温度で
ある８００〜１２００℃程度間で昇温し、そのまま３０
分以上保持し、ＳｉＣ膜を１０〜３０μｍ成膜する。(7) The temperature is raised again between the crystal growth temperature of 3C-SiC of about 800 to 1200 ° C.
The SiC film is formed to a thickness of 10 to 30 μm by holding for more than a minute.
【００３５】（８）所定の３Ｃ−ＳｉＣ結晶成長が終了
した時点で、メチルシラン原料の供給を停止する。(8) The supply of the methylsilane raw material is stopped when the predetermined 3C-SiC crystal growth is completed.
【００３６】（９）しかるのち、６００〜９００℃にし
て、ＴＥＯＳと称されているＳｉ（ＯＣ2Ｈ5）4などの
Ｓｉアルコキシドを原料ガスとして供給し、２０分程度
保持し、ＳｉＯ2膜をＳｉＣ膜の膜厚の２〜４倍程度成
長させる。(9) Thereafter, the temperature is set to 600 to 900 ° C., a Si alkoxide such as Si (OC 2 H 5 ) 4 called TEOS is supplied as a raw material gas, and the material is held for about 20 minutes to obtain a SiO 2 film. Is grown to about 2 to 4 times the thickness of the SiC film.
【００３７】上記工程（１）〜（９）により製造した３
Ｃ−ＳｉＣ半導体ウェーハと比較するために、ＳｉＯ2
膜を成長させない、すなわち上記（９）の操作を除いた
条件で、３Ｃ−ＳｉＣ／Ｓｉ基板を作製した。これらを
比較したところ、ＳｉＯ2膜とＢＰのバッファー膜を設
けて作成した３Ｃ−ＳｉＣ半導体の結晶素子は、反りが
なく。、かつ、格子欠陥違いによるミスフィット転位が
良好に抑制されており、高品質な結晶になっていたが、
ＳｉＯ2膜なしで製造したものは、反りが大きく、良質
な単結晶ＳｉＣを製造することはできなかった。3 produced by the above steps (1) to (9)
For comparison with a C-SiC semiconductor wafer, SiO 2
A 3C-SiC / Si substrate was produced under the condition that the film was not grown, that is, the operation (9) was excluded. Comparing these, the 3C-SiC semiconductor crystal element formed by providing the SiO 2 film and the BP buffer film has no warp. And, the misfit dislocations due to the difference in the lattice defects were well suppressed, resulting in a high quality crystal.
The product manufactured without the SiO 2 film had a large warp, and it was not possible to manufacture a high-quality single crystal SiC.
【００３８】＜実施例２＞
（１）Ｓｉ基板のＳｉ（１００）もしくは（１１１）を
水素雰囲気中で１０００℃以上に加熱することにより、
Ｓｉ基板の自然酸化膜を除去する。Example 2 (1) By heating Si (100) or (111) of a Si substrate to 1000 ° C. or higher in a hydrogen atmosphere,
The native oxide film on the Si substrate is removed.
【００３９】（２）キャリアガスを水素として、Ｂ原料
のＢＣｌ3とＰ原料のＰＣｌ3を反応管に流し、低温成長
を約２００〜５００℃で３０分程度行う。[0039] As hydrogen (2) carrier gas, flowing BCl 3 and PCl 3 in P raw material B material in the reaction tube, for about 30 minutes at about 200 to 500 ° C. The low temperature growth.
【００４０】（３）低温成長終了時にＢＰの原料供給を
止め、ＢＰの結晶成長温度である９００〜１２００℃ま
で昇温する。(3) When the low temperature growth is completed, the supply of the BP raw material is stopped, and the temperature is raised to 900 to 1200 ° C. which is the BP crystal growth temperature.
【００４１】（４）９００〜１２００℃の成長温度にな
ったら、ＢＰの原料供給を開始し、そのまま３０分以上
保持し、ＢＰ膜を１〜５μｍ程度成膜する。(4) When the growth temperature reaches 900 to 1200 ° C., the supply of the BP raw material is started and maintained for 30 minutes or longer to form a BP film of about 1 to 5 μm.
【００４２】（５）所定の結晶成長を終えたのち、ＢＰ
の原料供給を停止し、その温度のまま３０分程度保持す
る。(5) After completing the predetermined crystal growth, BP
The raw material supply is stopped and the temperature is maintained for about 30 minutes.
【００４３】（６）ついで、ＧａＮの低温成長温度であ
る４００℃〜５００℃まで温度を低下させ、原料である
ＴＭＧＴＭＧ｛トリメチルガリウム（ＣＨ3）3Ｇａ｝、
ＭＭＨ（モノメチルヒドラジンＣＨ3ＮＨＮＨ2）とキャ
リアガスＨ2に加え、Ｎ2の供給を開始し、３０分程度保
持する。(6) Next, the temperature is lowered to 400 ° C. to 500 ° C. which is the low temperature growth temperature of GaN, and the raw material TMGTMG {trimethylgallium (CH 3 ) 3 Ga},
In addition to MMH (monomethylhydrazine CH 3 NHNH 2 ) and carrier gas H 2 , supply of N 2 is started and maintained for about 30 minutes.
【００４４】（７）再びＧａＮの結晶成長温度である７
５０℃〜９００℃程度で昇温し、そのまま３０分以上保
持し、ＧａＮ膜を５〜１０μｍ成膜する。(7) The GaN crystal growth temperature is 7 again.
The temperature is raised at about 50 ° C. to 900 ° C. and kept for 30 minutes or longer to form a GaN film of 5 to 10 μm.
【００４５】（８）所定のＧａＮ結晶成長が終了した時
点で、原料の供給を停止する。(8) The supply of the raw material is stopped when the predetermined GaN crystal growth is completed.
【００４６】（９）しかるのち、６００〜９００℃にし
て、ＴＥＯＳと称されているＳｉ（ＯＣ2Ｈ5）4などの
Ｓｉアルコキシドを原料ガスとして供給し、２０分程度
保持し、ＳｉＯ2膜をＧａＮ膜の膜厚の２〜４倍程度成
長させる。(9) After that, the temperature is set to 600 to 900 ° C., a Si alkoxide such as Si (OC 2 H 5 ) 4 called TEOS is supplied as a source gas, and the material is held for about 20 minutes to obtain a SiO 2 film. Are grown to about 2 to 4 times the film thickness of the GaN film.
【００４７】本発明は、前述の実施例に限定されるもの
ではない。たとえば、原料ガスとしては、前述のガス以
外に種々のものが利用できる。The invention is not limited to the embodiments described above. For example, as the source gas, various gases other than the above-mentioned gases can be used.
【００４８】[0048]
【発明の効果】本発明によれば、ＳｉＯ2膜やＳｉ3Ｎ4
膜をＳｉＣまたはＧａＮ膜に加えて成膜させることによ
って、半導体ウェーハ全体の反り量をコントロールする
ことができる。According to the present invention, a SiO 2 film or a Si 3 N 4 film is used.
By forming the film in addition to the SiC or GaN film, the amount of warpage of the entire semiconductor wafer can be controlled.
【図１】図１の上側は、Ｓｉ基板上にＳｉＣを成長温度
でエピタキシャル成長させた場合の様子を示す模式図。
図１の下側は、それを室温まで冷却したときの様子を示
す模式図。FIG. 1 is a schematic diagram showing the upper side of FIG. 1 when SiC is epitaxially grown on a Si substrate at a growth temperature.
The lower side of FIG. 1 is a schematic diagram showing a state when it is cooled to room temperature.
【図２】図２の上側は、Ｓｉ基板にＳｉＯ2を成長温度
で成長させた場合の様子を示す模式図図２の下側は、そ
れを室温まで冷却したときの様子を示す模式図。FIG. 2 is a schematic diagram showing the state when SiO 2 is grown on a Si substrate at a growth temperature, and the lower side is a schematic diagram showing the state when it is cooled to room temperature.
【図３】本発明の１つの実施例を示す模式図。FIG. 3 is a schematic view showing one embodiment of the present invention.
【図４】本発明の他の実施例を示す模式図。FIG. 4 is a schematic view showing another embodiment of the present invention.
２ Ｓｉ基板 ５ Ｓｉ基板 ６ ＳｉＣ膜 ７ ＳｉＯ2膜 ８ Ｓｉ3Ｎ4膜2 Si substrate 5 Si substrate 6 SiC film 7 SiO 2 film 8 Si 3 N 4 film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中西 秀夫 神奈川県秦野市曽屋30番地 東芝セラミッ クス株式会社開発研究所内 Ｆターム(参考） 4G077 AA03 BE08 BE15 DB01 EE06 EF01 FJ06 TC13 TC16 TC17 5F045 AB06 AB14 AB31 AB32 AB33 AC08 AC15 AD06 AD07 AD08 AD09 AD13 AD14 AD15 AD16 AF03 BB11 DA53 DC65 5F052 DA04 GC03 KA01 KA05 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Hideo Nakanishi 30 Soya, Hadano City, Kanagawa Prefecture Kusu Co., Ltd. Development Laboratory F-term (reference) 4G077 AA03 BE08 BE15 DB01 EE06 EF01 FJ06 TC13 TC16 TC17 5F045 AB06 AB14 AB31 AB32 AB33 AC08 AC15 AD06 AD07 AD08 AD09 AD13 AD14 AD15 AD16 AF03 BB11 DA53 DC65 5F052 DA04 GC03 KA01 KA05
Claims (6)
がエピタキシャル成長により形成され、さらに、そのＳ
ｉＣまたはＧａＮ膜の表面にＳｉＯ2膜が形成されるこ
とを特徴とする半導体ウェーハの製造方法。1. A SiC or GaN film is formed by epitaxial growth on the surface of a Si substrate, and the S or S
A method for manufacturing a semiconductor wafer, wherein a SiO 2 film is formed on the surface of the iC or GaN film.
またはＧａＮ膜が形成されることを特徴とする請求項１
に記載の半導体ウェーハの製造方法。2. SiC on a Si substrate via a buffer film
Alternatively, a GaN film is formed.
A method of manufacturing a semiconductor wafer according to item 1.
〜４倍であることを特徴とする請求項１〜２のいずれか
１項に記載の半導体ウェーハの製造方法。3. The thickness of the SiO 2 film is 2 times that of the SiC film.
It is 4 times, The manufacturing method of the semiconductor wafer as described in any one of Claims 1-2.
がエピタキシャル成長により形成され、かつ、Ｓｉ基板
の裏面にＳｉ3Ｎ4膜が形成されることを特徴とする半導
体ウェーハの製造方法。4. A method of manufacturing a semiconductor wafer, wherein a SiC or GaN film is formed on a front surface of a Si substrate by epitaxial growth, and a Si 3 N 4 film is formed on a back surface of the Si substrate.
またはＧａＮ膜が形成されることを特徴とする請求項４
に記載の半導体ウェーハの製造方法。5. SiC on a Si substrate via a buffer film
Alternatively, a GaN film is formed.
A method of manufacturing a semiconductor wafer according to item 1.
ぼ同じであることを特徴とする請求項４〜５のいずれか
１項に記載の半導体ウェーハの製造方法。6. The method of manufacturing a semiconductor wafer according to claim 4, wherein the film thickness of the SiC film is substantially the same as the film thickness of the Si 3 N 4 film.
Priority Applications (5)
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|---|---|---|---|
| JP2002017875A JP2003218031A (en) | 2002-01-28 | 2002-01-28 | Method of manufacturing semiconductor wafer |
| US10/432,597 US6936490B2 (en) | 2001-09-06 | 2002-09-05 | Semiconductor wafer and its manufacturing method |
| PCT/JP2002/009035 WO2003023095A1 (en) | 2001-09-06 | 2002-09-05 | Semiconductor wafer and its manufacturing method |
| EP02765418A EP1424409A4 (en) | 2001-09-06 | 2002-09-05 | Semiconductor wafer and its manufacturing method |
| TW091120310A TWI222104B (en) | 2001-09-06 | 2002-09-05 | Semiconductor wafer and method of fabricating the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002017875A JP2003218031A (en) | 2002-01-28 | 2002-01-28 | Method of manufacturing semiconductor wafer |
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ID=27653418
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