JPH04257233A - Charge transfer device - Google Patents
Charge transfer deviceInfo
- Publication number
- JPH04257233A JPH04257233A JP3018580A JP1858091A JPH04257233A JP H04257233 A JPH04257233 A JP H04257233A JP 3018580 A JP3018580 A JP 3018580A JP 1858091 A JP1858091 A JP 1858091A JP H04257233 A JPH04257233 A JP H04257233A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor region
- semiconductor
- region
- charge transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 10
- 238000001444 catalytic combustion detection Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、ＣＣＤ（電荷結合素子
）等に用いられる電荷転送装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device used in a CCD (charge coupled device) or the like.
【０００２】0002
【従来の技術】民生用ムービーを始め、各種ビデオカメ
ラ用としてに普及している固体撮像素子の大半は、プレ
ーナ・チャネル形ＣＣＤと呼ばれる電荷転送素子（文献
：Ｃ．Ｈ．セクイン、 Ｍ．Ｆ．トンプセット（Ｃ．
Ｈ． Ｓｅｑｕｉｎ ＆ Ｍ． Ｆ． Ｔｏｍｐｓｅｔ
ｔ）， ”チャーシ゛・トランスファー・ディバイス（
Ｃｈａｒｇｅ Ｔｒａｎｓｆｅｒ Ｄｅｖｉｃｅ）”，
アカデミック・プレス（Ａｃａｄｅｍｉｃ Ｐｒｅｓｓ
）１９７５）である。2. Description of the Related Art Most of the solid-state image sensing devices that are popular for use in consumer movies and various video cameras are charge transfer devices called planar channel CCDs (Reference: C.H. Sequin, M.F. .Thompset (C.
H. Sequin & M. F. Tompset
t), “Charge Transfer Device (
Charge Transfer Device)”,
Academic Press
) 1975).
【０００３】このプレーナ・チャネル形ＣＣＤの中で最
も原理的な表面チャネルＣＣＤの構造は、図１２、図１
３に示すようにｐ型シリコン基板３０１の上部に形成さ
れた厚さＴｏｘのゲート酸化膜（通常は厚さ約５００〜
１０００ÅのＳｉＯ２）３０２の上に形成されたポリシ
リコンのゲート電極３０３、３０４、３０５などで構成
される。The structure of the surface channel CCD, which is the most basic among these planar channel CCDs, is shown in FIGS. 12 and 1.
3, a gate oxide film with a thickness of Tox is formed on the top of a p-type silicon substrate 301 (usually about 500 nm thick).
It consists of polysilicon gate electrodes 303, 304, 305, etc. formed on 1000 Å SiO2) 302.
【０００４】信号電荷の保持動作（または、蓄積動作と
もいう）は、図１２のようにゲート電極３０４に正電圧
を印加して発生した空乏領域 ３０６に電荷を蓄えるこ
とで実現する。[0004] The signal charge holding operation (also referred to as storage operation) is achieved by applying a positive voltage to the gate electrode 304 and storing the charge in a depletion region 306, as shown in FIG.
【０００５】また、信号電荷の転送動作は、図１３のよ
うにゲート電極３０５にゲート電極３０４よりも大きな
電圧を印加することで、空乏領域３０６内の信号電荷は
より電位の深い空乏領域３０７へ移動（すなわち転送）
する。[0005] Furthermore, the signal charge transfer operation is carried out by applying a voltage larger to the gate electrode 305 than to the gate electrode 304 as shown in FIG. Move (i.e. transfer)
do.
【０００６】[0006]
【発明が解決しようとする課題】ところが、シリコン基
板内に電荷の転送チャネルを形成する従来のプレーナ・
チャネル形ＣＣＤを使用した場合、素子の高密度化や小
型化の進めると、不要な光入射により生成された偽信号
電荷が転送チャネル中に混入することを避けるための遮
光領域の確保が不十分になり、偽信号の量を表わすスミ
アが増大する。また、ＣＣＤの転送チャネルを用いて転
送できる最大電荷量は転送チャネルの幅に依存するので
、ＤＲＡＭのような微細化技術をそのままＣＣＤには有
効に適用できず、ＣＣＤの微細化が進まない。[Problems to be Solved by the Invention] However, conventional planar technology that forms charge transfer channels within a silicon substrate
When channel-type CCDs are used, as devices become more densely packed and miniaturized, there is insufficient light-shielding area to prevent false signal charges generated by unnecessary light from entering the transfer channel. , and the smear, which represents the amount of false signals, increases. Further, since the maximum amount of charge that can be transferred using a transfer channel of a CCD depends on the width of the transfer channel, miniaturization technology such as DRAM cannot be effectively applied as is to CCDs, and the miniaturization of CCDs does not progress.
【０００７】これらの結果、画素を二次元配列したＣＣ
Ｄ型撮像素子では、画素の主要部である受光領域と電荷
転送領域のトレード・オフとなり、結局撮像素子の基本
特性である感度とダイナミック・レンジのトレード・オ
フという課題が生じている。As a result, CC with two-dimensional array of pixels
In the D-type image sensor, there is a trade-off between the light receiving area, which is the main part of the pixel, and the charge transfer area, resulting in the problem of a trade-off between sensitivity and dynamic range, which are the basic characteristics of the image sensor.
【０００８】本発明はこの様な従来ＣＣＤ型撮像素子の
課題に注目し、スミアが少なく、しかもＤＲＡＭ並の微
細化がそのまま適用できる電荷転送装置の提供を目的と
する。The present invention focuses on the problems of the conventional CCD type image pickup device, and aims to provide a charge transfer device that causes less smear and can be applied as is to miniaturization comparable to that of a DRAM.
【０００９】[0009]
【課題を解決するための手段】本発明は、半導体基板表
面の絶縁膜と、前記絶縁膜に電荷転送領域として埋め込
まれた複数の半導体領域と、前記半導体領域の電位を制
御する為に前記半導体領域に対応して設けられた制御電
極と、前記各半導体領域を相互に隔てるトンネル絶縁膜
とを備えた電荷転送装置である。Means for Solving the Problems The present invention includes an insulating film on the surface of a semiconductor substrate, a plurality of semiconductor regions embedded in the insulating film as charge transfer regions, and a semiconductor device for controlling the potential of the semiconductor region. The charge transfer device includes control electrodes provided corresponding to the regions, and a tunnel insulating film that separates the semiconductor regions from each other.
【００１０】また、本発明は、半導体基板表面に形成さ
れた高不純物領域と、前記半導体基板表面の第１の絶縁
膜に開孔された窓を通じて前記高不純物領域と接続され
た第１の制御電極と、前記第１の制御電極と全体的な重
なりを持ちしかも第１のトンネル絶縁膜で隔てられた第
１の半導体領域と、前記第１の半導体領域と部分的な重
なりを持ちしかも第２のトンネル絶縁膜で隔てられた第
２の半導体領域と、前記第１の半導体領域と部分的な重
なりを持ち、しかも第２の絶縁膜で隔てられた第２の制
御電極とを備えた電荷転送装置である。The present invention also provides a highly impurity region formed on the surface of a semiconductor substrate, and a first control region connected to the high impurity region through a window opened in a first insulating film on the surface of the semiconductor substrate. an electrode, a first semiconductor region that completely overlaps the first control electrode and is separated by a first tunnel insulating film, and a second semiconductor region that partially overlaps the first semiconductor region and a second semiconductor region separated by a tunnel insulating film; and a second control electrode partially overlapping the first semiconductor region and separated by a second insulating film. It is a device.
【００１１】また、本発明は、半導体基板表面に形成さ
れた第１の高不純物領域と、前記第１の不純物領域と同
一導電形で複数個の第２の高不純物領域と、前記第１の
不純物領域と全体的な重なりを持ちしかも前記半導体基
板表面の第１のトンネル絶縁膜で隔てられた第１の半導
体領域と、前記第１の半導体領域と部分的な重なりを持
ちしかも第２のトンネル絶縁膜で隔てられた第２の半導
体領域と、前記第１の半導体領域と部分的な重なりを持
ちしかも第２の絶縁膜で隔てられた第２の制御電極とを
備えた電荷転送装置である。The present invention also provides a first highly impurity region formed on the surface of the semiconductor substrate, a plurality of second highly impurity regions of the same conductivity type as the first impurity region, and a plurality of second highly impurity regions formed on the surface of the semiconductor substrate. a first semiconductor region that completely overlaps with the impurity region and is separated by a first tunnel insulating film on the surface of the semiconductor substrate; and a second tunnel that partially overlaps with the first semiconductor region and is separated by a first tunnel insulating film on the surface of the semiconductor substrate. The charge transfer device includes a second semiconductor region separated by an insulating film, and a second control electrode that partially overlaps the first semiconductor region and is separated by the second insulating film. .
【００１２】0012
【作用】本発明は、絶縁膜中に閉じこめられた複数のシ
リコンなどの半導体領域の間をトンネル効果により電荷
を輸送する、（スタック・チャネル形）電荷転送素子を
用いているので、ＣＣＤの主要特性の最大転送電荷量に
悪影響を与えずにＤＲＡＭの微細化技術を適用してＣＣ
Ｄの微細化を実現し、チャネル幅という概念が不要にな
るためダイナミイクレンジも大きくすること可能であり
、半導体基板に由来する特性（特に２次元撮像素子で重
要なスミア特性）の劣化も招かないため、ＣＣＤを信号
線のような感覚で各種デバイスに用いることが可能にな
る。[Operation] The present invention uses a (stacked channel type) charge transfer element that transports charges between multiple semiconductor regions such as silicon confined in an insulating film by a tunnel effect, so it is a main feature of a CCD. CC by applying DRAM miniaturization technology without adversely affecting the maximum transfer charge amount of characteristics.
By realizing miniaturization of D and eliminating the need for the concept of channel width, it is possible to increase the dynamic range. This makes it possible to use CCDs in various devices as if they were signal lines.
【００１３】[0013]
【実施例】以下、本発明の実施例について図面を参照し
て説明する。Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.
【００１４】図１、図２は、本発明にかかる電荷転送装
置の第１の実施例の構造を示すものである。ｐ形のシリ
コン基板（以下、ｐ基板と呼ぶ）１０１の表面に電荷注
入源となるｎ＋領域１０２と第１の制御電極となる複数
個のｎ＋領域１０３ａ、１０３ｂ、１０３ｃなどを形成
し、ｐ基板１０１の表面に順次形成した第１のトンネル
絶縁膜１０４（代表的なトンネル絶縁膜としては１００
〜２００Åの薄いゲート酸化膜、あるいは２０Åの薄い
窒化膜が利用できる）と絶縁膜１０５の上に複数個の第
１の半導体（ポリシリコン又は単結晶シリコン）領域１
０７ａ、１０７ｂ、１０７ｃなどを形成する。このとき
同時に、ｎ＋領域１０５とは窓形状に露出した第１のト
ンネル絶縁膜１０４だけで隔てられた電荷入力部となる
第１の半導体領域１０６を形成する。さらに、第１の半
導体領域１０６、１０７とは部分的な重なりを持ち、し
かも第２のトンネル絶縁膜１１４で隔てられた複数個の
第２の半導体領域１０８ａ、１０８ｂ、１０８ｃ、１０
８ｄなどを形成し、続いて、絶縁膜１０９で隔てられた
複数個の第２の制御電極として１１０ａ、１１０ｂ、１
１０ｃ、１１０ｄを形成する。なお、第２の制御電極１
１０ａ、１１０ｂ、１１０ｃ、１１０ｄを形成するとき
に、電荷入力部の制御電極１１１も同時に形成される。
１１２ａ、１１２ｂ、１１２ｃなどは金属（アルミニウ
ムなど）配線部である。FIGS. 1 and 2 show the structure of a first embodiment of a charge transfer device according to the present invention. An n+ region 102 serving as a charge injection source and a plurality of n+ regions 103a, 103b, 103c serving as a first control electrode are formed on the surface of a p-type silicon substrate (hereinafter referred to as a p-substrate) 101, and the p-type silicon substrate A first tunnel insulating film 104 is sequentially formed on the surface of 101 (a typical tunnel insulating film is 100
A plurality of first semiconductor (polysilicon or single crystal silicon) regions 1 are formed on the insulating film 105 (a thin gate oxide film of ~200 Å or a thin nitride film of 20 Å can be used) and an insulating film 105.
07a, 107b, 107c, etc. are formed. At this time, at the same time, a first semiconductor region 106 that becomes a charge input portion and is separated from the n+ region 105 by only the first tunnel insulating film 104 exposed in a window shape is formed. Further, a plurality of second semiconductor regions 108a, 108b, 108c, 10 partially overlap with the first semiconductor regions 106, 107 and are separated by a second tunnel insulating film 114.
8d, etc., and then 110a, 110b, 1 as a plurality of second control electrodes separated by an insulating film 109.
10c and 110d are formed. Note that the second control electrode 1
When forming the electrodes 10a, 110b, 110c, and 110d, the control electrode 111 of the charge input section is also formed at the same time. 112a, 112b, 112c, etc. are metal (aluminum, etc.) wiring parts.
【００１５】尚、電荷入力部は、上述した様に、ｎ＋領
域１０２と第１のトンネル絶縁膜１０４と第１の半導体
領域１０６と入力部の制御電極１１１および第２のトン
ネル絶縁膜１１４で隔てられた第１の半導体領域１０８
ａからなるが、この電荷入力部の対称的構造を最終段に
接続すれば電荷出力部として利用することが可能になる
。As described above, the charge input section is separated by the n+ region 102, the first tunnel insulating film 104, the first semiconductor region 106, the control electrode 111 of the input section, and the second tunnel insulating film 114. first semiconductor region 108
If the symmetric structure of this charge input section is connected to the final stage, it can be used as a charge output section.
【００１６】次に、上記第１の実施例の基本的な動作原
理を図１（ｃ）、（ｄ）、（ｅ）、（ｆ）、（ｇ）（ｈ
）（ｉ）に示したエネルギー・バンド図を用いて説明す
る。Next, the basic operating principle of the first embodiment is shown in FIGS. 1(c), (d), (e), (f), (g) and
) (i) This will be explained using the energy band diagram shown in (i).
【００１７】図２のＹ−Ｙ’断面図に対応した熱平衡状
態のエネルギー・バンド図が図３である。左側からｎ＋
領域１０２（バンド・ギャップ・エネルギー：Ｅｇ＝１
．１ｅＶ）、トンネル絶縁膜１０４（Ｅｇ＝８ｅＶ）、
第１の半導体領域１０６（Ｅｇ＝１．１ｅＶ）、第２の
トンネル絶縁膜１１４と絶縁膜１００（Ｅｇ＝８ｅＶ）
、制御電極１１１（Ｅｇ＝１．１ｅＶ）に対応している
。FIG. 3 is an energy band diagram in a thermal equilibrium state corresponding to the YY' cross-sectional view in FIG. 2. n+ from the left
Region 102 (band gap energy: Eg=1
．． 1 eV), tunnel insulating film 104 (Eg=8 eV),
First semiconductor region 106 (Eg=1.1eV), second tunnel insulating film 114 and insulating film 100 (Eg=8eV)
, corresponds to the control electrode 111 (Eg=1.1 eV).
【００１８】図４はｎ＋領域１０２から電荷を第１の半
導体領域１０６へ入力する『書き込み状態』のエネルギ
ー・バンド図である。制御電極１１１に正電圧を印加し
、ｎ＋領域１０２の印加電圧を０ｖとすると、フローテ
ィング状態にある第１の半導体領域１０６は容量結合に
より正電圧となるためフォラーノルドハイム（以下Ｆｏ
ｗｌｅｒ−Ｎｏｒｄｈｅｉｍという）トンネリングによ
りｎ＋領域１０２から第１の半導体領域１０６へ電子が
注入される。FIG. 4 is an energy band diagram of the "write state" in which charges are input from the n+ region 102 to the first semiconductor region 106. When a positive voltage is applied to the control electrode 111 and the voltage applied to the n+ region 102 is 0V, the first semiconductor region 106 in the floating state becomes a positive voltage due to capacitive coupling, so
Electrons are injected from the n+ region 102 into the first semiconductor region 106 by tunneling (called ler-Nordheim).
【００１９】図５は『保持状態』のエネルギー・バンド
図である。ｎ＋領域１０２と制御電極１１１が０ｖなの
でフローティング状態の第１の半導体領域１０６に注入
された電子は蓄積状態に留まる。FIG. 5 is an energy band diagram of the "holding state". Since n+ region 102 and control electrode 111 are at 0V, electrons injected into first semiconductor region 106 in a floating state remain in an accumulated state.
【００２０】図６は電荷入力部を電荷出力部として利用
できることの説明ともなる電荷の『排出状態』のエネル
ギー・バンド図である。ｎ＋領域１０２に正電圧を印加
し、制御電極１１１を０ｖとするとフローティング状態
の第１の半導体領域１０６は容量結合により正電圧とな
るためＦｏｗｌｅｒ−Ｎｏｒｄｈｅｉｍトンネリングに
より第１の半導体領域１０６からｎ＋領域１０２へ電子
が排出される。FIG. 6 is an energy band diagram of the "discharge state" of charges, which also explains that the charge input section can be used as a charge output section. When a positive voltage is applied to the n+ region 102 and the control electrode 111 is set to 0V, the first semiconductor region 106 in the floating state becomes a positive voltage due to capacitive coupling. Electrons are ejected to
【００２１】図２のＺ−Ｚ’およびＷ−Ｗ’断面に対応
する熱平衡状態のエネルギー・バンド図を図７に示す。
左側から第１の制御電極であるｎ＋領域１０３ａ、トン
ネル絶縁膜１０４と絶縁膜１０５の総和、第１の半導体
領域１０８ａ、絶縁膜１００、第２の制御電極１１０ａ
に対応している。FIG. 7 shows an energy band diagram in a thermal equilibrium state corresponding to the Z-Z' and WW' cross sections in FIG. 2. From the left: the n+ region 103a which is the first control electrode, the sum of the tunnel insulating film 104 and the insulating film 105, the first semiconductor region 108a, the insulating film 100, and the second control electrode 110a.
It corresponds to
【００２２】図８はＺ−Ｚ’断面に対応する転送状態の
エネルギー・バンド図である。第２の制御電極１１０ａ
を０ｖとし、第１の制御電極であるｎ＋領域１０３ａに
正電圧Ｖを印加すると、第２の半導体領域１０８ａの電
位Ｖ２ と第１の半導体領域１０７ａの電位Ｖ１ は容
量結合により０＜Ｖ２ ＜Ｖ１ ＜ＶとなるためＦｏｗ
ｌｅｒ−Ｎｏｒｄｈｅｉｍトンネリングにより、第２の
半導体領域１０８ａから第１の半導体領域１０７ａへ電
荷転送が実施される。FIG. 8 is an energy band diagram of the transfer state corresponding to the Z-Z' cross section. Second control electrode 110a
When is set to 0V and a positive voltage V is applied to the n+ region 103a, which is the first control electrode, the potential V2 of the second semiconductor region 108a and the potential V1 of the first semiconductor region 107a become 0<V2<V1 due to capacitive coupling. ＜V, so Fow
Charge transfer is performed from the second semiconductor region 108a to the first semiconductor region 107a by ler-Nordheim tunneling.
【００２３】図９はＷ−Ｗ’断面に対応する転送状態の
エネルギー・バンド図である。第１の制御電極であるｎ
＋領域１０３ａを０ｖとし、第２の制御電極１１０ａに
正電圧Ｖを印加すると、第１の半導体領域１０７ａの電
位Ｖ１ と第２の半導体領域１０８ａの電位Ｖ２は容量
結合により０＜Ｖ１ ＜Ｖ２ ＜ＶとなるためＦｏｗｌ
ｅｒ−Ｎｏｒｄｈｅｉｍトンネリングにより、第１の半
導体領域１０７ａから第２の半導体領域１０８ａへ電荷
転送が実施される。このような図８、図９の転送動作を
繰り返ことにより、スタック・チャネル形のＣＣＤが実
現する。FIG. 9 is an energy band diagram of the transfer state corresponding to the WW' cross section. n which is the first control electrode
When the + region 103a is set to 0V and a positive voltage V is applied to the second control electrode 110a, the potential V1 of the first semiconductor region 107a and the potential V2 of the second semiconductor region 108a become 0<V1<V2< due to capacitive coupling. Fowl to become V
Charge transfer is performed from the first semiconductor region 107a to the second semiconductor region 108a by er-Nordheim tunneling. By repeating the transfer operations shown in FIGS. 8 and 9, a stacked channel type CCD is realized.
【００２４】以上説明したように、本実施例によれば、
転送領域となる半導体領域が半導体基板の上の絶縁膜中
に埋め込まれているため、電荷の蓄積容量はＤＲＡＭの
ように微細化を駆使したさまざまな手法が適用できるた
め、ＣＣＤ自身の微細化と高性能化が一層推進できる。
しかも、半導体領域の容量は制御電極との間の絶縁膜の
誘電率や厚みで決定されることはＤＲＡＭのセル容量と
同じであるから、ダイナミックレンジもチャネル幅に依
存せず大きくすることが容易である。As explained above, according to this embodiment,
Since the semiconductor region that serves as the transfer region is embedded in the insulating film on the semiconductor substrate, various methods that make use of miniaturization, such as DRAM, can be applied to the charge storage capacity. High performance can be further promoted. Moreover, since the capacitance of the semiconductor region is determined by the dielectric constant and thickness of the insulating film between it and the control electrode, which is the same as the cell capacitance of a DRAM, it is easy to increase the dynamic range without depending on the channel width. It is.
【００２５】図１０、１１は、本発明の第２の実施例の
構造を示すものである。第１の実施例との差異は、図１
の第２の制御電極１１０ａ、１１０ｂ、１１０ｃ、１１
０ｄはもちろん、図１の第１の制御電極１０３ａ、１０
３ｂ、１０３ｃも半導体基板１０１中には形成しないと
ころである。即ち、ｐ基板２０１の表面に電荷注入源と
なるｎ＋領域２０２を形成し、ｐ基板２０１の表面に形
成した絶縁膜２０３の上に複数個の第１の制御電極２０
４ａ、２０４ｂ、２０４ｃなどを形成し、同時に絶縁膜
に開孔した窓を通じてｎ＋領域と接続する電極２０５が
形成される。電極２０５および第１の制御電極２０４ａ
、２０４ｂ、２０４ｃなどの表面に順次形成した第１の
トンネル絶縁膜２０６と絶縁膜２０７の上に複数個の第
１の半導体領域２０８ａ、２０８ｂ、２０８ｃなどを形
成する。同時に、電極２０５とは窓形状に露出した第１
のトンネル絶縁膜２０６だけで隔てられた電荷入力部の
第１の半導体領域２０９を形成する。さらに、第１の半
導体領域とは部分的な重なりを持ちしかも第２のトンネ
ル絶縁膜２１６だけで隔てられた複数個の第２の半導体
領域２１０ａ、２１０ｂ、２１０ｃなどを形成し、続い
て、絶縁膜２１１で隔てられた複数個の第２の制御電極
として２１２ａ、２１２ｂ、２１２ｃを形成する。なお
、第２の制御電極２１２ａ、２１２ｂ、２１２ｃを形成
するときに、電荷入力部の制御電極２１３も同時に形成
される。２１４ａ、２１４ｂ、２１４ｃなどは金属（ア
ルミニウムなど）配線部である。FIGS. 10 and 11 show the structure of a second embodiment of the present invention. The difference from the first embodiment is shown in Figure 1.
second control electrodes 110a, 110b, 110c, 11
0d as well as the first control electrodes 103a and 10 in FIG.
3b and 103c are also not formed in the semiconductor substrate 101. That is, an n+ region 202 serving as a charge injection source is formed on the surface of the p-substrate 201, and a plurality of first control electrodes 20 are formed on the insulating film 203 formed on the surface of the p-substrate 201.
4a, 204b, 204c, etc. are formed, and at the same time, an electrode 205 is formed which is connected to the n+ region through a window opened in the insulating film. Electrode 205 and first control electrode 204a
, 204b, 204c, etc., a plurality of first semiconductor regions 208a, 208b, 208c, etc. are formed on the first tunnel insulating film 206 and the insulating film 207, which are sequentially formed on the surfaces of the first tunnel insulating films 206, 204b, 204c, etc. At the same time, the electrode 205 is connected to the first electrode exposed in the shape of a window.
A first semiconductor region 209 of a charge input section is formed separated only by a tunnel insulating film 206. Furthermore, a plurality of second semiconductor regions 210a, 210b, 210c, etc., which partially overlap with the first semiconductor region and are separated only by the second tunnel insulating film 216, are formed, and then an insulating film is formed. A plurality of second control electrodes 212a, 212b, and 212c are formed separated by the film 211. Note that when forming the second control electrodes 212a, 212b, and 212c, the control electrode 213 of the charge input section is also formed at the same time. 214a, 214b, 214c, etc. are metal (aluminum, etc.) wiring parts.
【００２６】この第２の実施例の動作原理は第１の実施
例の１０３と本実施例の２０４が対応し、エネルギー・
バンド図もまったく同じである。The operating principle of this second embodiment is that 103 of the first embodiment corresponds to 204 of this embodiment, and the energy
The band diagram is exactly the same.
【００２７】[0027]
【発明の効果】以上説明したように本発明は、電荷転送
領域の動作性能である最大転送電荷量に悪影響を与えず
微細化ＣＣＤが実現でき、しかも電荷の転送領域が半導
体基板の外に形成されるためスミアなどもきわめて少な
いＣＣＤとなるため、本発明がもたらす実用的な効果は
大きい。As explained above, the present invention can realize a miniaturized CCD without adversely affecting the maximum transfer charge amount, which is the operating performance of the charge transfer region, and furthermore, the charge transfer region can be formed outside the semiconductor substrate. As a result, a CCD with very little smear etc. is obtained, and the practical effects of the present invention are great.
【図１】本発明の第１の実施例の電荷転送素子の構造を
示す平面図である。FIG. 1 is a plan view showing the structure of a charge transfer device according to a first embodiment of the present invention.
【図２】第１の実施例の電荷転送素子の断面図である。FIG. 2 is a cross-sectional view of the charge transfer element of the first example.
【図３】〜[Figure 3] ~
【図９】それぞれ各種状態に対応するエネルギー・バン
ド図である。FIG. 9 is an energy band diagram corresponding to various states.
【図１０】本発明の第２の実施例の電荷転送素子を示す
平面図である。FIG. 10 is a plan view showing a charge transfer device according to a second embodiment of the present invention.
【図１１】本発明の第２の実施例の電荷転送素子を示す
断面図である。FIG. 11 is a cross-sectional view showing a charge transfer device according to a second embodiment of the present invention.
【図１２】及び[Figure 12] and
【図１３】それぞれ従来のＣＣＤの構造を示す斜視図で
ある。FIG. 13 is a perspective view showing the structure of a conventional CCD.
１００、１０９ 絶縁膜
１０３、２０４ 第１の制御電極
１０４、２０６ 第１のトンネル絶縁膜１０７、２０
８ 第１の半導体領域
１１４、２１６ 第２のトンネル絶縁膜１０８、２１
０ 第２の半導体領域
１１０、２１２ 第２の制御電極100, 109 Insulating film 103, 204 First control electrode 104, 206 First tunnel insulating film 107, 20
8 First semiconductor region 114, 216 Second tunnel insulating film 108, 21
0 Second semiconductor region 110, 212 Second control electrode
Claims (4)
膜に電荷転送領域として埋め込まれた複数の半導体領域
と、前記半導体領域の電位を制御する為に前記半導体領
域に対応して設けられた制御電極と、前記各半導体領域
を相互に隔てるトンネル絶縁膜とを備えたこと特徴とす
る電荷転送装置。1. An insulating film on the surface of a semiconductor substrate, a plurality of semiconductor regions embedded in the insulating film as charge transfer regions, and a semiconductor region provided corresponding to the semiconductor region to control the potential of the semiconductor region. A charge transfer device comprising a control electrode and a tunnel insulating film separating the semiconductor regions from each other.
第１の半導体領域と、前記第１の半導体領域の間隙部分
に対応するように平行させて１次元配列した第２の半導
体領域と、前記第１の半導体領域と前記第２の半導体領
域の間に形成されたトンネル絶縁膜と、前記第１の半導
体領域の電位を制御する第１の制御電極と、前記第２の
半導体領域の電位を制御する第２の制御電極とを備えた
ことを特徴とする電荷転送装置。2. A first semiconductor region arranged one-dimensionally in a charge transfer direction, and a second semiconductor region arranged one-dimensionally parallel to each other so as to correspond to a gap between the first semiconductor regions. a tunnel insulating film formed between the first semiconductor region and the second semiconductor region; a first control electrode for controlling the potential of the first semiconductor region; and a potential of the second semiconductor region. A charge transfer device comprising: a second control electrode for controlling the charge transfer device.
領域と、前記半導体基板表面の第１の絶縁膜に開孔され
た窓を通じて前記高不純物領域と接続された第１の制御
電極と、前記第１の制御電極と全体的な重なりを持ちし
かも第１のトンネル絶縁膜で隔てられた第１の半導体領
域と、前記第１の半導体領域と部分的な重なりを持ちし
かも第２のトンネル絶縁膜で隔てられた第２の半導体領
域と、前記第１の半導体領域と部分的な重なりを持ち、
しかも第２の絶縁膜で隔てられた第２の制御電極とを備
えたことを特徴とする電荷転送装置。3. A high impurity region formed on a surface of a semiconductor substrate, a first control electrode connected to the high impurity region through a window opened in a first insulating film on the surface of the semiconductor substrate, and a first semiconductor region that completely overlaps the first control electrode and is separated by a first tunnel insulating film; a second tunnel insulating film that partially overlaps the first semiconductor region; a second semiconductor region separated by a region that partially overlaps the first semiconductor region;
A charge transfer device further comprising a second control electrode separated by a second insulating film.
不純物領域と、前記第１の不純物領域と同一導電形で複
数個の第２の高不純物領域と、前記第１の不純物領域と
全体的な重なりを持ちしかも前記半導体基板表面の第１
のトンネル絶縁膜で隔てられた第１の半導体領域と、前
記第１の半導体領域と部分的な重なりを持ちしかも第２
のトンネル絶縁膜で隔てられた第２の半導体領域と、前
記第１の半導体領域と部分的な重なりを持ちしかも第２
の絶縁膜で隔てられた第２の制御電極とを備えたことを
特徴とする電荷転送装置。4. A first high impurity region formed on a surface of a semiconductor substrate, a plurality of second high impurity regions having the same conductivity type as the first impurity region, and a plurality of second high impurity regions formed on the surface of the semiconductor substrate, and a plurality of second high impurity regions formed on the surface of the semiconductor substrate. the first layer on the surface of the semiconductor substrate.
a first semiconductor region separated by a tunnel insulating film, and a second semiconductor region partially overlapping with the first semiconductor region;
a second semiconductor region separated by a tunnel insulating film; and a second semiconductor region partially overlapping with the first semiconductor region and separated by a tunnel insulating film.
and a second control electrode separated by an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3018580A JPH04257233A (en) | 1991-02-12 | 1991-02-12 | Charge transfer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3018580A JPH04257233A (en) | 1991-02-12 | 1991-02-12 | Charge transfer device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04257233A true JPH04257233A (en) | 1992-09-11 |
Family
ID=11975569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3018580A Pending JPH04257233A (en) | 1991-02-12 | 1991-02-12 | Charge transfer device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04257233A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06120262A (en) * | 1992-10-06 | 1994-04-28 | Matsushita Electric Ind Co Ltd | Charge transfer device |
| KR20020057285A (en) * | 2000-12-30 | 2002-07-11 | 박종섭 | Image sensor havig 3-structual light collecting area |
| WO2014199642A1 (en) * | 2013-06-13 | 2014-12-18 | Tadao Nakamura | A direct-transfer marching memory and a computer system using the same |
-
1991
- 1991-02-12 JP JP3018580A patent/JPH04257233A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06120262A (en) * | 1992-10-06 | 1994-04-28 | Matsushita Electric Ind Co Ltd | Charge transfer device |
| KR20020057285A (en) * | 2000-12-30 | 2002-07-11 | 박종섭 | Image sensor havig 3-structual light collecting area |
| WO2014199642A1 (en) * | 2013-06-13 | 2014-12-18 | Tadao Nakamura | A direct-transfer marching memory and a computer system using the same |
| JP2016524264A (en) * | 2013-06-13 | 2016-08-12 | 維男 中村 | Direct transfer marching memory and computer system using the same |
| US9449696B2 (en) | 2013-06-13 | 2016-09-20 | Tadao Nakamura | Direct-transfer marching memory and a computer system using the same |
| TWI557749B (en) * | 2013-06-13 | 2016-11-11 | 中村維男 | A direct-transfer marching memory and a computer system using the same |
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