JPH0421105Y2 - - Google Patents
Info
- Publication number
- JPH0421105Y2 JPH0421105Y2 JP1983149464U JP14946483U JPH0421105Y2 JP H0421105 Y2 JPH0421105 Y2 JP H0421105Y2 JP 1983149464 U JP1983149464 U JP 1983149464U JP 14946483 U JP14946483 U JP 14946483U JP H0421105 Y2 JPH0421105 Y2 JP H0421105Y2
- Authority
- JP
- Japan
- Prior art keywords
- package
- presser
- guide
- lead terminal
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012360 testing method Methods 0.000 claims description 25
- 238000005259 measurement Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 2
- 238000007667 floating Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Description
【考案の詳細な説明】 (a) 考案の技術分野 本考案は半導体IC用試験装置の構造に関する。[Detailed explanation of the idea] (a) Technical field of invention The present invention relates to the structure of a test device for semiconductor ICs.
(b) 技術の背景
フラツトパツケージには磁器外装のもの、樹脂
モールド外装のものなど色々の外装形態がある
が、半導体IC（以後略してIC）はパツケージング
処理後、自動試験機によりDC試験、AC試験、フ
アンクシヨン試験を連続して行い良品を選別す
る。(b) Background of the technology There are various types of flat packages, such as those with a porcelain exterior and those with a resin molded exterior.After packaging, semiconductor ICs (hereinafter referred to as ICs) are subjected to DC testing using an automatic testing machine. , AC test, and function test are conducted continuously to select non-defective products.
本考案はICを試験するための試験装置に関す
るものである。 The present invention relates to a test device for testing ICs.
(c) 従来技術と問題点
第１図は従来の試験装置で、Ａは側面図、Ｂは
正面図である。(c) Prior art and problems Figure 1 shows a conventional testing device, with A being a side view and B being a front view.
ここで試験装置は合成樹脂などの絶縁材料で形
成され、上部にICパツケージ１を位置決めする
ための凹部２を備え凸状の断面をもつ基板部３
と、上方よりICパツケージ１とそのリード端子
４を押圧する押え部５とから成つている。ここで
基板部３の両側にはICパツケージ１よりのリー
ド端子４に正しく位置合わせされて複数個の接触
端子６が埋め込まれており、その他端は測定端子
７となつて自動試験機へ結線されている。 Here, the test device is made of an insulating material such as synthetic resin, has a concave part 2 for positioning the IC package 1 on the upper part, and has a board part 3 having a convex cross section.
and a holding part 5 that presses the IC package 1 and its lead terminals 4 from above. Here, a plurality of contact terminals 6 are embedded on both sides of the board part 3, aligned correctly with the lead terminals 4 from the IC package 1, and the other end becomes a measurement terminal 7 and is connected to an automatic testing machine. ing.
この試験装置の使用法としては、ICパツケー
ジ１を基板部３の凹部２にセツトした状態で押え
部５を降下させると、押え部５の下面８がICパ
ツケージ１の上面に接触した状態では押え部５の
押え板９がリード端子４を押圧し、リード端子４
と接触端子６とが充分に接触するよう構成されて
いる。すなわち、第１図Ａで示すイとロの距離は
等しく設計してある。ここでICパツケージ１の
厚さが正しく規定寸法内に納まつている場合はこ
れでよいが、ICの厚さ寸法が規定公差を外れて
厚すぎた場合は、リード端子４と接触端子６との
接触が不充分となつて誤測定の原因となり、一方
薄すぎた場合はリード端子４が過度に押圧される
結果として変形を起し、信頼度を損うと云う問題
点があつた。 How to use this test device is that when the IC package 1 is set in the recess 2 of the circuit board section 3 and the presser section 5 is lowered, the lower surface 8 of the presser section 5 is in contact with the upper surface of the IC package 1. The holding plate 9 of the portion 5 presses the lead terminal 4, and the lead terminal 4
and the contact terminal 6 are configured so as to be in sufficient contact with each other. That is, the distances between A and B shown in FIG. 1A are designed to be equal. This is fine if the thickness of the IC package 1 is correctly within the specified dimensions, but if the thickness of the IC exceeds the specified tolerance and is too thick, the lead terminals 4 and contact terminals 6 If the lead terminal 4 is too thin, the lead terminal 4 may be pressed too much, resulting in deformation, which impairs reliability.
(d) 考案の目的
本考案の目的はフラツトパツケージタイプの
IC試験において、適正な接触圧でリード端子と
接触端子とが接触し得る試験装置を提供すること
を目的とする。(d) Purpose of the invention The purpose of the invention is to develop a flat package type
The purpose of the present invention is to provide a test device that allows lead terminals and contact terminals to come into contact with appropriate contact pressure in IC testing.
(e) 考案の構成
本考案の目的は、フラツトパツケージタイプ半
導体ICの試験を行う試験装置が、
スプリングを備えてICパツケージを保持するガ
イド部と、
このガイド部を囲んで設けられ、複数個の接触端
子と測定端子を備えた基板部と、
このガイド部に対向し、ガイド部押えとリード端
子押えを備え、上下にスライド可能に設けられて
いる押え部とからなり、
この押え部を降下させ、ガイド部押えによりガイ
ド部を押し下げる際、まずICパツケージのリー
ド端子が基板部の接触端子に接触し、更に押え部
の降下によりリード端子押えがICパツケージの
リード端子を圧接した状態で測定を行うことを特
徴として半導体IC試験装置を構成することによ
り達成することができる。(e) Structure of the invention The purpose of the invention is to provide a test device for testing flat package type semiconductor ICs, which includes a guide part equipped with a spring to hold an IC package, and a plurality of guide parts provided surrounding this guide part. It consists of a board part equipped with contact terminals and measurement terminals, and a holding part that faces this guide part and is equipped with a guide part holder and a lead terminal holder and is slidable up and down. Then, when pressing down the guide part with the guide part holder, the lead terminal of the IC package first comes into contact with the contact terminal of the board part, and then the lead terminal holder presses the lead terminal of the IC package by lowering the holder part, and then the measurement is taken. This can be achieved by configuring a semiconductor IC testing device with the following characteristics.
(f) 考案の実施例
第２図は本考案に係る試験装置の側面図Ａと正
面図Ｂである。(f) Embodiment of the invention Figure 2 is a side view A and a front view B of a test device according to the invention.
本考案はIC試験を行う場合にパツケージ１に
力を加えず浮いた状態にしてリード端子４のみを
押圧するもので、ICパツケージ１をセツトする
ガイド部１０はスプリング１１により上下に移動
可能に構成されており、これを中心にして複数個
の接触端子６と測定端子７ともつ基板部３がモー
ルド成型などの方法で作られている。また、この
上部には前後にガイド部１０を押えるためのガイ
ド部押え１２と、左右リード端子４を押えるため
のリード端子押え１３を備えた押え部５が上下に
移動可能に形成されている。ここでガイド部押え
１２はガイド部１０を押し下げるものでICパツ
ケージ１とは接触しない。ここで押え部５のリー
ド端子押え１３の下面とガイド部押え１２の下面
との距離ハは、ICパツケージ１の上面とリード
端子４の下端との距離ニと較べて充分に大きくと
つてあるので押え部５が降下し、ガイド部押え１
２がガイド部１０を押し下げてリード端子押え１
３がリード端子４と接触した状態ではICパツケ
ージは浮き状態に保持されており、そのためIC
パツケージ１の厚さが規定寸法公差を外れている
場合でも押え部５の降下距離が変らぬ限り、リー
ド端子に変形を生ずることはない。 In the present invention, when performing an IC test, only the lead terminals 4 are pressed while the package 1 is in a floating state without applying force, and the guide section 10 for setting the IC package 1 is configured to be movable up and down by a spring 11. A substrate portion 3 having a plurality of contact terminals 6 and measurement terminals 7 is formed around this by a method such as molding. Moreover, a presser part 5 is formed in the upper part, which is movable up and down, and includes a guide part presser 12 for pressing the guide part 10 back and forth, and a lead terminal presser 13 for pressing the left and right lead terminals 4. Here, the guide portion presser 12 presses down the guide portion 10 and does not come into contact with the IC package 1. Here, the distance C between the lower surface of the lead terminal presser 13 of the presser section 5 and the lower surface of the guide section presser 12 is set to be sufficiently larger than the distance C between the upper surface of the IC package 1 and the lower end of the lead terminal 4. The presser foot 5 descends, and the guide presser foot 1
2 pushes down the guide part 10 and presses the lead terminal holder 1.
3 is in contact with lead terminal 4, the IC package is held in a floating state, so the IC
Even if the thickness of the package 1 is outside the specified dimensional tolerance, the lead terminals will not be deformed as long as the descending distance of the presser portion 5 remains unchanged.
なお、押え部５の降下距離はリード端子４に一
定の押圧を加えるよう正しく設定されている。第
３図Ａ，Ｂはリード端子押え１３に押圧され、リ
ード端子４と接触端子６とが接触した状態を示し
ている。 Note that the descending distance of the presser portion 5 is correctly set so as to apply a constant pressure to the lead terminal 4. 3A and 3B show a state in which the lead terminal 4 and the contact terminal 6 are pressed by the lead terminal presser 13 and are in contact with each other.
以上のように本考案に係る試験装置は、ICパ
ツケージ１を浮き状態としてリード端子のみを一
定圧で押圧するため、リード端子４と接触端子６
との間に接触不良や過度の圧力が加わることはな
い。 As described above, the test device according to the present invention leaves the IC package 1 in a floating state and presses only the lead terminals with a constant pressure.
There will be no poor contact or excessive pressure between the two.
(g) 考案の効果
モールド成型されたフラツトパツケージは、モ
ールド条件により厚さ寸法に変動が生じ易い。そ
れで従来の試験装置を用いる場合は、パツケージ
内のIC素子が良品であるにも抱わらず不良品と
して判定されたり、リード端子の一部が変形する
などの障害が起り易かつたが、本考案の実施によ
りこれらの障害はなくなり、信頼度の向上に寄与
することができた。(g) Effects of the invention The thickness of a molded flat package tends to vary depending on the molding conditions. Therefore, when using conventional test equipment, failures such as the IC element in the package being judged as a defective product even though it is good or a part of the lead terminal deforming tend to occur. By implementing the idea, these obstacles were eliminated, contributing to improved reliability.
第１図は従来のIC試験装置で、Ａは側面図、
Ｂは正面図、第２図は本考案に係るIC試験装置
で、Ａは側面図、Ｂは正面断面図、また第３図は
接触状態を示すもので、Ａは側面図、Ｂは正面断
面図である。
図において、１はICパツケージ、３は基板部、
４はリード端子、５は押え部、６は接触端子、７
は測定端子、１０はガイド部、１１はスプリン
グ、１２はガイド部押え、１３はリード端子押
え。
Figure 1 shows a conventional IC test device, where A is a side view;
B is a front view, FIG. 2 is an IC test device according to the present invention, A is a side view, B is a front sectional view, and FIG. 3 is a contact state, A is a side view, and B is a front sectional view. It is a diagram. In the figure, 1 is an IC package, 3 is a board part,
4 is a lead terminal, 5 is a holding part, 6 is a contact terminal, 7
10 is a measurement terminal, 10 is a guide portion, 11 is a spring, 12 is a guide portion holder, and 13 is a lead terminal holder.
Claims (1)
行う試験装置が、 スプリング１１を備えてICパツケージ１を保持
するガイド部１０と、 該ガイド部１０を囲んで設けられ、複数個の接触
端子６と測定端子７を備えた基板部３と、 前記ガイド部１０に対向し、ガイド部押え１２と
リード端子押え１３を備え、上下にスライド可能
に設けられている押え部５と、 からなり、該押え部５を降下させ、ガイド部押え
１２によりガイド部１０を押し下げる際、ICパ
ツケージのリード端子４が基板部３の接触端子６
に接触し、更に押え部５の降下により、リード端
子押え１３がICパツケージ１のリード端子４を
圧接した状態で測定を行うことを特徴とする半導
体IC試験装置。[Scope of Claim for Utility Model Registration] A testing device for testing a flat package type semiconductor IC comprises: a guide portion 10 having a spring 11 and holding an IC package 1; and a plurality of guide portions provided surrounding the guide portion 10. a substrate part 3 equipped with a contact terminal 6 and a measurement terminal 7; a presser part 5 that faces the guide part 10 and is provided with a guide part presser 12 and a lead terminal presser 13 and is slidable up and down; When the holding part 5 is lowered and the guide part 10 is pushed down by the guide part holding part 12, the lead terminals 4 of the IC package are connected to the contact terminals 6 of the board part 3.
A semiconductor IC testing device characterized in that measurement is carried out in a state in which a lead terminal presser 13 presses a lead terminal 4 of an IC package 1 by lowering the presser portion 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14946483U JPS6056285U (en) | 1983-09-27 | 1983-09-27 | Semiconductor IC testing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14946483U JPS6056285U (en) | 1983-09-27 | 1983-09-27 | Semiconductor IC testing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6056285U JPS6056285U (en) | 1985-04-19 |
| JPH0421105Y2 true JPH0421105Y2 (en) | 1992-05-14 |
Family
ID=30331781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14946483U Granted JPS6056285U (en) | 1983-09-27 | 1983-09-27 | Semiconductor IC testing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6056285U (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0636390B2 (en) * | 1989-03-22 | 1994-05-11 | 山一電機工業株式会社 | IC socket |
| JP4785190B2 (en) * | 2006-03-15 | 2011-10-05 | 大西電子株式会社 | Inspection socket for semiconductor devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6034031A (en) * | 1983-08-05 | 1985-02-21 | Tokyo Seimitsu Co Ltd | Device for measuring semiconductor element |
-
1983
- 1983-09-27 JP JP14946483U patent/JPS6056285U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6034031A (en) * | 1983-08-05 | 1985-02-21 | Tokyo Seimitsu Co Ltd | Device for measuring semiconductor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6056285U (en) | 1985-04-19 |
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