JPH04199667A - Package and its soldering method - Google Patents
Package and its soldering methodInfo
- Publication number
- JPH04199667A JPH04199667A JP33112590A JP33112590A JPH04199667A JP H04199667 A JPH04199667 A JP H04199667A JP 33112590 A JP33112590 A JP 33112590A JP 33112590 A JP33112590 A JP 33112590A JP H04199667 A JPH04199667 A JP H04199667A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output pins
- package
- pins
- protective layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 title abstract description 17
- 238000000034 method Methods 0.000 title abstract description 12
- 239000011241 protective layer Substances 0.000 claims abstract description 22
- 239000011347 resin Substances 0.000 claims abstract description 19
- 229920005989 resin Polymers 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 12
- 239000002904 solvent Substances 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 10
- 238000005452 bending Methods 0.000 abstract description 9
- 238000004140 cleaning Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 17
- 230000000694 effects Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000001476 alcoholic effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
入出力ピンが配列されたパッケージの配列面に保護層ま
たは保護板を設けるように形成したパッケージに関し、
半田付は工程においてピンの曲が生じることのないよう
にすることを目的とし、
入出力ピンが配列されたパッケージの配列面に溶剤洗浄
型樹脂材を塗布、硬化させることで該入出力ピンの配列
ピッチを拘束するよう固定させる所定の厚みの保護層を
該配列面に積層するように、また、入出力ピンが配列さ
れたパッケージの配列面に溶剤洗浄型樹脂材によって形
成され、該入出力ピンの配列ピッチを拘束するよう該入
出力ピンを固定する貫通穴を備えた所定の厚みの保護板
を固着するように構成する。[Detailed Description of the Invention] [Summary] Regarding a package formed in such a way that a protective layer or a protective plate is provided on the array surface of the package where input/output pins are arranged, the soldering process is performed to prevent the pins from bending. A protective layer of a predetermined thickness is applied to the arrangement surface of the package where the input/output pins are arranged, and is fixed by applying and curing a solvent-cleanable resin material to restrain the arrangement pitch of the input/output pins. is laminated on the arrangement surface, and is formed of a solvent-washed resin material on the arrangement surface of the package where the input/output pins are arranged, and fixes the input/output pins so as to restrict the arrangement pitch of the input/output pins. A protective plate having a predetermined thickness and having a through hole is fixed thereto.
本発明は、入出力ピンが配列されたパッケージの配列面
に保護層または保護板を設けるように形成したパッケー
ジに関する。The present invention relates to a package formed such that a protective layer or a protective plate is provided on the array surface of the package where input/output pins are arrayed.
近年、基板の高密度化、電子部品の高集積化が推進され
るようになり、電子部品に於ける入出力端子は、多ピン
化される傾向となった。BACKGROUND ART In recent years, there has been a trend toward higher density boards and higher integration of electronic components, and there has been a trend toward increasing the number of input/output terminals in electronic components.
そこで、半導体素子を構成するパッケージには多数の入
出力ピンを配設したピンクリットアレイパッケージ（Ｐ
ＧＡ）が用いられるようになった。Therefore, the package constituting the semiconductor element is a pin-lit array package (P), which has a large number of input/output pins.
GA) came to be used.
従来は第６図の従来の説明図に示すように構成されてい
た。第６図の（ａ）はパッケージの斜視図部側の配列面
３には所定のピッチＰによって複数の入出力ピン２が配
列されるように形成され、入出力ピン２を介して所定の
電気信号の入出力が行われる。Conventionally, the configuration was as shown in the conventional explanatory diagram of FIG. 6. In FIG. 6(a), a plurality of input/output pins 2 are arranged at a predetermined pitch P on the arrangement surface 3 on the perspective view side of the package, and a predetermined electricity is transmitted via the input/output pins 2. Signals are input and output.
このようなパッケージＩを基板に実装する場合は、（ｂ
ｌ）に示すように、入出力ピン２のピッチＰに対応する
ように基板ＩＯに配設されたパッド１１に予備半田１１
を施し、それぞれのパッドＩＩに入出力ピン２を位置決
めし、所定温度に加熱をすることで予備半田１１を溶融
させ、（ｂ２）に示すように、入出力ピン２の先端をパ
ッドＩＩに半田１２Ａによって接合させることが行われ
ていた。When mounting such a package I on a board, (b
As shown in FIG.
, position the input/output pins 2 on each pad II, melt the preliminary solder 11 by heating to a predetermined temperature, and solder the tips of the input/output pins 2 to the pads II as shown in (b2). 12A was used for joining.
また、この場合の予備半田１１は、基板１０に対する熱
ストレスを極力避けるよう入出力ピン２の先端に施すこ
ともある。Further, the preliminary solder 11 in this case may be applied to the tips of the input/output pins 2 to avoid thermal stress on the board 10 as much as possible.
しかし、このような入出力ピン２は外力が加わることで
容易に曲折するため、半田工程に於いて入出力ピン２に
曲折が生じる場合があり、特に、配列ピッチＰが微小な
値であれば、半田による接合で隣接間が短絡される問題
があった。However, since such input/output pins 2 are easily bent by external force, bending may occur in the input/output pins 2 during the soldering process, especially if the arrangement pitch P is a minute value. However, there was a problem in that adjacent devices were short-circuited due to solder bonding.
したがって、このような隣接間が短絡されるような障害
が生じた場合は、−旦半田付けされたパッケージ１を取
外し、入出力ピン２の曲折を直し、再度半田付けを行っ
ていた。Therefore, in the event that a fault such as short-circuit between adjacent devices occurs, the previously soldered package 1 must be removed, the input/output pins 2 bent, and then soldered again.
そこで、本発明では、半田付は工程においてピンの曲が
生じることのないようにすることを目的とする。Therefore, an object of the present invention is to prevent pins from bending during the soldering process.
第１図は本第１の発明の原理説明図で、第２図は本第２
の発明の原理説明図である。Figure 1 is an explanatory diagram of the principle of the first invention, and Figure 2 is an illustration of the principle of the second invention.
FIG. 2 is a diagram illustrating the principle of the invention.
第１図および第２図に示すように、入出力ピン２が配列
されたパッケージｌの配列面３に溶剤洗浄型樹脂材を塗
布、硬化させることで該入出力ピン２の配列ピッチＰを
拘束するよう固定させる所定の厚みＴの保護層４を該配
列面３に積層するように、または、入出力ピン２が配列
されたパッケージｌの配列面３に溶剤洗浄型樹脂材によ
って形成され、該入出力ピン２の配列ピッチＰを拘束す
るよう該入出力ピン２を固定する貫通穴６を備えた所定
の厚みＴの保護板５を固着するように構成する。As shown in FIGS. 1 and 2, the arrangement pitch P of the input/output pins 2 is restrained by coating and curing a solvent-cleanable resin material on the arrangement surface 3 of the package l on which the input/output pins 2 are arranged. A protective layer 4 of a predetermined thickness T is laminated on the arrangement surface 3 to fix the input/output pins 2, or a protective layer 4 is formed of a solvent-cleanable resin material on the arrangement surface 3 of the package l on which the input/output pins 2 are arranged. A protective plate 5 having a predetermined thickness T and provided with through holes 6 for fixing the input/output pins 2 is fixed so as to restrict the arrangement pitch P of the input/output pins 2.
このように構成することによって前述の課題は解決され
る。With this configuration, the above-mentioned problem is solved.
即ち、パッケージ１の入出力ピン２が配列された配列面
３に溶剤洗浄型樹脂材より成る保護層４または保護板５
を設け、保護層４または保護板５によって入出力ピン２
が曲折することな（、所定ピッチＰを維持するように人
出カピン２を拘束するように形成する。That is, a protective layer 4 or a protective plate 5 made of a solvent-cleanable resin material is placed on the array surface 3 on which the input/output pins 2 of the package 1 are arrayed.
is provided, and the input/output pin 2 is
The pins 2 are formed so as to be restrained so as not to bend (and maintain a predetermined pitch P).
また、保護層４および保護板５は溶剤によって溶解する
ことができ、入出力ピン２を所定のパッドに半田付は後
、溶剤によって洗浄を行うことで溶解させ、除去し、半
田付は工程に於いて入出力ピン２の曲折が生じることの
ないようにすることができ、従来発生していた入出力ピ
ン２の曲折による再半田付は作業をなくすことができる
。In addition, the protective layer 4 and the protective plate 5 can be dissolved with a solvent, and after soldering the input/output pin 2 to a predetermined pad, they are dissolved and removed by cleaning with a solvent, and the soldering is done in the process. In this case, bending of the input/output pin 2 can be prevented, and re-soldering work due to bending of the input/output pin 2, which conventionally occurs, can be eliminated.
以下本発明を第３図〜第５図を参考に詳細に説明する。 The present invention will be explained in detail below with reference to FIGS. 3 to 5.
第３図は本第１の発明による一実施例の説明図で、（ａ
）は側面図、 （ｂｌ）（ｂ２）は製造工程図、第４図
は本第２の発明による一実施例の説明図で、（ａ）は側
面図、（ｂ）は製造説明図、第５図の（ａ）〜（４）は
本発明の半田付は工程図である。全図を通じて、同一符
号は同一対象物を示す。FIG. 3 is an explanatory diagram of an embodiment according to the first invention, (a
) is a side view, (bl) and (b2) are manufacturing process diagrams, and FIG. 4 is an explanatory diagram of an embodiment according to the second invention. 5(a) to (4) are process diagrams of the soldering process of the present invention. The same reference numerals indicate the same objects throughout the figures.
第３図の（ａ）に示すように、パッケージ１の入出力ピ
ン２が配列された配列面３に厚みＴの保護層４を積層す
るようにしたものである。As shown in FIG. 3(a), a protective layer 4 having a thickness of T is laminated on an arrangement surface 3 on which input/output pins 2 of a package 1 are arranged.
このような保護層４の積層は、（ｂｌ）に示すように、
配列面３を上側にし、ゲル状の溶剤洗浄型樹脂７、例え
ば、ゴム系樹脂のポリアルキラール樹脂を載せ、スピン
コードなどによって塗布を行う、塗布後は６０℃で、約
３Ｈの硬化を行う。このように硬化させることで（ｂ２
）に示すように所定の厚みＴの保護層４を配列面３に形
成することが行える。The lamination of such a protective layer 4 is as shown in (bl),
With the array surface 3 facing upward, place a gel-like solvent-washable resin 7, such as a polyalkyral resin such as a rubber-based resin, and apply using a spin cord or the like. After application, cure at 60° C. for about 3 hours. . By curing in this way (b2
), a protective layer 4 having a predetermined thickness T can be formed on the array surface 3.
この場合、入出力ピン２の先端を入出力ピン２の全長の
１０〜２０％となる所定量Ｓだけ突出させ、半田付けに
際して半田の濡れ性を考慮する必要がある。In this case, it is necessary to make the tip of the input/output pin 2 protrude by a predetermined amount S, which is 10 to 20% of the total length of the input/output pin 2, and to take into consideration the wettability of the solder during soldering.
このように構成すると、入出力ピン２に多少の外力が加
わっても入出力ピン２が曲折することがなく、入出力ピ
ン２の配列ピッチＰを所定の基準値に維持させることが
できる。With this configuration, even if some external force is applied to the input/output pins 2, the input/output pins 2 will not bend, and the arrangement pitch P of the input/output pins 2 can be maintained at a predetermined reference value.
また、第４図の場合は、（ａ）に示すように、パッケー
ジｌの入出力ピン２が配列された配列面３に厚みＴの保
護板５を固着するようにしたものである。Further, in the case of FIG. 4, as shown in (a), a protection plate 5 having a thickness T is fixed to the arrangement surface 3 on which the input/output pins 2 of the package 1 are arranged.
このような保護板５を固着することは、（ｂ）に示すよ
うに、予め、溶剤洗浄型樹脂７である例えば、ゴム系樹
脂のポリアルキラール樹脂材を用い、モールド成形によ
って、入出力ピン２の配列ピッチＰと同ｂピッチの貫通
穴６を有する保護板５を形成し、貫通穴６に入出力ピン
２を挿入させることで配列面３に保護板５を装着し、配
列面３と保護板５との当接面に接着材を塗布し、接着に
よって固着を行う。To fix such a protection plate 5, as shown in (b), the input/output pins are fixed in advance by molding using a solvent-washed resin 7, for example, a polyalkyral resin material such as a rubber-based resin. The protection plate 5 is formed with through holes 6 having the same pitch b as the arrangement pitch P of 2, and the protection plate 5 is attached to the arrangement surface 3 by inserting the input/output pins 2 into the through holes 6. An adhesive is applied to the contact surface with the protection plate 5, and the protective plate 5 is fixed by adhesion.
この場合も前述と同様、保護板５の厚みが所定の厚みＴ
となるようにし、入出力ピンの先端に所定量Ｓによる突
出が行えるようにする必要がありまた、貫通穴６の径は
入出力ピン２の径よりも若干大きい程度に形成し、保護
板５を押圧することで装着行えるようにする。In this case as well, the thickness of the protective plate 5 is the predetermined thickness T.
It is necessary to make the tip of the input/output pin protrude by a predetermined amount S, and the diameter of the through hole 6 is formed to be slightly larger than the diameter of the input/output pin 2. It can be attached by pressing .
このように構成すると保護板５の装着によって入出力ピ
ン２の曲折を防ぐことができ、配列ピッチＰを所定の基
準値に維持させることができる。With this configuration, the input/output pins 2 can be prevented from bending by attaching the protection plate 5, and the arrangement pitch P can be maintained at a predetermined reference value.
また、第４図の構成では、前述の第３図の場合のような
硬化が不要となり、入出力ピン２対して硬化時の収縮に
よる影響を受けることがない利点かある。Further, the configuration shown in FIG. 4 does not require curing as in the case of FIG. 3 described above, and has the advantage that the input/output pin 2 is not affected by shrinkage during curing.
更に、入出力ピン２を半田付けする場合は、第５図に示
すように行う。Furthermore, when the input/output pin 2 is soldered, it is performed as shown in FIG.
配列面３に保護層４または保護板５が形成されたパッケ
ージｌを基板１０の上に載せ、先づ、（ａ）に示すよう
に、入出力ピン２の配列ピッチＰに対応するように基板
ｌに配設されたパッド１１に対して、それぞれの入出力
ピン２を合致させるように位置決めを行う。The package l, in which the protective layer 4 or the protective plate 5 is formed on the array surface 3, is placed on the substrate 10, and first, as shown in (a), the substrate is Positioning is performed so that the respective input/output pins 2 are aligned with the pads 11 disposed at 1.
この場合、パッド１１には、予め、予備半田１２が施さ
れている。In this case, preliminary solder 12 is applied to the pad 11 in advance.
そこで、予備半田１２が溶融する温度に加熱し、（ｂ）
に示すように入出力ピン２の先端を半田１２Ａによって
パッド１１に接合する。Therefore, the preliminary solder 12 is heated to a temperature that melts it, and (b)
The tip of the input/output pin 2 is bonded to the pad 11 with solder 12A as shown in FIG.
次に、入出力ピン２をパッドＩＩに接合した後、溶剤に
よって洗浄し、（ｃ）に示すように、保護層４または保
護板５を溶解し、除去を行う。Next, after the input/output pin 2 is bonded to the pad II, it is cleaned with a solvent to dissolve and remove the protective layer 4 or the protective plate 5, as shown in FIG.
この場合、溶剤としては、前述の樹脂材を用いた時は、
例えば、アルコール系のイソプロピルアルコールなどを
用いることで溶解させることができる。In this case, when the above-mentioned resin material is used as the solvent,
For example, it can be dissolved using alcoholic isopropyl alcohol.
また、樹脂の種類によっては半田付は時の加熱によって
重合度が変化し、洗浄による溶解が不可能となることが
あるため、極力低温度によって半田付けを行うよう、予
備半田１２としては、例えば、低融点の半田（Ｉｎ−５
ｎ ＋α、５ｎ−Ｐｂ−Ｂｉ系）を用いると良い。Also, depending on the type of resin, the degree of polymerization during soldering may change due to heating, making it impossible to dissolve by washing. , low melting point solder (In-5
n + α, 5n-Pb-Bi system) is preferably used.
尚、本発明では、予備半田１２はパッドＩＩに施すこと
で説明したが、入出力ピン２の先端に予備半田１２を施
すことでも良く、この場合でも同等の効果を得るこがで
きる。In the present invention, the preliminary solder 12 is applied to the pad II, but the preliminary solder 12 may also be applied to the tip of the input/output pin 2, and the same effect can be obtained in this case as well.
以上説明したように、本発明によれば、溶剤洗浄型樹脂
材より成る保護層または保護板をパッケージの入出力ピ
ンの配列面に設け、保護層または保護板により入出力ピ
ンを拘束させることで半田付けを行い、半田付けに際し
ての入出力ピンに外力が加わることによる曲折を防ぐこ
とが行える。As explained above, according to the present invention, a protective layer or a protective plate made of a solvent-cleanable resin material is provided on the input/output pin arrangement surface of the package, and the input/output pins are restrained by the protective layer or protective plate. Soldering can be performed to prevent bending due to external force being applied to the input/output pins during soldering.
したがって、従来のような入出力ピンの曲折による障害
によって、半田付は後、パッケージを取り外して入出力
ピンの曲折を直して再度半田付けを行うことがなくなり
、パッドとの接合が確実となり、工数の削減および信頼
性の向上が図れ、実用的効果は大である。Therefore, there is no need to remove the package, correct the bends in the input/output pins, and resolder them after soldering due to problems caused by bending the input/output pins as in the past. The practical effects are significant, as the reduction in noise and the improvement in reliability can be achieved.
第１図は本箱１の発明の原理説明図。
第２図は本箱２の発明の原理説明図。
第３図は本箱１の発明による一実施例の説明図で、（ａ
）は側面図、 （ｂｉ ）（ｂ２）は製造工程図。
第４図は本箱２の発明にょる一実施例の説明図で、（ａ
）は側面図、（ｂ）は製造説明図。
第５図の（ａ）〜（４）は本発明の半田付は工程図。
第６図は（ａ）はパッケーシノ斜視図、 （ｂｌ、 ）
、 （ｂ２）は半田付けの工程図を示す。
図において、
■はパッケージ、 ２は入出力ピン。
３は配列面、 ４は保護層。
５は保護板、 ６は貫通穴を示す。
２人出力じン
本箱１の猜明の原理説明図
第１図
本箱２１）預明ＩＩ）原理説明図
第２図
１ ハ′、、ケーレ
（α）
（ｂ２）
本箱１の発明１：よ６−寅斃例の説ＦｉＡ図射３図
１ ハ゛、／Ｔ−シ′
／
（ａ）
（ｂ）
木屑２の発明にｊ５−支永１列の説明口哨４図
１ ハ′・・Ｊγ−シ′
＼
（ｂ）
（Ｃ）
本斧明の手Ｂｌｌ付は工程図
第５図FIG. 1 is an explanatory diagram of the principle of the invention of the bookcase 1. FIG. 2 is an explanatory diagram of the principle of the invention of the bookcase 2. FIG. 3 is an explanatory diagram of an embodiment according to the invention of bookcase 1, and (a
) is a side view, (bi) (b2) is a manufacturing process diagram. FIG. 4 is an explanatory diagram of an embodiment according to the invention of Bookcase 2.
) is a side view, and (b) is a manufacturing illustration. FIGS. 5(a) to 5(4) are process diagrams for soldering according to the present invention. In Figure 6, (a) is a perspective view of the package, (bl, )
, (b2) shows a soldering process diagram. In the figure, ■ is the package, and 2 is the input/output pin. 3 is the array surface, 4 is the protective layer. 5 indicates a protection plate, and 6 indicates a through hole. Figure 1: Explanatory diagram of the principle of the two-person production bookcase 1. Bookcase 21) Seimei II) Explanatory diagram of the principle: Figure 2. :Yo 6-Explanation of the example of death FiA Illustration 3 Figure 1 H, /T-C' / (a) (b) Invention of wood chips 2 j5-Shinaga 1 line explanation mouthpost 4 Figure 1 Ha'... Jγ-shi' ＼ (b) (C) The hand Bll of Akira Honshu is shown in Figure 5 of the process diagram.
Claims (1)
の配列面（３）に溶剤洗浄型樹脂材を塗布，硬化させる
ことで該入出力ピン（２）の配列ピッチ（Ｐ）を拘束す
るよう固定させる所定の厚み（Ｔ）の保護層（４）を該
配列面（３）に積層することを特徴とするパッケージ。 〔２〕入出力ピン（２）が配列されたパッケージ（１）
の配列面（３）に溶剤洗浄型樹脂材によって形成され、
該入出力ピン（２）の配列ピッチ（Ｐ）を拘束するよう
該入出力ピン（２）を固定する貫通穴（６）を備えた所
定の厚み（Ｔ）の保護板（５）を固着することを特徴と
するパッケージ。 〔３〕請求項１および請求項２記載の前記入出力ピン（
２）が実装すべき基板（１０）のパッド（１１）に半田
（１２Ａ）によって接合された後、前記保護層（４）ま
たは前記保護板（５）を溶剤によって溶解し、該保護層
（４）または該保護板（５）の除去を行うことを特徴と
するパッケージの半田付け方法。[Claims] [1] Package (1) in which input/output pins (2) are arranged
A protective layer (4) of a predetermined thickness (T) that is fixed to restrain the arrangement pitch (P) of the input/output pins (2) by coating and curing a solvent-cleanable resin material on the arrangement surface (3) of the input/output pins (2). is laminated on the arrangement surface (3). [2] Package (1) with input/output pins (2) arranged
is formed of a solvent-washable resin material on the array surface (3) of the
A protection plate (5) of a predetermined thickness (T) is fixed, which is provided with a through hole (6) for fixing the input/output pin (2) so as to restrict the arrangement pitch (P) of the input/output pin (2). A package characterized by: [3] The input/output pin according to claims 1 and 2 (
2) is bonded to the pad (11) of the board (10) to be mounted by solder (12A), the protective layer (4) or the protective plate (5) is dissolved with a solvent, and the protective layer (4) is bonded to the pad (11) of the board (10) to be mounted. ) or removing the protective plate (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33112590A JPH04199667A (en) | 1990-11-29 | 1990-11-29 | Package and its soldering method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33112590A JPH04199667A (en) | 1990-11-29 | 1990-11-29 | Package and its soldering method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04199667A true JPH04199667A (en) | 1992-07-20 |
Family
ID=18240153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33112590A Pending JPH04199667A (en) | 1990-11-29 | 1990-11-29 | Package and its soldering method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04199667A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020088366A (en) * | 2018-11-28 | 2020-06-04 | 宗哲 蔡 | Semiconductor package with in-package compartmental shielding and fabrication method thereof |
| US10896880B2 (en) | 2018-11-28 | 2021-01-19 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and fabrication method thereof |
| US10923435B2 (en) | 2018-11-28 | 2021-02-16 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and improved heat-dissipation performance |
| US11211340B2 (en) | 2018-11-28 | 2021-12-28 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding |
| US11239179B2 (en) | 2018-11-28 | 2022-02-01 | Shiann-Tsong Tsai | Semiconductor package and fabrication method thereof |
-
1990
- 1990-11-29 JP JP33112590A patent/JPH04199667A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020088366A (en) * | 2018-11-28 | 2020-06-04 | 宗哲 蔡 | Semiconductor package with in-package compartmental shielding and fabrication method thereof |
| US10847480B2 (en) | 2018-11-28 | 2020-11-24 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and fabrication method thereof |
| US10896880B2 (en) | 2018-11-28 | 2021-01-19 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and fabrication method thereof |
| US10923435B2 (en) | 2018-11-28 | 2021-02-16 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and improved heat-dissipation performance |
| US11211340B2 (en) | 2018-11-28 | 2021-12-28 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding |
| US11239179B2 (en) | 2018-11-28 | 2022-02-01 | Shiann-Tsong Tsai | Semiconductor package and fabrication method thereof |
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