JPH04188642A - Element mounting structure and method - Google Patents

Element mounting structure and method

Info

Publication number
JPH04188642A
JPH04188642A JP2311437A JP31143790A JPH04188642A JP H04188642 A JPH04188642 A JP H04188642A JP 2311437 A JP2311437 A JP 2311437A JP 31143790 A JP31143790 A JP 31143790A JP H04188642 A JPH04188642 A JP H04188642A
Authority
JP
Japan
Prior art keywords
pattern
resin
substrate
mounting
bare chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2311437A
Other languages
Japanese (ja)
Inventor
Masanao Fujii
昌直 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2311437A priority Critical patent/JPH04188642A/en
Publication of JPH04188642A publication Critical patent/JPH04188642A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To simplify the mounting step of elements for enabling the high density mounting method to be applied by a method wherein the title element mounting structure is provided with a resin layer coated on the first pattern and the element leaving the parts wherein the pattern and the elements are electrically connected. CONSTITUTION:A bare chip 32 and the first pattern 31 bonded onto a substrate 30 are coated with a resin 34. Next, the second pattern 37 is formed on the surface of the resin 34 and vias 36 so as to make respective wiring of the first pattern 31 and the bare chip 32. Thus, the bare chip 32 sealed with the resin 34 can be prevented from corroding, etc. Through these procedures, the electric connection can be effected by the second pattern 37 so as to eliminate the specific step besides, due to the three-dimentional mounting structure of the bare chip 32 and an LSI 39, the high density mounting method can be applied.

Description

【発明の詳細な説明】[Detailed description of the invention]

ｔｍ要】 素子実装構造およびその実装方法に係り、特に近年の高
密度実装に適用できる素子実装構造およびその実装方法
に関し、 基板上に実装される素子の実装工程を簡素化し、また高
密度実装にも優れたものを提供することを目的とし、 第１のパターンが施された基板上に、バンプが形成され
た面を当該基板と反する面に配置した状態で搭載される
素子と、該第１のパターンおよび該素子の電気接続を行
なう部分のみを残し、当該第１のパターンおよび当該素
子上に塗布される樹脂層と、該樹脂層の表面に形成され
、該第１のパターンまたは該素子の配線を行なう第２の
パターンとを有するよう構成する。tm Required] Regarding element mounting structures and mounting methods, especially those that can be applied to recent high-density mounting, this article simplifies the mounting process of elements mounted on a board and is suitable for high-density mounting. The present invention aims to provide an element which is mounted on a substrate on which a first pattern is formed, with the surface on which the bumps are formed being placed on the opposite side of the substrate, and the first pattern. Leaving only the pattern and the part for electrical connection of the element, the resin layer applied on the first pattern and the element, and the part formed on the surface of the resin layer of the first pattern or the element. and a second pattern for wiring.

【産業上の利用分野】[Industrial application field]

本発明は、素子実装構造およびその実装方法に係り、特
に近年の高密度実装に適用できる素子実装構造およびそ
の実装方法に関するものである。 τ従来の技術】 従来上記高密度実装を行なう方法としては以下のような
ものがあった。 つまり、ＴＡＢと呼ばれるものは第５図（ａ）に示すよ
うに、基板上にテープを形成し、そのテープ上に素子を
実装し、リードをボンディングするものである。 またＣＯＢと呼ばれるものは第５図（ｂ）に示すように
、基板上に素子を搭載し、基板上のバ・ラドとをワイヤ
にて接続し、素子とワイヤおよびノぐラドとを封止剤に
よって封止して実装するものである。The present invention relates to an element mounting structure and its mounting method, and more particularly to an element mounting structure and its mounting method that can be applied to recent high-density mounting. [Background Art] Conventionally, the following methods have been used to perform the above-mentioned high-density packaging. That is, as shown in FIG. 5(a), what is called TAB is a method in which a tape is formed on a substrate, elements are mounted on the tape, and leads are bonded. In addition, as shown in Figure 5(b), what is called a COB has an element mounted on a substrate, a wire connected to the board on the board, and a seal between the element, the wire, and the board. The device is sealed and mounted using an adhesive.

【発明が解決しようとする課Ｂ】[Problem B that the invention attempts to solve]

しかしながらＴＡＢ実装方法では素子を搭載したテープ
に形成されているリードが長く、素子の大きさに比して
実装面積が太き（なってしまい、またＣＯＥ実装方法で
は素子搭載後ワイヤでボンディングしこれを樹脂で封止
しなければならず、封止剤の選定、コスト基板の反り等
に問題があった。 従って、本発明は基板上に実装される素子の実装工程を
簡素化し、また高密度実装にも優れたものを提供するこ
とを目的とするものである。 ［ｍ題を解決するための手段］ 上記目的は、第１のパターン５が施された基板１上に、
バンプ４が形成された面を当該基板１と反する面に配置
した状態で搭載される素子２と、該第１のパターン５お
よび該素子２の電気接続を行なう部分のみを残し、当該
第１のパターン５および当該素子２上に塗布される樹脂
層３と、該樹脂層３の表面に形成され、該第１のパター
ン５または該素子２の配線を行なう第２のパターン６と
、 を有することを特徴とする素子実装構造によって達成す
ることができる。However, in the TAB mounting method, the leads formed on the tape on which the device is mounted are long, and the mounting area is large (compared to the size of the device). must be sealed with a resin, which poses problems such as selection of sealant, cost, and warpage of the board.Therefore, the present invention simplifies the mounting process of elements mounted on the board, and also enables high-density The purpose is to provide a device that is excellent in mounting. [Means for solving problem m]
The element 2 is mounted with the surface on which the bumps 4 are formed on the opposite side to the substrate 1, and the first pattern 5 and the element 2 are mounted, leaving only the part for electrical connection between the first pattern 5 and the element 2. A resin layer 3 coated on the pattern 5 and the element 2; and a second pattern 6 formed on the surface of the resin layer 3 and used for wiring the first pattern 5 or the element 2. This can be achieved by an element mounting structure characterized by the following.

【作用】[Effect]

即ち、本発明においては、素子を基板に実装する際にパ
ターンを用いて且つその素子を樹脂剤によって封止する
こととなるから、必要最小限に接続領域を確保すること
ができる。That is, in the present invention, when an element is mounted on a substrate, a pattern is used and the element is sealed with a resin, so that the minimum necessary connection area can be secured.

【実施例】【Example】

以下、本発明の望ましい実施例を第２図および第３図を
用いて詳細に説明する。 第３図は、本発明の実施例を示す図であり、第４図は、
ペアチップのバンプに対する前処理を示す図である。 第３回および第４図において、３０は基板。 ３１は第１のパターン、３２はペアチップ、３３は緩衝
材、３４は耐熱性樹脂、３５はメタルマスク、３６ばビ
ア、３７は第２のパターン、３８はパッド、３９はＬＳ
Ｉ、４０はリー１４１は半田、４２ばバンプ、４３は導
電性ペースト４４および４４′は治具、４５は銅粉末を
それぞれ示す。 尚、第３図および第４図において同一符号を付したもの
は同一対象物をそれぞれ示す。 まず、第３図に示すように、ペアチップの前処理として
、ペアチップ３２に形成された金バンプ４２に、別途治
具４４の表面に塗布された導電性ペースト４３を塗布さ
せる（第４図（ａ））。 その後、バンプ４２の表面に塗布された導電性ペースト
４３の表面に、異なる治具４４゛の表面に塗布された銅
粉末４５を塗布する（第４図（ｂ））。 すると第４図（Ｃ）に示すように、ペアチップ３２のバ
ンプ４２が緩衝材３３が形成される。 上記のように構成された緩衝材３３を存するペアチップ
３２を基板３０上に実装する工程について説明すると、
第３図（ａ）に示すように、予め公知の方法によってパ
ターンニングされた第１のパターン３１を有する基板の
所定の位置に緩衝材３３を有する面を基板３０の表面と
は反するように（緩衝材３３を上にした状態）配置し、
接着剤で固着する。 第３図（ｂ）に示すように、この基板３０上に固着され
たペアチップ３２および第１のパターン３１に対して即
ち基板３０全体に耐熱性に優れた樹脂３４、例えばポリ
イミドまたはエポキシ系の樹脂を所定の厚みをもって塗
布する。この状態では第１のパターン３１およびペアチ
ップ３２は完全に樹脂剤３４によって隠れた状態となっ
ている。 第３図（Ｃ）に示すように、耐熱性の樹脂３４０表面に
銅等のメタルマスク３５を形成する。このメタルマスク
３５を形成する部分は、後述説明するが、層間接続用の
ビア３６を形成する部分はそのマスクを行わない。 第３図（ｄ、）に示すように、所定の部分にメタルマス
ク３５が施された樹脂表面に対して、レーザ光等の照射
を行ってビアを形成する。この時、バンプ４２の表面に
は銅粉末４５を塗布しているので、レーザ光を拡散し、
更に発生した熱は導電性ペースト４３が蒸発することで
吸収し、ベアチップ３２自体に熱等の悪影響を与えない
。尚、銅粉末４５および導電性ペースト４３は元々導電
性を有しているので導通不良を起こすことばない。 その後、第３図（ｅ）に示すように、樹脂３４の表面お
よびビア３６に対して公知のパターンニング方法を用い
て第２のパターン３７を形成することで、第１のパター
ン３１およびペアチップ３２の各々の配線が行われる。 この状態ではペアチップ３２が樹脂剤３４によって封止
され、且つ第２のパターン３７によって所望の配線を行
なうことができるため、配線に関しては必要最小限の実
装領域とすることができる。 第３図（ｆ）に示すように、第２のパターン３７を形成
する時に樹脂３４の表面にバンド３８を形成し、このバ
ッド３８に対して位置合わせしたＬＳＩ３９を搭載する
。ＬＳＩ３９のリード４０とバッド３８とば半ＥＥ？４
１によって電気的・機械的に接合されている。 以上説明したように本実施例においては、ペアチップ３
２は樹脂剤３４によって封止されることで腐食等が発生
しないことば勿論のこと、電気的接続を行なうのは第２
のパターン３７によって行われることから、特殊な工程
を要することがない。 また、ペアチップ３２とＬＳＩ３９とを立体的な実装構
造としているため、高密度実装もを行なうことができる
。Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3. FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 4 is a diagram showing an embodiment of the present invention.
FIG. 7 is a diagram showing preprocessing for bumps on paired chips. In the third issue and FIG. 4, 30 is a substrate. 31 is a first pattern, 32 is a pair chip, 33 is a buffer material, 34 is a heat-resistant resin, 35 is a metal mask, 36 is a via, 37 is a second pattern, 38 is a pad, 39 is an LS
Reference numerals I and 40 denote solder, 42 a bump, 43 a conductive paste 44 and 44' a jig, and 45 a copper powder, respectively. Note that in FIGS. 3 and 4, the same reference numerals indicate the same objects, respectively. First, as shown in FIG. 3, as a pretreatment of the paired chips, the gold bumps 42 formed on the paired chips 32 are coated with a conductive paste 43 that is separately applied to the surface of a jig 44 (FIG. 4(a) )). Thereafter, the copper powder 45 applied to the surface of a different jig 44' is applied to the surface of the conductive paste 43 applied to the surface of the bump 42 (FIG. 4(b)). Then, as shown in FIG. 4(C), the bumps 42 of the paired chips 32 form the cushioning material 33. The process of mounting the pair chip 32 having the buffer material 33 configured as described above on the substrate 30 will be explained as follows.
As shown in FIG. 3(a), the surface having the cushioning material 33 at a predetermined position of the substrate having the first pattern 31 patterned in advance by a known method is placed opposite to the surface of the substrate 30 ( with the cushioning material 33 facing up),
Secure with adhesive. As shown in FIG. 3(b), a resin 34 having excellent heat resistance, such as polyimide or epoxy resin, is applied to the pair chips 32 and the first pattern 31 fixed on the substrate 30, that is, the entire substrate 30. Apply to a specified thickness. In this state, the first pattern 31 and the paired chips 32 are completely hidden by the resin agent 34. As shown in FIG. 3(C), a metal mask 35 made of copper or the like is formed on the surface of the heat-resistant resin 340. The portion where the metal mask 35 is to be formed will be explained later, but the portion where the via 36 for interlayer connection is to be formed is not masked. As shown in FIG. 3(d), vias are formed by irradiating the resin surface with a metal mask 35 on predetermined portions by irradiating laser light or the like. At this time, since the surface of the bump 42 is coated with copper powder 45, the laser beam is diffused.
Furthermore, the generated heat is absorbed by evaporation of the conductive paste 43, and does not have any adverse effects such as heat on the bare chip 32 itself. Incidentally, since the copper powder 45 and the conductive paste 43 are inherently conductive, no conduction failure occurs. Thereafter, as shown in FIG. 3(e), a second pattern 37 is formed on the surface of the resin 34 and the vias 36 using a known patterning method, thereby forming the first pattern 31 and the paired chips 32. Each wiring is performed. In this state, the paired chips 32 are sealed with the resin 34, and desired wiring can be performed using the second pattern 37, so that the mounting area for wiring can be kept to the minimum necessary. As shown in FIG. 3(f), when forming the second pattern 37, a band 38 is formed on the surface of the resin 34, and an LSI 39 aligned with this band 38 is mounted. LSI39 lead 40 and bad 38 and half EE? 4
1 electrically and mechanically connected. As explained above, in this embodiment, the pair chip 3
2 is sealed with a resin material 34 to prevent corrosion, etc., and the electrical connection is made using the second
Since this is performed using the pattern 37, no special process is required. Further, since the pair chip 32 and the LSI 39 have a three-dimensional mounting structure, high-density mounting can be performed.

【発明の効果】 以上説明したように本発明においては、ボンディング・
半田付は等の接続工程が不要となる為、基板上に実装さ
れる素子の実装工程を簡素化し、また高密度実装にも優
れる効果を有する。[Effect of the invention] As explained above, in the present invention, bonding
Since connection processes such as soldering are not required, the mounting process of elements mounted on the board is simplified, and it also has an excellent effect on high-density mounting.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の原理図であり、 第２図は、本発明の実装工程を示す図であり、第３図は
、本発明の実施例を示す図であり、第４図は、ペアチッ
プのバンプに対する前処理を示す図であり、 第５図は、従来例を示す図であり、 同図（ａ）は、ＴＡＢ実装を示し、 同図（ｂ）は、ＣＯＢ実装を示す図である。 図において、 １・・・基板。 ２・・・素子。 ３・・・樹脂層。 ４・・・バンプ。 ５・・・第１のパターン。 ６・・・第２のパターン。 をそれぞれ示す。FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a mounting process of the present invention, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 5 is a diagram showing preprocessing for bumps on paired chips; FIG. 5 is a diagram showing a conventional example; FIG. 5(a) shows TAB mounting; and FIG. 5(b) shows COB mounting. be. In the figure: 1...Substrate. 2...Motoko. 3...Resin layer. 4...Bump. 5...First pattern. 6...Second pattern. are shown respectively.

Claims (2)

【特許請求の範囲】[Claims] （１）第１のパターン（５）が施された基板（１）上に
、バンプ（４）が形成された面を当該基板（１）と反す
る面に配置した状態で搭載される素子（２）と、 該第１のパターン（５）および該素子（２）の電気接続
を行なう部分のみを残し、当該第１のパターン（５）お
よび当該素子（２）上に塗布される樹脂層（３）と、 該樹脂層（３）の表面に形成され、該第１のパターン（
５）または該素子（２）の配線を行なう第２のパターン
（６）と、 を有することを特徴とする素子実装構造。(1) The element (2) is mounted on the substrate (1) on which the first pattern (5) is formed, with the surface on which the bumps (4) are formed on the opposite surface from the substrate (1). ), and a resin layer (3) coated on the first pattern (5) and the element (2), leaving only the part for electrical connection of the first pattern (5) and the element (2). ), formed on the surface of the resin layer (3), and the first pattern (
5) or a second pattern (6) for wiring the element (2); （２）イ）基板（１）上に第１のパターン（５）を形成
する工程と、 ロ）該第１のパターン（５）が形成された該基板（１）
上に、バンプ（４）が形成されたを該基板（１）と反す
る面に位置するように配置した状態で素子（２）を搭載
する工程と、 ハ）該第１のパターン（５）および該素子（２）上に樹
脂層（３）を形成する工程と、 ニ）該樹脂層（３）の非ビア形成位置にメタルマスクを
行なう工程と、 ホ）該樹脂層（３）をエッチングする工程と、ヘ）該エ
ッチングされた位置に、第２のパターンを形成する工程
と、 を有することを特徴とする素子実装方法。(2) A) A step of forming a first pattern (5) on the substrate (1), and (b) the substrate (1) on which the first pattern (5) is formed.
a step of mounting the element (2) on the substrate (1) with the bump (4) formed thereon positioned on the opposite side of the substrate (1); c) the first pattern (5); and forming a resin layer (3) on the element (2); d) applying a metal mask to non-via forming positions of the resin layer (3); and e) etching the resin layer (3). and f) forming a second pattern at the etched position.
JP2311437A 1990-11-19 1990-11-19 Element mounting structure and method Pending JPH04188642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2311437A JPH04188642A (en) 1990-11-19 1990-11-19 Element mounting structure and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2311437A JPH04188642A (en) 1990-11-19 1990-11-19 Element mounting structure and method

Publications (1)

Publication Number Publication Date
JPH04188642A true JPH04188642A (en) 1992-07-07

Family

ID=18017206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2311437A Pending JPH04188642A (en) 1990-11-19 1990-11-19 Element mounting structure and method

Country Status (1)

Country Link
JP (1) JPH04188642A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037338A2 (en) * 1999-11-16 2001-05-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Method for integrating a chip in a printed board and integrated circuit
JP2006514785A (en) * 2003-02-28 2006-05-11 シーメンス　アクチエンゲゼルシヤフト Connection technology for power semiconductors

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037338A2 (en) * 1999-11-16 2001-05-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Method for integrating a chip in a printed board and integrated circuit
WO2001037338A3 (en) * 1999-11-16 2001-12-27 Fraunhofer Ges Forschung Method for integrating a chip in a printed board and integrated circuit
JP2006514785A (en) * 2003-02-28 2006-05-11 シーメンス　アクチエンゲゼルシヤフト Connection technology for power semiconductors
US7855451B2 (en) 2003-02-28 2010-12-21 Siemens Aktiengesellschaft Device having a contacting structure
JP4763463B2 (en) * 2003-02-28 2011-08-31 シーメンス アクチエンゲゼルシヤフト Apparatus comprising substrate and power electronics element and method for manufacturing the same

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