JPH04167709A - 表面波素子のワイヤボンデイング方法 - Google Patents

表面波素子のワイヤボンデイング方法

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Publication number
JPH04167709A
JPH04167709A JP2293812A JP29381290A JPH04167709A JP H04167709 A JPH04167709 A JP H04167709A JP 2293812 A JP2293812 A JP 2293812A JP 29381290 A JP29381290 A JP 29381290A JP H04167709 A JPH04167709 A JP H04167709A
Authority
JP
Japan
Prior art keywords
wire
interdigital electrode
wave element
bonding
surface wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2293812A
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English (en)
Inventor
Yukio Murata
村田 幸男
Kayo Matsumoto
圭代 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2293812A priority Critical patent/JPH04167709A/ja
Publication of JPH04167709A publication Critical patent/JPH04167709A/ja
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
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    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明1x、表面波素子にワイヤボンディングにより
ワイヤを接合する方法に関するものである0〔従来の技
術〕 第4図は一般的な表面波素子を示T図であり、図におい
て、1は表面波素子用結晶基板、2は丁だれ状電極3に
接続されているワイヤである。4aは入力側リード、4
t)GZ出力側リードで1外部への接続はこれらの端子
により行われる。上記ワイヤ2は、ウェッジワイヤボン
ディング装置にてすだれ状電極3に接続される。ウェッ
ジワイヤボンディングは、ワイヤに超音波を印加し7て
接合を行うものである。
次に動作について説明する。表面波素子への電気信号は
入力側リード仏間に加えられる。この電気信号は、ワイ
ヤ2を通ってすだれ状電極3に印加される。この′wL
気信号はすだれ状電極3において表面波に変換され、結
晶基板1の上を伝搬して、出力側の丁だれ状電極3に伝
わり、ワイヤ2を通って出力側リード4bに出力される
〔発明が解決しようとする課題〕
従来の表面波素子は以上のように構成されているので、
ウェッジワイヤボンディングの超音波により、ワイヤと
結晶基板上のすだれ状電極を接合Tるための安定条件が
狭く、ひどい場合、すだれ状電極かにがれを発生したり
、基板が割れるなどの問題点があった。
本発明はこのような問題点を解消するためになされたも
ので、ワイヤと電極の接続Ti:安定して行い得るワイ
ヤボンディング方法を提供しようとするものである。
〔課題を解決するための手段〕
本発明に係る表面波素子のワイヤボンデイング方法は、
ワイヤとすだれ状電極を超音波併用熱圧着ポールボンデ
ィングを用いて接続する際Gこ、表面波素子用結晶基板
の結晶軸と超音波の印加方向を90度ずらせたものであ
る。
〔作用〕
本発明における表面波素子のワイヤボンデイング方法は
、ワイヤ圧着時の衝撃を軽減し、すだれ状電極のはがれ
や基板のひび割れを防止する。
〔実施例〕
以下この発明の一実施例を図について説明する。
第1肉はこの発明を実施した表面波素子の要部拡大図で
ある。丁だれ状電極3は結晶基板1の表面に形成されて
いる。すだれ状電極3は、動作周波数、基板の材質、下
地への付着力などを考慮してアルミニウムが広く用いら
れ、数千オングストロームの膜厚である。結晶基板1は
水晶やL iN b Os、LiTa()+ 、 Bi
GθO1などが使用きれている。特にLiNbO5など
は、機械的衝撃に弱く、割れたり、欠けたすしや丁い。
ワイヤ2の材質は、ウェッジワイヤボンディングではア
ルミニウムか一般的に使用されている。
ウェッジワイヤボンディングにてワイヤ2をすだれ状の
電極3の薄い膜の上に接合する場合、第2図イに示すよ
うに、ワイヤ2の先端がつぶれ、本来の太さより減少す
る。この程度のつぶれは1通常の基板には影響ないが、
表面波素子Oこ使用される結晶基板では、つぶれるとき
の機械的衝撃力により・結晶基板1が割れたり、すだれ
状電極3がはがれたりして信頼性のある接続ができない
本発明では、結晶基板3に加わる機械的衝撃を弱め/l
)ため、超音波併用ポールボンディングによるボール側
を選んだもので、そσ〕接合状態を第2図口に断面で示
している。ワイヤボールの直径は、ワイヤの数倍あるた
め、結晶基板1や丁だれ状電極3に与える機械的衝撃が
少なくなり、良好に接続される。
しかしながら、実際にワイヤボンディングを行ってみる
と、第2図へに示すように、結晶基板1にひびが入る不
良が発生した。この原因は結晶基板1の結晶軸とワイヤ
ボンディングを行うときの超音波の印加方向に関係があ
り、これが不適切な場合に不良が発生することが判明し
た。
第8図はワイヤボンディングの超音波印加方向と結晶基
板の結晶軸間の角度を横軸にとり、不良発生率を縦軸に
とってグラフ化したものである。
これにより、結晶軸と超音波印加方向が90度の場合に
不良発生率が低く、良好な接合がされることがわかる。
そこで、本発明では、結晶基板3に加わる機械的衝撃を
弱めるため、超音波併用ポールボンディングによるボー
ル側を選ぶと同時に、超音波の印加方向を、結晶基板1
の結晶軸方向に対して90度ずらすことにより、信頼性
の高い表面波素子を得ようとするものである。
〔発明の効果〕
以上のように本発明によれは、表面波素子の製作Gこお
いて不良発生率をきわめて低く抑えることができる。
【図面の簡単な説明】
第1図は本発明を実施した表向波素子の要部を示す斜視
図、第2図イ、口、ハにワイヤボンディングの態様を示
す断面図、第8図は本発明の詳細な説明するための図、
第4図は一般的な表面波素子を示す斜視図である。 図中・ 1は結晶基板、2はワイヤ・ 3はすだれ状電
極である。 なお肉中同−勾号は同一または相当部分を示す。

Claims (1)

    【特許請求の範囲】
  1. 表面波素子用結晶基板上に形成されたすだれ状電極にワ
    イヤを超音波併用熱圧着ボールボンディングを用いて接
    続する際に、ボール側をすだれ状電極に接合すると共に
    、表面波素子用結晶基板の結晶軸と超音波の印加方向を
    90度ずらせたことを特徴とする表面波素子のワイヤボ
    ンデイング方法。
JP2293812A 1990-10-30 1990-10-30 表面波素子のワイヤボンデイング方法 Pending JPH04167709A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2293812A JPH04167709A (ja) 1990-10-30 1990-10-30 表面波素子のワイヤボンデイング方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2293812A JPH04167709A (ja) 1990-10-30 1990-10-30 表面波素子のワイヤボンデイング方法

Publications (1)

Publication Number Publication Date
JPH04167709A true JPH04167709A (ja) 1992-06-15

Family

ID=17799471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2293812A Pending JPH04167709A (ja) 1990-10-30 1990-10-30 表面波素子のワイヤボンデイング方法

Country Status (1)

Country Link
JP (1) JPH04167709A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053130A (ja) * 2005-08-15 2007-03-01 Matsushita Electric Ind Co Ltd 接合構造および接合方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053130A (ja) * 2005-08-15 2007-03-01 Matsushita Electric Ind Co Ltd 接合構造および接合方法
US8012869B2 (en) 2005-08-15 2011-09-06 Panasonic Corporation Bonded structure and bonding method

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