JPH0349215B2 - - Google Patents
Info
- Publication number
- JPH0349215B2 JPH0349215B2 JP59208791A JP20879184A JPH0349215B2 JP H0349215 B2 JPH0349215 B2 JP H0349215B2 JP 59208791 A JP59208791 A JP 59208791A JP 20879184 A JP20879184 A JP 20879184A JP H0349215 B2 JPH0349215 B2 JP H0349215B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- frequency
- signal
- phase
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003252 repetitive effect Effects 0.000 claims description 15
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 230000010355 oscillation Effects 0.000 claims description 5
- 238000004804 winding Methods 0.000 description 10
- 239000000700 radioactive tracer Substances 0.000 description 9
- 238000005259 measurement Methods 0.000 description 7
- 238000001514 detection method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は基準周波数に同期した繰返し電圧を発
生する回路であり、カーブ・トレーサの如き半導
体特性測定装置において、外部電源周波数（基準
周波数）と同相の繰返し電圧である可変コレクタ
電圧を発生する回路に利用できる。[Detailed Description of the Invention] [Industrial Application Field] The present invention is a circuit that generates a repetitive voltage synchronized with a reference frequency, and is used in a semiconductor characteristic measuring device such as a curve tracer to generate a repetitive voltage that is synchronized with an external power supply frequency (reference frequency). It can be used in a circuit that generates a variable collector voltage that is a repeating voltage of the same mode.
半導体特性測定装置、特にカーブ・トレーサ
は、トランジスタやダイオード等の基本的な半導
体素子を測定するのに有効な装置である。従来の
カーブ・トレーサは第３図に示す如き構成となつ
ている。即ち、コレクタ電圧供給回路１０からの
正弦波電圧を変圧器１２の１次巻線に供給する。
この変圧器１２の２次巻線は複数のタツプを有
し、選択整流回路１４が測定レンジに応じてこれ
らタツプの１つを選択し、選択されたタツプから
の正弦波電圧を整流する。選択整流回路１４から
の整流された電圧は、リミツタ用抵抗器１６を介
して被測定トランジスタ１８のコレクタに供給す
る。なお、抵抗器１６の値は測定レンジに応じて
切替える。変圧器１２の２次巻線の下端は、電流
検出用抵抗器２０を介して被測定トランジスタ１
８のエミツタに接続すると共に接地する。また、
トランジスタ１８のベースには、ステツプ状に変
化するバイアス信号をバイアス供給回路２２から
供給する。なお、第３図では被測定トランジスタ
１８がエミツタ接地形式でカーブ・トレーサに接
続されているが、ベース接地形式又はコレクタ接
地形式でもよい。電圧検出回路２４は被測定トラ
ンジスタ１８のコレクタ及びエミツタ間の電圧
VCEを検出し、適当に分圧した後、増幅器２６を
介して表示器である陰極線管（CRT）２８の水
平偏向板に供給する。電圧検出回路３０は抵抗器
２０の両端の電圧差、即ち被測定トランジスタ１
８のコレクタ電流ICを検出し、増幅器３２を介し
てCRT２８の垂直偏向板に供給する。よつて、
CRT２８にトランジスタ１８のVCE−IC特性を表
示することができる。
Semiconductor characteristic measuring devices, particularly curve tracers, are effective devices for measuring basic semiconductor devices such as transistors and diodes. A conventional curve tracer has a configuration as shown in FIG. That is, the sine wave voltage from the collector voltage supply circuit 10 is supplied to the primary winding of the transformer 12.
The secondary winding of this transformer 12 has a plurality of taps, and a selective rectifier circuit 14 selects one of these taps depending on the measurement range and rectifies the sinusoidal voltage from the selected tap. The rectified voltage from the selective rectifier circuit 14 is supplied to the collector of the transistor under test 18 via a limiter resistor 16. Note that the value of the resistor 16 is changed depending on the measurement range. The lower end of the secondary winding of the transformer 12 is connected to the transistor under test 1 via a current detection resistor 20.
Connect to the emitter of No. 8 and ground. Also,
A bias signal varying in steps is supplied to the base of the transistor 18 from a bias supply circuit 22. In FIG. 3, the transistor to be measured 18 is connected to the curve tracer in a grounded emitter type, but it may be connected in a grounded base type or a grounded collector type. The voltage detection circuit 24 detects the voltage between the collector and emitter of the transistor under test 18.
After V CE is detected and appropriately divided, it is supplied via an amplifier 26 to a horizontal deflection plate of a cathode ray tube (CRT) 28 which is a display. The voltage detection circuit 30 detects the voltage difference across the resistor 20, that is, the transistor under test 1.
8 is detected and supplied to the vertical deflection plate of the CRT 28 via the amplifier 32. Then,
The V CE -I C characteristics of the transistor 18 can be displayed on the CRT 28.
ところで、繰返し電圧を発生するコレクタ電圧
供給回路１０は、第４図に示すように従来は構成
されていた。即ち、外部電源である商用電源から
の正弦波電圧はスイツチ３４を介して電源回路３
６及び可変変圧器３８に供給する。電源回路３６
は、種々の安定化された直流電圧を各回路に供給
するためのものである。また、可変変圧器３８は
電源電圧を可変して、第３図の変圧器１２の１次
巻線に供給する。よつて、変圧器１２の２次巻線
からは外部電源周波数と同相で、振幅が可変変圧
器３８で制御された繰返し正弦波電圧が得られ
る。 By the way, the collector voltage supply circuit 10 that generates a repetitive voltage has conventionally been configured as shown in FIG. That is, the sine wave voltage from the commercial power source, which is an external power source, is applied to the power supply circuit 3 via the switch 34.
6 and variable transformer 38. Power supply circuit 36
is for supplying various stabilized DC voltages to each circuit. Further, the variable transformer 38 varies the power supply voltage and supplies it to the primary winding of the transformer 12 shown in FIG. Therefore, a repetitive sine wave voltage whose amplitude is controlled by the variable transformer 38 is obtained from the secondary winding of the transformer 12 in phase with the external power supply frequency.
ところで、第４図に示した従来の繰返し電圧発
生回路には種々の問題点がある。まず、商用電源
の波形は完全な正弦波ではなく、種々の歪を含ん
でいる。よつて、カーブ・トレーサにおいて、被
測定トランジスタに供給される繰返し電圧波形も
完全な正弦波でないため、CRT２８に表示され
る特性曲線の行き（整流された正弦波電圧の上昇
期間）のトレースと戻り（整流された正弦波電圧
の下降期間）のトレースとが異なり、正確に被測
定トランジスタの特性が測定できない。この現象
を便宜的に表示歪と呼ぶ。また商用電源電圧の振
幅は正確ではなく、ある一定の幅で変化するた
め、被測定トランジスタに供給される繰返し電圧
の振幅も商用電源に応じて変化し、正確な特性測
定が困難になる。更に、第３図のカーブ・トレー
サにデジタル・ストレージ回路を適用した場合、
即ち、電源検出回路２４及び増幅器２６の間、並
びに電源検出回路３０及び増幅器３２の間にＡ／
Ｄ変換器、デジタル・メモリ及びＤ／Ａ変換器の
組合せを接続した場合、Ａ／Ｄ変換器のクロツク
周波数が商用電源周波数と独立なので、Ａ／Ｄ変
換器の出力に電源のリツプルの影響が現われ、測
定精度が低下する。仮え、Ａ／Ｄ変換器のクロツ
ク周波数を商用電源周波数に同期させるには、専
用の位相制御回路が必要となり、カーブ・トレー
サが高価となる。
By the way, the conventional repetitive voltage generating circuit shown in FIG. 4 has various problems. First, the waveform of commercial power is not a perfect sine wave, but contains various distortions. Therefore, in a curve tracer, the repetitive voltage waveform supplied to the transistor under test is not a perfect sine wave, so the trace of the characteristic curve displayed on the CRT 28 (the rising period of the rectified sine wave voltage) and the return. (during the falling period of the rectified sinusoidal voltage), the characteristics of the transistor under test cannot be accurately measured. This phenomenon is conveniently called display distortion. Furthermore, since the amplitude of the commercial power supply voltage is not accurate and changes within a certain range, the amplitude of the repetitive voltage supplied to the transistor under test also changes depending on the commercial power supply, making accurate characteristic measurement difficult. Furthermore, when a digital storage circuit is applied to the curve tracer in Figure 3,
That is, A/D is connected between the power supply detection circuit 24 and the amplifier 26, and between the power supply detection circuit 30 and the amplifier 32.
When a combination of a D converter, digital memory, and D/A converter is connected, the clock frequency of the A/D converter is independent of the commercial power supply frequency, so the output of the A/D converter is not affected by ripples in the power supply. appears, reducing measurement accuracy. However, in order to synchronize the clock frequency of the A/D converter with the commercial power supply frequency, a dedicated phase control circuit would be required, making the curve tracer expensive.
本発明は可変周波数信号発生器５０と、この可
変周波数信号発生器の出力信号を分周して複数の
分周出力信号を発生する分周器５２と、この分周
器の所定の分周出力信号の位相と電源周波数信号
である基準周波数信号の位相とを比較して、可変
周波数信号発生器の発振周波数を制御する位相比
較器４８と、分周器の分周出力信号に応じて入力
電圧を正弦波等の所望波形に変換するため、ゲー
ト回路５４〜６０、アナログ・マルチプレクサ６
２及び１０６、複数の抵抗器６４〜７８及び積分
器８０〜８２で構成された変換手段と、この変換
手段の出力電圧に応じた電圧と基準電圧VREFとを
比較して変換手段の入力電圧を発生する電圧比較
器とを具えている。
The present invention includes a variable frequency signal generator 50, a frequency divider 52 that divides the output signal of the variable frequency signal generator to generate a plurality of divided output signals, and a predetermined divided output signal of the frequency divider. A phase comparator 48 controls the oscillation frequency of the variable frequency signal generator by comparing the phase of the signal with the phase of a reference frequency signal which is a power supply frequency signal, and a phase comparator 48 controls the oscillation frequency of the variable frequency signal generator. In order to convert the signal into a desired waveform such as a sine wave, gate circuits 54 to 60 and an analog multiplexer 6 are used.
2 and 106, a plurality of resistors 64 to 78, and integrators 80 to 82, and a voltage corresponding to the output voltage of this conversion means is compared with a reference voltage V REF to determine the input voltage of the conversion means. It is equipped with a voltage comparator that generates.
本発明によれば、可変周波数信号発生器、分周
器及び位相比較器により位相ロツク・ループを形
成しており、分周器の複数の分周出力信号は電源
周波数に同期している。これら分周出力信号に応
じて変換手段により正弦波等の所望波形の電圧を
発生しているので、被測定トランジスタに供給さ
れる正弦波電圧の歪は非常に少なく上述の表示歪
の問題が生じない。また電源電圧及び周波数の変
動にかかわらず、電圧比較器により変換手段が発
生する正弦波繰返し電圧の振幅を基準電圧に応じ
た一定電圧に保つているので、被測定トランジス
タの特性を正確に測定できる。更に可変周波数信
号発生器及び分周器の出力信号は電源周波数に同
期しており、正弦波繰返し電圧を発生する変換手
段以外に、他の種々の回路、例えばＡ／Ｄ変換器
のクロツク信号にも兼用できる。
According to the present invention, a variable frequency signal generator, a frequency divider and a phase comparator form a phase lock loop, and the plurality of divided output signals of the frequency divider are synchronized to the power supply frequency. Since a voltage with a desired waveform such as a sine wave is generated by the conversion means according to these frequency-divided output signals, the distortion of the sine wave voltage supplied to the transistor under test is very small, and the above-mentioned display distortion problem occurs. do not have. In addition, regardless of fluctuations in power supply voltage and frequency, the voltage comparator keeps the amplitude of the sine wave repetitive voltage generated by the conversion means at a constant voltage according to the reference voltage, allowing accurate measurement of the characteristics of the transistor under test. . Furthermore, the output signals of the variable frequency signal generator and frequency divider are synchronized with the power supply frequency, and can be applied to various other circuits, such as the clock signal of an A/D converter, in addition to the conversion means that generates the sinusoidal repetitive voltage. Can also be used.
以下、添付図を参照して本発明の好適な実施例
を説明する。なお、この実施例では所望波形が正
弦波である。第１図は本発明の繰返し電圧発生回
路を含んだカーブ・トレーサの一部を示すブロツ
ク図である。外部の商用電源からの交流電圧は電
源スイツチ３４を介して電源回路３６内の変圧器
４０の１次巻線に供給する。変圧器４０の複数の
２次巻線を電源回路３６内の直流電圧安定化回路
（図示せず）に接続して、各回路用の直流電圧を
発生させる。変圧器４０の最下端の２次巻線にお
ける接地に対する交流電圧を抵抗器４２及び４４
により分圧する。電圧比較器４６はこの分圧され
た交流電圧と接地電圧とを比較し、電源電圧が接
地電圧と交差する毎にそのレベルが反転するパル
ス信号fLを発生する。このパルス信号fLは電源電
圧と周波数及び位相が等しい基準信号であること
に注意されたい。
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Note that in this embodiment, the desired waveform is a sine wave. FIG. 1 is a block diagram showing a portion of a curve tracer including a repetitive voltage generating circuit according to the present invention. AC voltage from an external commercial power supply is supplied to the primary winding of a transformer 40 in a power supply circuit 36 via a power switch 34. The plurality of secondary windings of transformer 40 are connected to a DC voltage stabilization circuit (not shown) in power supply circuit 36 to generate DC voltage for each circuit. The alternating current voltage with respect to ground at the bottom secondary winding of transformer 40 is connected to resistors 42 and 44.
The pressure is divided by The voltage comparator 46 compares this divided AC voltage with the ground voltage, and generates a pulse signal f L whose level is inverted every time the power supply voltage crosses the ground voltage. It should be noted that this pulse signal f L is a reference signal having the same frequency and phase as the power supply voltage.
可変周波数信号発生器（VCO）５０の発振周
波数はパルス信号fLの2n（ｎ：正の整数）であり、
例えば4096倍であり、その出力信号（4096fL）を
分周器５２であるカウンタのクロツク端子に供給
する。分周器５２はVCO５０の出力信号を分周
し、周波数がパルス信号fLの16倍の信号１６、
８倍の信号８、４倍の信号４、２倍の信号２
ｆ及び等しい信号ｆを発生する。なお、１６，
８ｆ，４及び２の横線は入力信号に対し、位
相反転されたものであることを示す。位相比較器
４８はパルス信号fLと分周器５２からの出力パル
ス信号ｆとの位相を比較し、パルス信号fLとｆと
の位相が等しくなるように、VCO５０の発振周
波数を制御する。よつて、位相比較器４８、
VCO５０及び分周器５２は位相ロツク・ループ
を形成し、分周器５２の各出力パルスは交流電源
に同期する。 The oscillation frequency of the variable frequency signal generator (VCO) 50 is 2n (n: positive integer) of the pulse signal fL ,
For example, it is multiplied by 4096 times, and its output signal (4096f L ) is supplied to the clock terminal of the counter, which is the frequency divider 52. The frequency divider 52 divides the output signal of the VCO 50 to generate a signal 16 whose frequency is 16 times that of the pulse signal fL ,
8x signal 8, 4x signal 4, 2x signal 2
f and generates a signal f equal to f. In addition, 16,
The horizontal lines 8f, 4, and 2 indicate that the phase of the input signal is inverted. The phase comparator 48 compares the phases of the pulse signal f L and the output pulse signal f from the frequency divider 52, and controls the oscillation frequency of the VCO 50 so that the pulse signals f L and f have the same phase. Therefore, the phase comparator 48,
VCO 50 and frequency divider 52 form a phase-locked loop such that each output pulse of frequency divider 52 is synchronized to the AC power supply.
分周器５２の出力パルスをコード化する符号化
回路は４個の拝他的オア・ゲート（XOR）５４
〜６０を含んでおり、XOR５４はパルス信号１
６ｆ及び２を受け、XOR５６はパルス信号８
ｆ及び２を受け、XOR５８はパルス信号４
及び２を受け、XOR６０はパルス信号２及
びｆを受ける。よつて、XOR６０の出力パルス
信号Ｓはパルス信号ｆ即ちfLよりも位相が90度遅
れ、XOR５４〜５８の出力パルス信号Ａ〜Ｃは
パルス信号Ｓの90度（４分の１周期）毎に「000」
〜「111」にまた「111」〜「000」に変化する３
ビツトのデジタル信号となる。これら信号の位相
関係を第２図に示す。 The encoding circuit that encodes the output pulses of the frequency divider 52 consists of four mutually exclusive OR gates (XOR) 54.
~60, XOR54 is pulse signal 1
6f and 2, XOR56 receives pulse signal 8
f and 2, XOR58 receives pulse signal 4
and 2, and the XOR 60 receives pulse signals 2 and f. Therefore, the output pulse signal S of the XOR 60 is delayed in phase by 90 degrees from the pulse signal f, that is, f L , and the output pulse signals A to C of the XORs 54 to 58 are delayed every 90 degrees (1/4 period) of the pulse signal S. "000"
～Changes to “111” and “111” to “000”3
It becomes a bit digital signal. The phase relationship of these signals is shown in FIG.
第１選択手段であるアナログ・マルチプレクサ
６２はXOR５４〜５８からのデジタル信号Ａ〜
Ｃにより、入力端子Ｉを出力端子０〜７の１つに
選択的に接続する。即ち、選択端子Ａ〜Ｃの信号
が「000」のとき出力端子０を選択し、「001」の
とき出力端子１を選択し、「010」のとき出力端子
２を選択し、以下同様に「011」、「100」、「101」、
「110」及び「111」のとき夫々出力端子３，４，
５，６及び７を選択する。マルチプレクサ６２の
出力端子０〜７を夫々抵抗器６４〜７８の一端に
接続し、これら抵抗器の他端を積分器の入力端に
接続する。この積分器は、非反転入力端が接地さ
れた演算増幅器８０、並びにこの演算増幅器の反
転入力端及び出力端間に接続されたコンデンサ８
２により構成する。よつて、選択された抵抗器６
４〜７８の１つが入力抵抗器であるミラー積分器
となる。なお、これら抵抗器６４〜７８の値は例
えば、夫々15.0KΩ、16.9KΩ、19.1KΩ、23.7K
Ω、31.6KΩ、51.1KΩ及び154KΩであり、コン
デンサ８２の値は例えば0.1μFである。 The analog multiplexer 62, which is the first selection means, receives the digital signals A~ from the XORs 54~58.
C selectively connects input terminal I to one of output terminals 0-7. That is, when the signals at the selection terminals A to C are "000", output terminal 0 is selected, when the signal is "001", output terminal 1 is selected, when the signal is "010", output terminal 2 is selected, and so on. 011", "100", "101",
When "110" and "111", output terminals 3, 4,
Select 5, 6 and 7. Output terminals 0-7 of multiplexer 62 are connected to one end of resistors 64-78, respectively, and the other ends of these resistors are connected to the input end of the integrator. This integrator includes an operational amplifier 80 whose non-inverting input terminal is grounded, and a capacitor 8 connected between the inverting input terminal and the output terminal of this operational amplifier.
Consisting of 2. Therefore, the selected resistor 6
One of the input resistors 4 to 78 becomes a Miller integrator. Note that the values of these resistors 64 to 78 are, for example, 15.0KΩ, 16.9KΩ, 19.1KΩ, and 23.7K, respectively.
Ω, 31.6KΩ, 51.1KΩ, and 154KΩ, and the value of the capacitor 82 is, for example, 0.1μF.
積分器の出力信号Ｑをピーク値検出器を介して
電圧比較器に供給する。このピーク検出器はダイ
オード８６、コンデンサ８８、抵抗器９０及び９
２により構成する。電圧比較器８４は、積分器の
出力信号Ｑのピーク値と基準電圧VREFとを比較
し、それらの差である出力電圧は抵抗器９４及び
９６により分圧されて、反転増幅器９８及び非反
転増幅器１００に供給される。なお、反転増幅器
９８の入力抵抗器１０２及び帰還抵抗器１０４の
値は等しい。増幅器９８及び１００の出力電圧は
第２選択手段である電子スイツチ１０６を介して
マルチプレクサ６２の入力端子Ｉに供給する。ま
た、電子スイツチ１０６をパルス信号Ｓにより制
御する。これら回路素子５４〜８２及び１０６は
変換手段を構成する。 The output signal Q of the integrator is fed to a voltage comparator via a peak value detector. This peak detector consists of diode 86, capacitor 88, resistor 90 and 9
Consisting of 2. The voltage comparator 84 compares the peak value of the output signal Q of the integrator with the reference voltage V REF , and the output voltage, which is the difference between them, is divided by resistors 94 and 96, and is divided by the inverting amplifier 98 and the non-inverting is supplied to amplifier 100. Note that the values of the input resistor 102 and the feedback resistor 104 of the inverting amplifier 98 are equal. The output voltages of amplifiers 98 and 100 are applied to input terminal I of multiplexer 62 via second selection means, electronic switch 106. Further, the electronic switch 106 is controlled by the pulse signal S. These circuit elements 54 to 82 and 106 constitute conversion means.
よつて、第２図に示す如く、時点T0〜T1の４
分の１周期は、スイツチ１０６により非反転増幅
器１００の出力信号がマルチプレクサ６２の入力
端子Ｉに供給される。また、パルス信号Ａ〜Ｃに
より、この４分の１周期を８等分して抵抗器６４
〜７８を順次選択するので、積分器の出力信号Ｑ
は正弦波の４分の１周期となる。次に時点T1〜
T2の期間は、反転増幅器９８の出力電圧がマル
チプレクサ６２の入力端子Ｉに供給され、またこ
の期間を８等分して抵抗器７８〜６４を順次選択
する。以下、同様な動作により積分器の出力信号
Ｑは電源周波数と同相な繰返し正弦波電圧にな
る。なお、ピーク検出器８６〜９２と電圧比較器
８４とにより、積分器の入力電圧を制御してこの
正弦波電圧Ｑの振幅を一定に保持しているので、
外部商用電源の周波数及び振幅の変動に正弦波電
圧Ｑの振幅は影響されない。 Therefore, as shown in FIG .
During one period, the switch 106 supplies the output signal of the non-inverting amplifier 100 to the input terminal I of the multiplexer 62. In addition, by pulse signals A to C, this quarter cycle is divided into eight equal parts, and the resistor 64
~78 are selected sequentially, so the integrator output signal Q
is a quarter period of a sine wave. Then at time T 1 ~
During the period T2 , the output voltage of the inverting amplifier 98 is supplied to the input terminal I of the multiplexer 62, and this period is divided into eight equal parts to sequentially select the resistors 78-64. Thereafter, by similar operation, the output signal Q of the integrator becomes a repetitive sine wave voltage in phase with the power supply frequency. Note that the input voltage of the integrator is controlled by the peak detectors 86 to 92 and the voltage comparator 84 to keep the amplitude of the sine wave voltage Q constant.
The amplitude of the sinusoidal voltage Q is not affected by variations in the frequency and amplitude of the external commercial power supply.
積分器の出力電圧Ｑは、電子スイツチ１０８及
び可変増幅器（高調波歪を除去するローパス・フ
イルタを含んでいる）１１０を介して変圧器１２
の１次巻線に供給する。この変圧器１２の２次巻
線の後段の回路は第３図の回路と同じでもよい。
なお、第１図の回路では、位相比較器４８の出力
電圧を抵抗器１１６〜１２０により分圧した基準
電圧と比較器１１２及び１１４により比較してい
る。即ち、比較器１１２は位相比較器４８の出力
電圧が所定上限電圧よりも低いか否かを判断し、
比較器１１４は位相比較器４８の出口電圧が所定
下限電圧よりも高いか否かを判断している。そし
て、位相比較器４８の出力電圧が所定下限値以上
でかつ所定上限値以下の場合にスイツチ１０８が
増幅器８０を選択し、それ以外の場合にスイツチ
１０８が接地を選択する。よつて、変換手段の発
生する正弦波電圧Ｑの位相が、外部電源の位相と
所定値以上異なつた場合、この正弦波電圧Ｑを後
段に供給するのを阻止して、精度の下つた測定を
行なわないようにする。 The output voltage Q of the integrator is applied to the transformer 12 via an electronic switch 108 and a variable amplifier 110 (including a low-pass filter to remove harmonic distortion).
Supplied to the primary winding of The circuit after the secondary winding of this transformer 12 may be the same as the circuit shown in FIG.
In the circuit shown in FIG. 1, the output voltage of the phase comparator 48 is compared with a reference voltage divided by resistors 116 to 120 using comparators 112 and 114. That is, the comparator 112 determines whether the output voltage of the phase comparator 48 is lower than a predetermined upper limit voltage,
Comparator 114 determines whether the output voltage of phase comparator 48 is higher than a predetermined lower limit voltage. Then, when the output voltage of the phase comparator 48 is greater than or equal to a predetermined lower limit value and less than a predetermined upper limit value, the switch 108 selects the amplifier 80, and in other cases, the switch 108 selects grounding. Therefore, if the phase of the sine wave voltage Q generated by the conversion means differs from the phase of the external power supply by more than a predetermined value, this sine wave voltage Q is prevented from being supplied to the subsequent stage, and the measurement accuracy is reduced. Try not to do it.
上述は本発明の好適な実施例について説明した
が、本発明の要旨を逸脱することなく種々の変更
及び変形が可能である。例えば、電圧比較器８４
の前段にはピーク値検出器以外に平均値検出器、
実効値検出器等も利用できる。また、電圧比較器
８４の反転出力信号及び非反転出力信号を直接ス
イツチ１０６に供給してもよい。更に、変換手段
の抵抗器の数を更に増やすと共に、符号化回路５
４〜６０及びマルチプレクサ６２を変更して、正
弦波電圧Ｑを発生するときの傾きを一層細分化し
てもよい。また、抵抗器６４〜７８の値及び数を
変更させることにより三角波等の種々の波形も発
生できる。 Although the preferred embodiments of the present invention have been described above, various changes and modifications can be made without departing from the spirit of the invention. For example, voltage comparator 84
In addition to the peak value detector, there is an average value detector,
An effective value detector etc. can also be used. Alternatively, the inverted and non-inverted output signals of voltage comparator 84 may be directly supplied to switch 106. Furthermore, the number of resistors in the conversion means is further increased, and the encoding circuit 5
4 to 60 and the multiplexer 62 may be changed to further divide the slope when generating the sinusoidal voltage Q. Further, by changing the values and numbers of the resistors 64 to 78, various waveforms such as triangular waves can be generated.
上述の如く本発明によれば、外部電源の波形に
影響されない歪の少ない繰返し正弦波電圧を所定
振幅でかつ外部電源と同相で発生できる。よつ
て、カーブ・トレーサに利用した場合、表示歪が
なく、電源リツプルに影響されず、正確な測定が
可能となる。
As described above, according to the present invention, it is possible to generate a repetitive sine wave voltage with a predetermined amplitude and in phase with the external power source, which is not affected by the waveform of the external power source and has little distortion. Therefore, when used as a curve tracer, there is no display distortion, it is not affected by power supply ripples, and accurate measurements can be made.
第１図は本発明の好適な一実施例のブロツク
図、第２図は第１図の動作を説明する波形図、第
３図は繰返し電圧発生回路を含むカーブ・トレー
サのブロツク図、第４図は従来の繰返し電圧発生
回路のブロツク図である。
図において、４８は位相比較器、５０は可変周
波数信号発生器、５２は分周器、５４〜８０及び
１０６は変換手段、８４は電圧比較器である。
FIG. 1 is a block diagram of a preferred embodiment of the present invention, FIG. 2 is a waveform diagram explaining the operation of FIG. 1, FIG. 3 is a block diagram of a curve tracer including a repetitive voltage generating circuit, and FIG. The figure is a block diagram of a conventional repetitive voltage generating circuit. In the figure, 48 is a phase comparator, 50 is a variable frequency signal generator, 52 is a frequency divider, 54 to 80 and 106 are conversion means, and 84 is a voltage comparator.
Claims (1)
発生器の出力信号を分周して複数の分周出力信号
を発生する分周器と、該分周器の所定の分周出力
信号の位相と基準周波数信号の位相とを比較し
て、上記可変周波数信号発生器の発振周波数を制
御する位相比較器と、上記分周器の分周出力信号
に応じて入力電圧を所望波形に変換する変換手段
と、該変換出段の出力電圧に応じた電圧と基準電
圧とを比較して、上記変換手段の入力電圧を発生
する電圧比較器とを具え、上記変換手段から上記
基準周波数信号に同期した繰返し電圧を得ること
を特徴とする繰返し電圧発生回路。1. A variable frequency signal generator, a frequency divider that divides the output signal of the variable frequency signal generator to generate a plurality of frequency-divided output signals, and a phase of a predetermined frequency-divided output signal of the frequency divider. a phase comparator that controls the oscillation frequency of the variable frequency signal generator by comparing the phase of the reference frequency signal; and a converter that converts the input voltage into a desired waveform in accordance with the divided output signal of the frequency divider. and a voltage comparator that compares a voltage corresponding to the output voltage of the conversion stage with a reference voltage to generate an input voltage of the conversion means, and repeats the signal from the conversion means in synchronization with the reference frequency signal. A repetitive voltage generation circuit characterized by obtaining a voltage.
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59208791A JPS6187429A (en) | 1984-10-04 | 1984-10-04 | Generating circuit of repetitive voltage |
| NL8502385A NL8502385A (en) | 1984-10-04 | 1985-08-30 | DEVICE FOR MEASURING THE CHARACTERISTICS OF ELECTRONIC DEVICES. |
| GB08522462A GB2165363B (en) | 1984-10-04 | 1985-09-11 | Waveform generator and apparatus for measuring characteristics of electronic devices |
| DE19853533636 DE3533636C2 (en) | 1984-10-04 | 1985-09-20 | Device for measuring the characteristic data of electronic components |
| US06/780,957 US4727318A (en) | 1984-10-04 | 1985-09-27 | Apparatus for measuring characteristics of electronic devices |
| CA000491897A CA1242813A (en) | 1984-10-04 | 1985-09-30 | Apparatus for measuring characteristics of electronic devices |
| FR8514776A FR2571501B1 (en) | 1984-10-04 | 1985-10-04 | APPARATUS FOR MEASURING THE CHARACTERISTICS OF ELECTRONIC DEVICES |
| US07/074,910 US4782290A (en) | 1984-10-04 | 1987-07-17 | Apparatus for measuring characteristics or electronic devices |
| CA000547089A CA1248600A (en) | 1984-10-04 | 1987-09-16 | Sine-wave generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59208791A JPS6187429A (en) | 1984-10-04 | 1984-10-04 | Generating circuit of repetitive voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6187429A JPS6187429A (en) | 1986-05-02 |
| JPH0349215B2 true JPH0349215B2 (en) | 1991-07-26 |
Family
ID=16562170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59208791A Granted JPS6187429A (en) | 1984-10-04 | 1984-10-04 | Generating circuit of repetitive voltage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6187429A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0721526B2 (en) * | 1987-08-18 | 1995-03-08 | ソニ−・テクトロニクス株式会社 | Element measuring device |
-
1984
- 1984-10-04 JP JP59208791A patent/JPS6187429A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6187429A (en) | 1986-05-02 |
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