JPH0344148B2 - - Google Patents

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Publication number
JPH0344148B2
JPH0344148B2 JP58175684A JP17568483A JPH0344148B2 JP H0344148 B2 JPH0344148 B2 JP H0344148B2 JP 58175684 A JP58175684 A JP 58175684A JP 17568483 A JP17568483 A JP 17568483A JP H0344148 B2 JPH0344148 B2 JP H0344148B2
Authority
JP
Japan
Prior art keywords
reaction
reaction chamber
silicon
film
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58175684A
Other languages
Japanese (ja)
Other versions
JPS6067673A (en
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP17568483A priority Critical patent/JPS6067673A/en
Publication of JPS6067673A publication Critical patent/JPS6067673A/en
Priority to JP33905390A priority patent/JPH03183125A/en
Publication of JPH0344148B2 publication Critical patent/JPH0344148B2/ja
Granted legal-status Critical Current

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Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/4401Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical Vapour Deposition (AREA)
  • ing And Chemical Polishing (AREA)
  • Physical Or Chemical Processes And Apparatus (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はプラズマ気相反応方法およびその製造
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a plasma gas phase reaction method and an apparatus for producing the same.

〔従来の技術〕[Conventional technology]

従来、プラズマ気相反応方法においては、一対
の電極を平行に配し、平行平板型電極とし、その
電極間にプラズマ放電をグロー放電法により実施
することにより半導体被膜等の形成を行つてい
た。
Conventionally, in the plasma vapor phase reaction method, a pair of electrodes are arranged in parallel to form a parallel plate type electrode, and a plasma discharge is generated between the electrodes using a glow discharge method to form a semiconductor film, etc. .

またこの際形成される付着物はCF4+O2(2〜
20%)でCF2Cl2,CF3Br等でプラズマエツチを
行つていた。
Also, the deposits formed at this time are CF 4 +O 2 (2~
20%), plasma etching was performed using CF 2 Cl 2 , CF 3 Br, etc.

また、酸素または酸化珪素が反応室に混入しな
い真空引き可能な1つまたは複数の反応室にて、
被酸化物であるアモルフアス、マイクロクリスタ
ルまたはセミアモルフアス構造を有する非単結晶
の珪素または炭化珪素を主成分とする被膜を形成
する工程の際に同時に反応室の内部に形成されて
しまう同一主成分の付着物、フレーク、被膜等を
除去することがきわめて重要である。
In addition, in one or more reaction chambers that can be evacuated so that oxygen or silicon oxide does not enter the reaction chamber,
The same main component that is simultaneously formed inside the reaction chamber during the process of forming a film whose main component is amorphous, microcrystalline, or non-single-crystal silicon or silicon carbide, which are oxidized materials. It is extremely important to remove deposits, flakes, coatings, etc.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしかかる方法においてはエツチングの後、
炭素、酸素が内壁、フード等の表面に残存し、ま
た塩素(Cl)臭素(Br)が残存してしまつた。
However, in such a method, after etching,
Carbon and oxygen remained on the inner walls and surfaces of the hood, as well as chlorine (Cl) and bromine (Br).

この炭素がアモルフアス珪素中に混入すると、
電気伝導度を下げ、再結合中心を作つてしまつ
た。
When this carbon mixes into amorphous silicon,
This lowers the electrical conductivity and creates recombination centers.

また酸素が混入すると、水素と反応し、Si−
CH結合を構成し、光照射効果(ステブラ・ロン
スキ効果)による電気伝導度の劣化の原因になつ
てしまつた。
Also, when oxygen is mixed, it reacts with hydrogen and Si-
It forms a CH bond and becomes the cause of deterioration of electrical conductivity due to light irradiation effect (Stebla-Lonski effect).

さらに塩素、臭素が混入すると、この場合は原
子半径が弗素に比べて大きいため、再結合中心を
構成してしまつた。
Furthermore, when chlorine and bromine were mixed in, they formed recombination centers because their atomic radius was larger than that of fluorine.

これらのことより、反応室の内壁等に付着した
珪素、炭化珪素を主成分とした付着物を取るには
非酸素、非炭素、非塩素、非臭素気体が用いられ
ていることがプラズマ・エツチされた後に再び珪
素を主成分とする非単結晶半導体被膜形成を行う
際、その被膜の特性を向上させるためにきわめて
重要であることがわかつた。
From these facts, it is clear that non-oxygen, non-carbon, non-chlorine, and non-bromine gases are used in plasma etching to remove deposits mainly composed of silicon and silicon carbide attached to the inner walls of the reaction chamber. It has been found that this is extremely important for improving the properties of a non-single-crystal semiconductor film containing silicon as a main component when forming a non-single-crystal semiconductor film containing silicon as a main component.

以上のことに鑑みて本発明は、なされたもので
あり、半導体被膜形成の際、反応室の内壁に付着
した珪素、炭化珪素を主成分とした被膜を非酸
素、非炭素、非塩素、非臭素気体でエツチングす
ることにより、内壁に付着した付着物を珪素、炭
化珪素被膜の特性を劣化させることのないような
ものにすることを目的としたものである。
In view of the above, the present invention has been made, and when forming a semiconductor film, a film mainly composed of silicon or silicon carbide attached to the inner wall of a reaction chamber is The purpose of etching with bromine gas is to remove deposits adhering to the inner wall so that they do not deteriorate the properties of the silicon or silicon carbide coating.

〔問題を解決するための手段〕[Means to solve the problem]

本発明はかかる目的のため、真空引きが可能な
反応室にて、珪素または炭化珪素を主成分とする
非単結晶被膜を形成した後、前記反応室内部に付
着した珪素または炭化珪素を主成分とする付着物
を酸素が1%以下好ましくは0.1%以下の99.0%
以上の高純度を有する弗化水素(無水弗化水素と
もいう、以下HFという)をプラズマ化してドラ
イエツチをして除去することとしたものである。
For this purpose, the present invention forms a non-single-crystalline film mainly composed of silicon or silicon carbide in a reaction chamber that can be evacuated, and then removes silicon or silicon carbide that has adhered to the interior of the reaction chamber as its main component. 99.0% of deposits with oxygen content of 1% or less, preferably 0.1% or less
Hydrogen fluoride (also referred to as anhydrous hydrogen fluoride, hereinafter referred to as HF) having the above-mentioned high purity is turned into plasma and removed by dry etching.

このHFのプラズマを用いると、石英、ステン
レスはアモルフアス珪素の1/100以下のエツチ
速度でしかエツチングされず、反応容器の損傷が
実質的にまつたくないという特性を実験的に見出
し、さらに反応室内のエツチング後の残存物があ
つても水素と弗素であり、これらはともに珪素、
炭化珪素を主成分とする非単結晶半導体の再結合
中心の中和剤(ターミネイタ)でなるため何等半
導体特性の劣化を生じさせないものである。
Using this HF plasma, we have experimentally discovered that quartz and stainless steel can be etched at an etch rate less than 1/100 of that of amorphous silicon, and that there is virtually no damage to the reaction vessel. What remains after etching is hydrogen and fluorine, both of which are silicon and fluorine.
Since it is a neutralizer (terminator) for the recombination center of a non-single-crystal semiconductor mainly composed of silicon carbide, it does not cause any deterioration of semiconductor characteristics.

よつてこのHFのプラズマは、非単結晶半導体
の被膜形成用の反応室内の清浄化にきわめて理想
的であることが判明した。
Therefore, it has been found that this HF plasma is extremely ideal for cleaning the inside of a reaction chamber for forming a film on a non-single crystal semiconductor.

以下に本発明の実施例を図面に従つて説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

実施例 1 本実施例は珪素または炭化珪素を主成分とする
非単結晶半導体層をP型半導体、I型半導体およ
びN型半導体と積層してPIN接合を基板上に形成
するに際し、それぞれの反応容器を分離部を介し
て連結せしめたマルチチヤンバ方式のPCVD法お
よびこのそれぞれの反応室にHFによるプラズ
マ・エツチ(以下PEという)法を用いてP型用
不純物、N型用不純物がPEの際互いに混入しな
いように独立してエツチングを行う方式のもので
ある。そして、かかる多数の反応容器を連結した
マルチチヤンバ方式のプラズマ反応方法におい
て、一度に多数の基板を同時にその被膜成長速度
を大きくしたいわゆる多量生産方式のものであ
る。
Example 1 In this example, when a PIN junction is formed on a substrate by laminating a non-single crystal semiconductor layer mainly composed of silicon or silicon carbide with a P-type semiconductor, an I-type semiconductor, and an N-type semiconductor, the reactions of each are evaluated. Using a multi-chamber PCVD method in which containers are connected through a separation part and a plasma etching (hereinafter referred to as PE) method using HF in each reaction chamber, P-type impurities and N-type impurities are removed from each other during PE. This is a method in which etching is performed independently to prevent contamination. This multi-chamber plasma reaction method in which a large number of reaction vessels are connected is a so-called mass production method in which a large number of substrates are grown at a high film growth rate at the same time.

第1図に従つて本発明方法に用いたプラズマ気
相反応装置の実施例を説明する。
An embodiment of a plasma vapor phase reactor used in the method of the present invention will be described with reference to FIG.

この図面は、PIN接合、PIP接合、NIN接合、
PN接合またはPINPIN…PIN接合等の基板上の
半導体に、異種導電型でありながらも、形成され
る半導体の主成分または化学量論比(構成成分
比)の異なる半導体層をそれぞれの半導体層をそ
の前工程において形成された半導体層の影響(混
入)を受けずに積層させるための多層に自動かつ
連続的に形成するための装置である。
This drawing shows PIN junction, PIP junction, NIN junction,
Semiconductor layers with different conductivity types but different main components or stoichiometric ratios (constituent component ratios) are formed on a semiconductor on a substrate such as a PN junction or PINPIN...PIN junction. This is an apparatus for automatically and continuously forming multiple layers without being influenced (contaminated) by semiconductor layers formed in the previous process.

図面においてはPIN接合を構成する3つのP,
IおよびN型の半導体層を積層して形成する3つ
の反応系(,,)とさらに第1および第2
の予備室を有するマルチチヤンバ(ここでは3つ
の反応容器)方式のプラズマ気相反応装置を示
す。
In the drawing, the three Ps that make up the PIN joint,
Three reaction systems (,,) formed by stacking I- and N-type semiconductor layers, and the first and second
This figure shows a multi-chamber (here, three reaction vessels) type plasma gas phase reactor having several preliminary chambers.

勿論図面において系,の間にそれぞれの反
応室の混入をさらに少なくするため、バツフア室
を設け、また系、系の間に他のバツフア室の
分離部を設けて7つの室を連結することにより1
つのPIN接合を有する半導体を積層してもよい。
Of course, in the drawing, in order to further reduce the mixing of the reaction chambers between the systems, a buffer chamber is provided between the systems, and a separate part of another buffer chamber is provided between the systems to connect the seven chambers. 1
Semiconductors having two PIN junctions may be stacked.

本実施例はかかるマルチチヤンバ方式のP,
I,Nをそれぞれの反応室にて独立に形成させた
後の反応室内に付着した不純物をエツチングして
除去したものである。
In this embodiment, P of such a multi-chamber system,
After I and N were formed independently in each reaction chamber, impurities deposited in the reaction chamber were removed by etching.

図面における系,,は、3つの各反応室
6,7,8を有し、それぞれの反応容器間に分離
部としてのゲート弁44,45,46,47を有
している。またそれぞれ独立して反応性気体の導
入フード17′,18′,19′と排気フード17,
18,19とを有し、反応性気体が供給系または
排気系から逆流、または他の系から反応性気体の
混入を防いでいる。
The system in the drawings has three reaction chambers 6, 7, 8, and gate valves 44, 45, 46, 47 as separation parts between the reaction vessels. In addition, the reactive gas introduction hoods 17', 18', 19' and the exhaust hood 17,
18 and 19, to prevent reactive gas from flowing back from the supply system or exhaust system, or from mixing with reactive gas from other systems.

この装置は入り口側には第1の予備室5が設け
られ、まず扉42より基板ホルダ(ホルダともい
う)74に基板4を挿着し、この予備室に配置さ
せた。
This apparatus is provided with a first preliminary chamber 5 on the entrance side, and the substrate 4 is first inserted into a substrate holder (also referred to as holder) 74 through the door 42 and placed in this preliminary chamber.

この被形成面を有する基板は被膜形成を行わな
い裏面を互いに隣接し、2枚を一対として6cmの
間〓を有して林立させている。
The substrates having the surfaces on which the film is to be formed are arranged so that the back surfaces on which the film is not formed are adjacent to each other, and two of the substrates are arranged in pairs with a distance of 6 cm between them.

2〜10cmの一定の間〓を経て被膜形成面に概略
平行に配置された基板の加熱は赤外線ランプによ
り行つた。
An infrared lamp was used to heat the substrate, which was placed approximately parallel to the surface on which the film was formed, with a distance of 2 to 10 cm between the substrates.

反応空間の大きさは20cm×60cmの基板を20枚同
時に形成させる場合、高さ50cm、巾70cm、奥行き
70cmであり、各反応室は高さ80cm、巾120cm、奥
行き120cmとした。
When forming 20 substrates of 20 cm x 60 cm at the same time, the reaction space size is 50 cm in height, 70 cm in width, and 70 cm in depth.
Each reaction chamber had a height of 80 cm, a width of 120 cm, and a depth of 120 cm.

また、HFガスを用いたプラズマエツチング法
においては金属例えばアルミニユームまたは酸化
珪素はエツチング処理を1時間行つても200Å以
下しかエツチングされず正確には3Å/分のエツ
チング速度であつた。
Furthermore, in the plasma etching method using HF gas, metals such as aluminum or silicon oxide were etched by less than 200 Å even after one hour of etching, and to be more precise, the etching rate was 3 Å/min.

このうち酸化珪素に関してはSi−Oの結合部分
において、電気陰性度の差によつて珪素元素はδ+
に電荷を帯びている。一方HFガスを用いてプラ
ズマ化を行つた場合、HFラジカルはCF3ラジカ
ルのように電気的に偏つた状態を取らないので酸
化珪素とは反応が進行しにくいのがその理由であ
る。またHFガスは金属の表面に付着して不動体
を形成し易い性質を持つているので、活性化され
たHFガスが金属表面になかなか達しないために
エツチングされないのであります。
Among these, regarding silicon oxide, in the Si-O bond part, silicon element is δ + due to the difference in electronegativity.
is charged with an electric charge. On the other hand, when HF gas is used to generate plasma, HF radicals do not take an electrically biased state like CF 3 radicals, so the reaction with silicon oxide is difficult to proceed. Furthermore, since HF gas has the property of easily adhering to metal surfaces and forming passive bodies, activated HF gas does not easily reach the metal surface and is not etched.

このため反応室の作製において、石英、ステン
レスを用いたマルチチヤンバ方式の反応室を作製
した。そしてそれぞれの反応室内での被膜の特性
の向上に加えて、チヤンバ内壁に不要の反応生成
物が付着することを可能なかぎり防ぎ、逆に加え
て供給した反応性気体の被膜になる割合、即ち収
集効率を高めている。このため絶縁性(石英)ホ
ルダにより囲み、チムニー(煙突)状に基板の配
置されている筒状空間に反応性気体を供給フード
に選択的に導入させ、排気フードに排気させた。
さらに基板の被形成面を実質的に被膜形成の反応
空間となるチムニーの内壁を構成せしめるように
した。
For this reason, we fabricated a multi-chamber type reaction chamber using quartz and stainless steel. In addition to improving the properties of the film in each reaction chamber, it also prevents unnecessary reaction products from adhering to the inner walls of the chamber as much as possible, and conversely improves the rate at which the supplied reactive gas forms a film. Improving collection efficiency. For this purpose, reactive gas was selectively introduced into a supply hood into a cylindrical space surrounded by an insulating (quartz) holder, in which the substrates were arranged in a chimney shape, and was exhausted through an exhaust hood.
Further, the surface of the substrate to be formed substantially constitutes the inner wall of the chimney, which serves as a reaction space for film formation.

そしてこの第1の予備室5を真空ポンプ35に
てバルブを開けて真空引きをした。この後、予め
真空引きがされている反応室6,7,8との分離
用のゲート弁44,45,46,47を開けて基
板およびホルダを移した。例えば、予備室5より
第1の反応容器6に移し、さらにゲート弁44を
閉じることにより基板1およびホルダ74を第1
の反応室6に移動させたものである。この時、第
1の反応室6に保持されていた基板1は第2の反
応室7に、また第2の反応室7に保持されていた
基板2は第3の反応室8に、また第3の反応室8
に保持されていた基板3は出口側の第2の予備室
9に同時にゲート弁45,46,47を開けて移
動させた。この後、ゲート弁44,45,46,
47を閉めた。第2の予備室に移された基板はゲ
ート弁47が閉じられた後41より窒素が導入さ
れて大気圧にされ、43の扉より外へ出した。
Then, the first preparatory chamber 5 was evacuated using the vacuum pump 35 by opening the valve. Thereafter, the gate valves 44, 45, 46, 47 for separation from the reaction chambers 6, 7, 8, which had been evacuated in advance, were opened and the substrate and holder were transferred. For example, by transferring the substrate 1 and holder 74 from the preliminary chamber 5 to the first reaction vessel 6 and closing the gate valve 44,
It was moved to the reaction chamber 6 of At this time, the substrate 1 held in the first reaction chamber 6 is transferred to the second reaction chamber 7, and the substrate 2 held in the second reaction chamber 7 is transferred to the third reaction chamber 8. 3 reaction chamber 8
The substrate 3 held therein was moved to the second preliminary chamber 9 on the exit side by simultaneously opening the gate valves 45, 46, and 47. After this, gate valves 44, 45, 46,
47 closed. After the gate valve 47 was closed, the substrate transferred to the second preliminary chamber was brought to atmospheric pressure by introducing nitrogen through the gate 41, and was taken out through the door 43.

系における第1の反応室6でP型半導体層を
PCVD法により形成する場合を以下に示す。
A P-type semiconductor layer is formed in the first reaction chamber 6 in the system.
The case of forming by PCVD method is shown below.

反応系(反応室6を含む)は10-3〜10torr好
ましくは0.01〜1torr例えば0.08torrとした。
The reaction system (including reaction chamber 6) was set to 10 -3 to 10 torr, preferably 0.01 to 1 torr, for example 0.08 torr.

反応性気体は珪化物気体24に対してはシラン
(SinH2o+2n>1特にSiH4)、フツ化珪素(SiF4
SiF2)等があるが、取扱が容易なシランを用い
た。本実施例のSixC1-x(0<x<1)を形成する
ため、炭化物気体23に対してはメタン(CH4
を用いた。
For the silicide gas 24, the reactive gas is silane (SinH 2o+2 n>1, especially SiH 4 ), silicon fluoride (SiF 4 ,
SiF 2 ), etc., but we used silane, which is easy to handle. In order to form Si x C 1-x (0<x<1) in this example, methane (CH 4 ) is used for the carbide gas 23.
was used.

炭化珪素(SixC1-x0<x<1)に対しては、
P型の不純物としてボロンを水素にて2000PPM
に希釈されたジボランより25より供給した。ま
たガリユームをTMG(Ga(CH33)により1019
9×1021cm-3の濃度になるように加えてもよい。
For silicon carbide (Si x C 1-x 0<x<1),
2000PPM of boron with hydrogen as a P-type impurity
diborane diluted to 25%. In addition, galiyum was treated with TMG (Ga(CH 3 ) 3 ) at 10 19 ~
It may be added to a concentration of 9×10 21 cm −3 .

これらの反応性気体はそれぞれ流量計33およ
びバルブ32を経て、反応性気体の供給フード1
7より高周波電源14の負電極61を経て反応容
器6に供給された。反応性気体はこのホルダ74
に囲まれた筒状空間内に供給され、この空間を構
成する基板1に被膜形成を行つた。さらに負電極
61と正電極51間に電気エネルギ例えば
13.56MHzの高周波エネルギ14を加えてプラズ
マ反応せしめ、基板上に反応生成物を被膜形成せ
しめた。
These reactive gases pass through a flow meter 33 and a valve 32, respectively, to the reactive gas supply hood 1.
7 and was supplied to the reaction vessel 6 via the negative electrode 61 of the high frequency power source 14. The reactive gas is in this holder 74.
A coating was formed on the substrate 1 constituting this space. Further, electric energy is applied between the negative electrode 61 and the positive electrode 51, for example.
High frequency energy 14 of 13.56 MHz was applied to cause a plasma reaction, and a reaction product formed a film on the substrate.

さらにこの第1の高周波の電気エネルギに直角
の電界で他の第2の高周波エネルギを電源84よ
り一対の電極71,81より加え形成させる被膜
の均一化を図つた。
Furthermore, another second high frequency energy is applied from the power source 84 through the pair of electrodes 71 and 81 in an electric field perpendicular to this first high frequency electric energy to make the formed film uniform.

基板は導体基板(ステンレス、チタン、アルミ
ニユーム、その他の金属)、半導体(珪素、ゲル
マニユーム)、絶縁体(アルミナ、ガラス、有機
物質)または複合基板(アルミニユーム、ステン
レス上に絶縁膜を形成させた絶縁性表面を有する
可曲性基板を形成し、この上面に分離されて被膜
の導体電極が形成された基板またはガラス絶縁基
板の上面に弗素が添加された酸化スズ、ITO等の
導電膜が単層またはITO上にSnO2が形成された
2層膜が形成されたもの)を用いた。
The substrate can be a conductive substrate (stainless steel, titanium, aluminum, or other metal), a semiconductor (silicon, germanium), an insulator (alumina, glass, organic material), or a composite substrate (aluminum, an insulating film formed on stainless steel). A single layer or a conductive film such as tin oxide or ITO doped with fluorine is formed on the upper surface of a substrate or a glass insulating substrate on which a conductive electrode of a film is formed by separating the flexible substrate with a surface. A two-layer film of SnO 2 formed on ITO) was used.

かかる基板を100〜400℃例えば200℃に赤外線
ヒータ11,11′より加熱した。
The substrate was heated to 100 to 400°C, for example 200°C, using infrared heaters 11 and 11'.

この後、前記したが、この容器に前記した反応
性気体を導入し、さらに10〜500W例えば200Wに
高周波エネルギ14,84をそれぞれ供給してプ
ラズマ反応を起こさせた。
Thereafter, as described above, the above-mentioned reactive gas was introduced into this container, and high-frequency energy 14 and 84 of 10 to 500 W, for example 200 W, was supplied respectively to cause a plasma reaction.

かくしてP型半導体層はB2H6/SiH4=0.5%,
CH4/(SiH4+CH4)=50%の条件にて、この反
応系で約100Åの厚さを有する薄膜(膜厚のば
らつき95〜105Å)として形成させた。Eg=
2.0eV,σ=1×10-6〜3×10-5(Ωcm)-1であつ
た。
Thus, the P-type semiconductor layer has B 2 H 6 /SiH 4 =0.5%,
A thin film having a thickness of about 100 Å (film thickness variation: 95 to 105 Å) was formed using this reaction system under the conditions of CH 4 /(SiH 4 +CH 4 )=50%. Eg=
2.0eV, σ=1×10 -6 to 3×10 -5 (Ωcm) -1 .

かくして1〜5分間プラズマ気相反応をさせ
て、P型不純物としてホウ素またはガリユームが
添加された炭化珪素膜を約100Åの厚さに作製し
た。さらにこの第1の半導体層上に基板を前記し
た操作順序に従つて第2の反応室7に移動し、こ
こで真性の半導体層を約5000Åの厚さに形成させ
た。
In this way, a plasma vapor phase reaction was carried out for 1 to 5 minutes, and a silicon carbide film doped with boron or gallium as a P-type impurity was produced to a thickness of about 100 Å. Further, the substrate was transferred to the second reaction chamber 7 on top of the first semiconductor layer according to the above-described operating sequence, where an intrinsic semiconductor layer was formed to a thickness of about 5000 Å.

即ち第1図における反応系において、半導体
の反応性気体としてシランを28より、また、
1017cm-3以下のホウ素を添加するため、水素、シ
ラン等により0.5〜30PPMに希釈したB2H6を2
7より、また、キヤリアガスを必要に応じて26
より供給フード18、ホルダ74、排気フード18
により真空ポンプ37へ排気させた。被膜として
シランによりアモルフアス珪素を作製した場合、
5000Åの厚さにSiH4200c.c./分、被膜形成速度8
Å/秒、基板(20cm×60cmを20枚、延べ面積
24000cm2)で圧力0.08torr、全出力300Wとした。
That is, in the reaction system shown in FIG. 1, silane is used as the reactive gas of the semiconductor, and
In order to add less than 10 17 cm -3 of boron, B 2 H 6 diluted to 0.5 to 30 PPM with hydrogen, silane, etc.
From 7, also add carrier gas to 26 as needed.
Supply hood 18, holder 74, exhaust hood 18
The air was evacuated to the vacuum pump 37. When amorphous silicon is made with silane as a coating,
SiH 4 200 c.c./min to 5000 Å thickness, film formation rate 8
Å/sec, substrate (20 pieces of 20cm x 60cm, total area
24000cm 2 ), the pressure was 0.08torr, and the total output was 300W.

かくして第1の反応室にてプラズマ気相法によ
りP型半導体層を形成した上に他のPCVD法によ
りI型半導体層を形成させてPI接合を構成させ
た。
Thus, in the first reaction chamber, a P-type semiconductor layer was formed by the plasma vapor phase method, and then an I-type semiconductor layer was formed by another PCVD method to form a PI junction.

このI型半導体層を約5000Åの厚さに形成させ
た後、基板は前記した操作に従つて第1図系の
反応室8に移され、N型半導体層を形成させた。
このN型半導体層は、PCVD法によりフオスヒン
をPH3/SiH4=1.0%とし31よりまたシランを
30より、またキヤリアガスの水素を38より
SiH4/H2=50%として供給し、系と同様にし
て約200Åの厚さにN型の微結晶性または繊維構
造を有する多結晶の半導体層を形成させ、さらに
その上面にメタンをCH4/(SiH4+CH4)=0.1と
して29より供給してSixC1-x(0<x<1)で示
されるN型半導体層を10〜200Åの厚さ例えば50
Åの厚さに積層して形成させたものである。その
他反応装置については系と同様である。
After forming this I-type semiconductor layer to a thickness of about 5000 Å, the substrate was transferred to the reaction chamber 8 of FIG. 1 according to the operations described above, and an N-type semiconductor layer was formed.
This N-type semiconductor layer was made by PCVD using phosphin at PH 3 /SiH 4 = 1.0%, silane from 31, silane from 30, and hydrogen as a carrier gas from 38.
SiH 4 /H 2 = 50% was supplied, and an N-type microcrystalline or polycrystalline semiconductor layer with a fibrous structure was formed to a thickness of approximately 200 Å in the same manner as the system, and methane was further added to the top surface of the polycrystalline semiconductor layer with a thickness of approximately 200 Å. 4 / (SiH 4 + CH 4 ) = 0.1 and supply from 29 to form an N-type semiconductor layer represented by Si x C 1-x (0<x<1) to a thickness of 10 to 200 Å, for example 50
It is formed by laminating layers to a thickness of . Other reaction equipment is the same as the system.

かかる工程の後、第2の予備室9より外にPIN
接合を構成して出された基板上に100〜1500Åの
厚さのITOをさらにその上に反射性電極としての
アルミニユーム電極を真空蒸着法により約0.3μの
厚さに作り、ガラス基板上に(ITO+SnO2)表
面電極−(PIN半導体)−(裏面電極)を構成させ
た。
After this process, enter the PIN from the second preliminary room 9.
ITO with a thickness of 100 to 1500 Å is formed on the substrate formed by forming the bond, and an aluminum electrode with a thickness of about 0.3 μm is made as a reflective electrode on top of it by vacuum evaporation method, and then on the glass substrate ( ITO+SnO 2 ) surface electrode-(PIN semiconductor)-(back surface electrode) was constructed.

その光電変換装置としての特性は7〜9%平均
8%を10cm×10cmの基板でAMI(100mW/cm2
の条件下にて真性効率特性として有し、集積化し
てハイブリツド型にした20cm×60cmのガラス基板
においても、3〜5%(平均3.8%)を実効効率
で得ることができた。
Its characteristics as a photoelectric conversion device are 7 to 9%, average 8%, and AMI (100mW/cm 2 ) on a 10cm x 10cm substrate.
Under these conditions, it was possible to obtain an effective efficiency of 3 to 5% (3.8% on average) even in a 20 cm x 60 cm glass substrate integrated into a hybrid type.

かくのごとくにして第1図に示した反応室にお
いて、少なくとも50回の被膜形成を行つた。する
と系の反応室6では約1μ、系の反応室7で
は約80μ、系の反応室8では約2μの付着物が内
壁やフード表面に形成された。この反応室内の温
度は一定のため、約80μの厚さで石英フード、電
極に形成されても、大部分ではフレーク(雪片)
とならない。しかし側面の付着物はフレークが発
生し、これが被形成面に付着するとピンホールの
発生を促し、素子の劣化をさせている。
In this way, coatings were formed at least 50 times in the reaction chamber shown in FIG. As a result, deposits of about 1μ in the reaction chamber 6 of the system, about 80μ in the reaction chamber 7 of the system, and about 2μ in the reaction chamber 8 of the system were formed on the inner walls and the hood surface. Since the temperature inside this reaction chamber is constant, even if a thickness of about 80 μm is formed on the quartz hood and electrode, most of it is flakes (snowflakes).
Not. However, the deposits on the side surfaces generate flakes, and when these adhere to the surface on which they are formed, they promote the generation of pinholes and deteriorate the device.

このため、これらの付着物が最大100μ付着し
た後、反応室にドーピング系より無水弗化水素
(純度99.9%以上)を系では100、系では
101、系では102より100c.c./分の流量導
入した。反応室6,7,8は内部圧力を0.2torr
として13.56MHzの圧力を計500W加えた。反応室
内の温度は室温〜300℃、本実施例では150℃とし
た。すると系において1000Å/分、系にて
3000Å/分、系にて1000Å/分のエツチ速度を
得ることができるため、5時間エツチングすると
十分反応室内を清浄にすることが可能となつた。
For this reason, after a maximum of 100 microns of these deposits have adhered, anhydrous hydrogen fluoride (purity of 99.9% or more) is added to the reaction chamber from the doping system at 100 c.c./min from 100 for the system, 101 for the system, and 102 for the system. Introduced flow rate. The internal pressure of reaction chambers 6, 7, and 8 is 0.2 torr.
A total of 500W of pressure at 13.56MHz was applied. The temperature in the reaction chamber was from room temperature to 300°C, and in this example was 150°C. Then, 1000Å/min in the system,
Since an etching rate of 1000 Å/min could be obtained using the system, it was possible to sufficiently clean the inside of the reaction chamber after etching for 5 hours.

さらに必要ならばこのHFを真空排気した後水
素(純度4N以上)でプラズマ水素クリーニング
をするとFの付着物をさらに除去することができ
た。
Furthermore, if necessary, after the HF was evacuated, plasma hydrogen cleaning was performed using hydrogen (purity of 4N or higher) to further remove F deposits.

他方、HF中に1%以上の酸素または酸化物例
えば4%の酸素が混入すると、珪素は殆どエツチ
されず1%の混入でもアモルフアス珪素は200〜
500Å/分ときわめてばらつき、さらにその表面
も凹凸が大きく実用化ができなかつた。このこと
よりHF中の酸素または酸化物気体の濃度は1%
以下の可能なかぎり少なくすることが重要であつ
た。
On the other hand, if 1% or more of oxygen or oxides, such as 4% oxygen, are mixed into HF, silicon is hardly etched, and even with 1%, amorphous silicon is
The rate was extremely variable at 500 Å/min, and the surface was also highly uneven, making it impossible to put it to practical use. From this, the concentration of oxygen or oxide gas in HF is 1%.
It was important to minimize the following:

この場合、PCVDにより多量に付着物が形成さ
れる高電界領域に同一電極で除去を行うため同様
に高電界となり、厚く付着物ができた部分のより
速いエツチ速度を得ることができる。このため同
一反応装置に同一反応電極でPEを行うことは清
浄化のためにきわめて好都合であつた。
In this case, since removal is performed using the same electrode in a high electric field area where a large amount of deposits are formed due to PCVD, the electric field is similarly high, and a faster etch rate can be obtained in areas where thick deposits are formed. For this reason, it was extremely convenient for cleaning to perform PE using the same reaction electrode in the same reaction apparatus.

さらに従来よりのCF4+O2反応ではもし局部的
な強電界領域があると、この部分ではCFよりCF
ラジカルではなく、Cそのものがさらに分離して
でき付着してしまう。しかしこの炭素を完全に除
去するには酸素のPFをおなじ反応室で再びしな
ければならず、反応室内のC,Oが残存してしま
う。
Furthermore, in the conventional CF 4 + O 2 reaction, if there is a local strong electric field region, CF will react more strongly than CF in this region.
Instead of radicals, C itself is further separated and attached. However, to completely remove this carbon, oxygen must be PFed again in the same reaction chamber, and C and O remain in the reaction chamber.

このためこの後の被膜形成にはもつとも避ける
べきC,O不純物が混入してしまう。
Therefore, C and O impurities, which should be avoided, are mixed into the subsequent film formation.

本発明においては、反応性気体はHとFのみで
あるため、PEの後の残存付着物がC,O,Cl,
Br等であることは本質的に有りえないという特
長を有し、珪素を主成分とする被膜形成用の反応
室でのPE法には最適であつた。
In the present invention, since the reactive gases are only H and F, the remaining deposits after PE are C, O, Cl,
It has the characteristic that it is essentially impossible for it to be Br, etc., and is ideal for the PE method in a reaction chamber for forming a film mainly composed of silicon.

またこの被膜形成を100〜300バツチ行うと、収
率が20%を示していて、排気されずに内壁に付着
する反応生成物も10μ〜5mmの厚さにまで形成さ
れてしまつたが、この付着物をHFのPE法により
除去すると、実質的に5μ付着していても2時間
で十分除去してしまうことができた。
Furthermore, when this coating was formed in batches of 100 to 300 times, the yield was 20%, and the reaction products that adhered to the inner wall without being exhausted were also formed to a thickness of 10 μ to 5 mm. When the deposits were removed using the HF PE method, even if the deposit was substantially 5 μm, it could be sufficiently removed in 2 hours.

さらにこのHFのPEの第1の反応室および石英
フード等の治具の表面には何等の炭素等の粉末が
残存することなく、十分清浄な平坦な表面を得る
ことができた。
Further, no powder such as carbon remained on the surfaces of the HF PE first reaction chamber and jigs such as the quartz hood, and a sufficiently clean and flat surface could be obtained.

形成させる半導体の種類に関しては、前記した
ごとく、SixC1-x―Si―SixC1-xの複数層ではなく
他の族のSi,Ge,SixC1-x(0<x<1)Six
Ge1-x(0<x<1)、SixSn1-x(0<x<1)単層
または多層であつてもよいことはいうまでもな
い。本発明は3つの反応容器を用いてマルチチヤ
ンバ方式でのPCVD法を示した。しかしこれを1
つの反応容器とし、そこでPCVD法によりPIN接
合その他の接合を有する半導体層を形成させるこ
とは有効である。
Regarding the type of semiconductor to be formed, as mentioned above, it is not a multiple layer of Si x C 1-x -Si-Si x C 1-x , but other groups of Si, Ge, Si x C 1-x (0<x <1) Si x
It goes without saying that it may be Ge 1-x (0<x<1), Si x Sn 1-x (0<x<1), a single layer or a multilayer. The present invention demonstrated a multi-chamber PCVD method using three reaction vessels. But this 1
It is effective to form a semiconductor layer having a PIN junction or other junction by using a single reaction vessel and using the PCVD method.

本発明で形成された非単結晶半導体被膜は、絶
縁ゲイト型電界効果半導体装置におけるN(ソー
ス)I(チヤネル形成領域)N(ドレイン)接合ま
たはPIP接合に対しても有効である。さらにPIN
ダイオードであつてエネルギバンド巾がW−N−
W(WIDE−NALLOW−WIDE)のSixC1-x―Si
―SixC1-x(0<x<1)構造のPIN接合型または
その逆にN−W−N型のPIN接合型のスーパラテ
イスを用いた可視光、発光素子を作つてもよい。
特に光入射光側のエネルギバンド巾を大きくした
ヘテロ接合構造を有するいわゆるW(PまたはN
型)―N(I型)(WIDE TO NALLOW)と各
反応室にて導電型のみではなく生成物を異ならせ
てそれぞれに独立して作製して積層させ、さらに
独立してPEを行うことが可能になり、工業的に
きわめて重要なものであると信ずる。
The non-single crystal semiconductor film formed according to the present invention is also effective for N (source), I (channel forming region), N (drain) junctions or PIP junctions in insulated gate field effect semiconductor devices. More PIN
It is a diode and the energy band width is W-N-
W (WIDE−NALLOW−WIDE) Si x C 1-x ―Si
-Visible light and light emitting elements may be made using a PIN junction type superstructure with a Si x C 1-x (0<x<1) structure, or vice versa, a N-W-N type PIN junction type superstructure.
In particular, the so-called W (P or N
type) - N (type I) (WIDE TO NALLOW), and in each reaction chamber, not only the conductivity type but also the product is different, each is independently produced and laminated, and PE can be performed independently. We believe that this will become possible and will be of great industrial importance.

加えて本実施例は水素または弗素が添加された
非単結晶半導体層、好ましくは珪素、ゲルマニユ
ーム、炭化珪素(SiCのみではなく、本発明にお
いては、SixC1-x0<x<1の総称を意味する)、
その他珪素を主成分とする珪化ケルマニユーム
(SixGe1-x0<x<1)、珪化スズ((SixSn1-x
<x<1)であつて、この被膜中に活性状態の水
素または弗素を充填することにより、再結合中心
密度の小さなP,IおよびN型の導電型を有する
半導体層を複数形成し、その積層境界にてPI接
合、NI接合、PN接合またはこれらを組み合わせ
てPIP接合、NIN接合、PIN接合、PNI接合を形
成するとともに、それぞれの半導体層に他の隣接
する半導体層からの不純物が混入して接合特性を
劣化させることなく形成するとともに、またそれ
ぞれに半導体層を形成する工程間に大気特に酸素
に触れさせて、半導体の一部が酸化されることに
より層間絶縁物が形成されることのないようにし
た連続生産を行うためのプラズマ気相反応でもあ
る。
In addition, this embodiment uses a non-single-crystal semiconductor layer doped with hydrogen or fluorine, preferably silicon, germanium, silicon carbide (not only SiC, but in the present invention, Si x C 1-x 0<x<1). meaning a generic term),
In addition, kermanium silicide (Si x Ge 1-x 0<x<1) whose main component is silicon, tin silicide ((Si x Sn 1-x 0
<x<1), and by filling this film with hydrogen or fluorine in an active state, a plurality of semiconductor layers having conductivity types of P, I, and N types with a small recombination center density are formed. A PI junction, NI junction, PN junction, or a combination of these forms a PIP junction, NIN junction, PIN junction, or PNI junction at the layer boundary, and impurities from other adjacent semiconductor layers are mixed into each semiconductor layer. It can be formed without deteriorating the junction characteristics, and it also prevents the formation of an interlayer insulator by exposing a part of the semiconductor to the atmosphere, especially oxygen, during the process of forming the semiconductor layer, which oxidizes a part of the semiconductor. It is also a plasma gas phase reaction for continuous production.

本発明のプラズマ・エツチングを行う前の被膜
形成はプラズマCVD法ではなくプラズマを用い
ない光CVD法、LT CVD法(HOMO CVD法と
もいう)を採用し、さらにその際作られる反応室
内の付着物をHFのPE法により除去することは有
効である。
The film formation before the plasma etching of the present invention is not a plasma CVD method, but an optical CVD method that does not use plasma, or a LT CVD method (also referred to as the HOMO CVD method). It is effective to remove the HF using PE method.

〔効果〕〔effect〕

本発明は、珪素または炭化珪素を主成分とする
非単結晶被膜を形成した後、前記反応室内部に付
着した珪素または炭化珪素を主成分とする付着物
を非酸素、非炭素、非塩素、非臭素気体である酸
素が1%以下即ち、純度99%以上好ましくは酸素
が0.1%以下の純度99.0%以上の高純度を有する
弗化水素(無水弗化水素ともいう、以下HFとい
う)をプラズマ化してドライエツチをして除去す
ることとしたものであるため、内壁に付着した付
着物が珪素、炭化珪素被膜に混入して特性を劣化
させるというようなことなく反応室内を清浄にす
ることができた。
In the present invention, after forming a non-single-crystal coating mainly composed of silicon or silicon carbide, the deposits mainly composed of silicon or silicon carbide deposited inside the reaction chamber can be removed by non-oxygen, non-carbon, non-chlorine, Hydrogen fluoride (also referred to as anhydrous hydrogen fluoride, hereinafter referred to as HF) having a high purity of 99.0% or more with a non-bromine gas of 1% or less oxygen, i.e., 99% or more, preferably 0.1% or less oxygen, is used in plasma. Since the reaction chamber is removed by dry etching, it is possible to clean the inside of the reaction chamber without causing deposits on the inner walls to mix with the silicon and silicon carbide coatings and deteriorate their properties. Ta.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を実施するための半導体膜形成
用製造装置の概略を示す。
FIG. 1 schematically shows a manufacturing apparatus for forming a semiconductor film for carrying out the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 真空引きが可能な反応室にて、珪素または炭
化珪素を主成分とする非単結晶被膜を形成した
後、前記反応室内部に付着した珪素または炭化珪
素を主成分とする付着物を酸素または酸化物気体
が1%以下しか含まない弗化水素を導入し、電気
エネルギを加えてプラズマ化することにより気相
エツチをして除去することを特徴とするプラズマ
気相反応方法。
1. After forming a non-single-crystal film mainly composed of silicon or silicon carbide in a reaction chamber that can be evacuated, the deposits mainly composed of silicon or silicon carbide attached inside the reaction chamber are removed by oxygen or A plasma gas phase reaction method characterized in that hydrogen fluoride containing 1% or less of oxide gas is introduced and removed by gas phase etching by applying electrical energy to transform it into plasma.
JP17568483A 1983-09-22 1983-09-22 Plasma gaseous phase reaction method Granted JPS6067673A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP17568483A JPS6067673A (en) 1983-09-22 1983-09-22 Plasma gaseous phase reaction method
JP33905390A JPH03183125A (en) 1983-09-22 1990-11-30 Method for plasma vapor-phase reaction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17568483A JPS6067673A (en) 1983-09-22 1983-09-22 Plasma gaseous phase reaction method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP33905390A Division JPH03183125A (en) 1983-09-22 1990-11-30 Method for plasma vapor-phase reaction

Publications (2)

Publication Number Publication Date
JPS6067673A JPS6067673A (en) 1985-04-18
JPH0344148B2 true JPH0344148B2 (en) 1991-07-05

Family

ID=16000425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17568483A Granted JPS6067673A (en) 1983-09-22 1983-09-22 Plasma gaseous phase reaction method

Country Status (1)

Country Link
JP (1) JPS6067673A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62280368A (en) * 1986-05-30 1987-12-05 Semiconductor Energy Lab Co Ltd Thin film forming device
US7421258B2 (en) * 2003-10-10 2008-09-02 Rosemount Inc. Compact temperature transmitter with improved lead connections

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54125143A (en) * 1978-03-24 1979-09-28 Toshiba Corp Treating device using hydrogen fluoride-containing gas
JPS5559727A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Plasma deposition device
JPS5644763A (en) * 1979-09-20 1981-04-24 Toshiba Corp Cvd device under reduced pressure
JPS56166935A (en) * 1980-05-23 1981-12-22 Mitsubishi Electric Corp Apparatus for vapor growth under reduced pressure
JPS5825226A (en) * 1982-07-19 1983-02-15 Shunpei Yamazaki Plasma cvd unit
JPS5895550A (en) * 1982-11-01 1983-06-07 Shunpei Yamazaki Device for forming non-single crystal semiconductor layer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54125143A (en) * 1978-03-24 1979-09-28 Toshiba Corp Treating device using hydrogen fluoride-containing gas
JPS5559727A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Plasma deposition device
JPS5644763A (en) * 1979-09-20 1981-04-24 Toshiba Corp Cvd device under reduced pressure
JPS56166935A (en) * 1980-05-23 1981-12-22 Mitsubishi Electric Corp Apparatus for vapor growth under reduced pressure
JPS5825226A (en) * 1982-07-19 1983-02-15 Shunpei Yamazaki Plasma cvd unit
JPS5895550A (en) * 1982-11-01 1983-06-07 Shunpei Yamazaki Device for forming non-single crystal semiconductor layer

Also Published As

Publication number Publication date
JPS6067673A (en) 1985-04-18

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