JPH0463537B2 - - Google Patents

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Publication number
JPH0463537B2
JPH0463537B2 JP58151407A JP15140783A JPH0463537B2 JP H0463537 B2 JPH0463537 B2 JP H0463537B2 JP 58151407 A JP58151407 A JP 58151407A JP 15140783 A JP15140783 A JP 15140783A JP H0463537 B2 JPH0463537 B2 JP H0463537B2
Authority
JP
Japan
Prior art keywords
electric field
substrate
reaction
electrodes
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58151407A
Other languages
Japanese (ja)
Other versions
JPS6043820A (en
Inventor
Shunpei Yamazaki
Mamoru Tashiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP58151407A priority Critical patent/JPS6043820A/en
Publication of JPS6043820A publication Critical patent/JPS6043820A/en
Publication of JPH0463537B2 publication Critical patent/JPH0463537B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 本発明はプラズマ気相反応方法およびその製造
装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a plasma gas phase reaction method and an apparatus for producing the same.

本発明は１つの反応容器内に２つの独立した電
界を平行平板電極により供給することにより、均
一な膜厚の被膜を作製することを目的とする。 An object of the present invention is to produce a film with a uniform thickness by supplying two independent electric fields into one reaction vessel using parallel plate electrodes.

本発明はかかる目的のため、基板の基形成面に
概略平行に第１の電界を発生させ、プラズマ反応
をせしめ、さらにこの電界に直交して第２の電界
をアシスト（補助用）電界として供給せしめたこ
とを目的とする。 For this purpose, the present invention generates a first electric field approximately parallel to the base forming surface of the substrate to cause a plasma reaction, and further supplies a second electric field orthogonal to this electric field as an assisting electric field. The purpose is to instruct.

従来、プラズマ気相反応方法においては、一対
のみの電極を平行に配し、平行平板型電極とし、
その電極間にプラズマ放電をグロ−放電法により
実施することにより半導体被膜等の形成を行つて
いた。かかる一対の電極のみ用いる方式では、こ
の電極の一方に被形成面を有する基板を配設して
電極と等電位とする場合は、被膜の均一性を±５
％以内のばらつきの範囲に有せしめることができ
る。 Conventionally, in the plasma gas phase reaction method, only one pair of electrodes are arranged in parallel, and a parallel plate type electrode is used.
Semiconductor films and the like have been formed by applying plasma discharge between the electrodes using a glow discharge method. In such a method using only a pair of electrodes, if a substrate having a surface to be formed is disposed on one of the electrodes to have the same potential as the electrode, the uniformity of the coating should be ±5.
It can be made to have a variation within %.

しかしかかる方式では、被形成面を電極面積以
上に大きくすることができない。このため、多量
生産に不向きであるという欠点を有する。 However, in this method, the surface on which the electrode is formed cannot be made larger than the area of the electrode. Therefore, it has the disadvantage of being unsuitable for mass production.

他方、基板を平行平板型電極の間にその電界が
被形成面に概略平行になるように多数の基板を互
いに一定の距離（２〜６cm）を離間して林立せし
めて配設する方法が知られている。 On the other hand, a method is known in which a large number of substrates are arranged in a row at a certain distance (2 to 6 cm) from each other so that the electric field is approximately parallel to the surface on which the substrate is formed between parallel plate type electrodes. It is being

その一例は本発明人の出願になる特許願（プラ
ズマ気相反応装置 昭和57年９月20日出願 特願
昭57−163728／163729／163730）である。 An example of this is a patent application filed by the present inventor (Plasma gas phase reactor, patent application No. 163728/163729/163730, filed September 20, 1980).

即ち、基板を電位的にいずれの電極からも遊離
せしめて気相反応を行ういわゆるフローテイング
プラズマ気相反応方法（以下FPCVD法という）
において、多量の被膜形成を行うことができると
いう特徴を有する。このため従来より高知の平行
平板型電極の一方電極上に基板を配設する方法に
比べて５〜20倍の生産性をあげることができた。
しかしかかるFPCVD法において、得られる膜厚
の均一性はその一例として第１図に示すごときも
のであつた。 That is, the so-called floating plasma vapor phase reaction method (hereinafter referred to as FPCVD method) in which the substrate is electrically isolated from any electrode to perform a gas phase reaction.
It has the feature that a large amount of film can be formed. As a result, productivity can be increased 5 to 20 times compared to the conventional method of disposing a substrate on one electrode of Kochi's parallel plate type electrodes.
However, in this FPCVD method, the uniformity of the film thickness obtained was as shown in FIG. 1 as an example.

図面Ａにおいて、基板２と電極６２，５２との
相対位置関係を示している。基板２は約5000Åの
厚さに珪素を形成したものであるが、一対の電極
６２，５２間でＢ、Ｃに示すごとく、電極近傍が
厚くなり、またＤ、Ｅに示すごとく電極の中央部
が厚く、また電極端部が薄くなつてしまつた。こ
のため基板２上側端部に形成される膜厚は中央部
の上下端部の厚さに比べて20〜30％も厚さが薄く
なつてしまつた。 In Drawing A, the relative positional relationship between the substrate 2 and the electrodes 62, 52 is shown. The substrate 2 is made of silicon with a thickness of approximately 5000 Å, but between the pair of electrodes 62 and 52, the area near the electrodes is thicker as shown in B and C, and the center part of the electrodes is thicker as shown in D and E. The electrode was thick and the end of the electrode was thin. For this reason, the thickness of the film formed at the upper end of the substrate 2 is 20 to 30% thinner than the thickness at the upper and lower ends of the central part.

即ち、従来より公知のPCVD法において被形成
面のスパツタを少なくするため、そのプラズマ反
応に用いられる高周波の電界は被形成面に添つて
流れるように層流を構成して供給され、即ち電界
は被形成面に概略平行になるように配設せしめて
いる。しかし一対の電極による電界のみでは端部
の電界が外方向に放散し、電束密度が小さくなつ
てしまう。その結果、電極端部下の被形成面上で
は被膜はその厚さが薄くなつたものと判断され
る。 That is, in order to reduce spatter on the surface to be formed in the conventionally known PCVD method, the high-frequency electric field used for the plasma reaction is supplied in a laminar flow along the surface to be formed. It is arranged so as to be approximately parallel to the surface to be formed. However, if only the electric field is generated by a pair of electrodes, the electric field at the end will be dissipated outward, and the electric flux density will become small. As a result, it is determined that the thickness of the film on the surface under which the electrode is formed becomes thinner.

このため本発明はかかる膜厚の不均一性を防ぎ
四角形の被形成面のすべての周辺部、中央部も所
定の厚さに対しその厚さのばらつき±５％以内と
するため、電極を２対とし、それぞれ対をなす電
極を互いに直交する方向に供給して電気エネルギ
を供給することを特徴としている。 Therefore, in the present invention, in order to prevent such non-uniformity in film thickness and to keep the variation in thickness within ±5% with respect to the predetermined thickness at all the peripheral and central portions of the rectangular formation surface, two electrodes are used. It is characterized in that the electrodes in each pair are supplied in directions orthogonal to each other to supply electrical energy.

即ち、前記した第１の電界に直交して第２のア
シスト電界を供給せしめて、端部での電束密度が
小さくなることを防いだ。本発明はこれら２つの
電極から基板の被形成面が電気的に浮いた（フロ
ーテイング）とすることにより、プラズマエネル
ギが被形成面をスパツタする程度を軽減せしめ
た。 That is, by supplying the second assist electric field orthogonally to the first electric field described above, the electric flux density at the end portions was prevented from becoming small. The present invention reduces the extent to which plasma energy sputters on the formation surface by electrically floating the formation surface of the substrate from these two electrodes.

即ち、本発明は一対の上下方向に配設された
（電極間距離の短い）主電極による主電界を発生
せしめ、さらにそれに直交してアシスト電界を発
生させている。そしてこれら２つの電界は互いに
直交または概略直交（膜圧の薄い方向に電界を加
える）し、かつ被形成面に概略平行に配設される
ように位置関係を有せしめている。本発明はこの
２対の電極を１つの反応容器内に配設し、かかる
反応容器にて被膜例えば非単結晶半導体の形成を
行うことを特徴としている。 That is, in the present invention, a main electric field is generated by a pair of main electrodes arranged in the vertical direction (with a short distance between the electrodes), and an assist electric field is further generated perpendicular to the main electric field. These two electric fields are orthogonal or approximately orthogonal to each other (the electric field is applied in the direction of thinner film thickness), and are arranged in a positional relationship so that they are approximately parallel to the surface to be formed. The present invention is characterized in that these two pairs of electrodes are disposed in one reaction vessel, and a film such as a non-single crystal semiconductor is formed in this reaction vessel.

さらに本発明はかかる半導体層をＰ型半導体、
Ｉ型半導体およびＮ型半導体と積層してPIN接合
を基板上に形成するに際し、それぞれの反応容器
を分離部を介して連結せしめたマルチチヤンバ方
式のPCVD法に適用可能である。 Furthermore, the present invention provides that the semiconductor layer is a P-type semiconductor,
When stacking an I-type semiconductor and an N-type semiconductor to form a PIN junction on a substrate, the present invention can be applied to a multi-chamber PCVD method in which each reaction vessel is connected via a separation part.

本発明は水素またはハロゲン元素が添加された
非単結晶半導体層、好ましくは珪素、ゲルマニユ
ーム、炭化珪素（SiCのみではなく、SixC1-x０
＜ｘ＜１の総称を意味する）、珪化ゲルマニユー
ム（SixGe1-x０＜ｘ＜１）、珪素スズ（SixSn1-x
０＜ｘ＜１）であつて、この被膜中に活性状態の
水素またはハロゲン元素を充填することにより、
再結合中心密度の小さなＰ、ＩおよびＮ型の導電
型を有する半導体層を複数形成し、その積層境界
にてPI接合、NI接合またはこれらを組み合わせ
てPIP接合、NIN接合、PIN接合を形成するとと
もに、それぞれの半導体層に他の隣接する半導体
層からの不純物が混入して接合特性を劣化させる
ことなく形成するとともに、またそれぞれに半導
体層を形成する工程間に大気特に酸素に触れさせ
て、半導体の一部が酸化されることにより、層間
絶縁物が形成されることのないようにした連続生
産を行うためのプラズマ気相反応に適用可能であ
る。 The present invention is a non-single crystal semiconductor layer doped with hydrogen or a halogen element, preferably silicon, germanium, silicon carbide (not only SiC, but also SixC 1-x 0).
<x<1), germanium silicide (SixGe 1-x 0<x<1), silicon tin (SixSn 1-x
0<x<1), and by filling this film with hydrogen or a halogen element in an active state,
A plurality of semiconductor layers having conductivity types of P, I, and N types with a small recombination center density are formed, and a PI junction, NI junction, or a combination of these forms a PIP junction, NIN junction, or PIN junction at the lamination boundary. At the same time, each semiconductor layer is formed without contaminating impurities from other adjacent semiconductor layers and deteriorating the bonding characteristics, and is also exposed to the atmosphere, particularly oxygen, between the steps of forming each semiconductor layer. It is applicable to a plasma vapor phase reaction for continuous production in which interlayer insulators are not formed due to oxidation of a part of the semiconductor.

さらに本発明はかかる多数の反応容器を連結し
たマルチチヤンバ方式のプラズマ反応方法におい
て、一度に多数の基板を同時にその被膜成長速度
を大きくしたいわゆる多量生産方式に関する。 Furthermore, the present invention relates to a so-called mass production method in which a large number of substrates are simultaneously grown at a high film growth rate in a multi-chamber plasma reaction method in which a large number of reaction vessels are connected.

本発明では２〜10cm好ましくは３〜５cmの一定
の間隙を経て被膜形成面に概略平行に配置された
基板の上部、下部および中央、周辺で膜厚の均一
性、また膜質の均質性を促すため、一対をなす電
極を２対互いに直交するように設けた。さらに、
基板の加熱を少なくとも上方向および下方向によ
り棒状赤外線ランプを互いに90°曲げて配向し、
均熱化を図る手段を付加すると好ましい。即ち10
cm×10cmまたは電極方向に10〜40cm例えば20cmを
有するとともに巾15〜120cm例えば60cmの基板
（20cm×60cmを１バツチ20枚配設）が、その温度
分布において、100〜650℃の温度設定において±
10℃以内のばらつきとする。 The present invention promotes uniformity of film thickness and film quality at the top, bottom, center, and periphery of the substrate, which is arranged approximately parallel to the film formation surface with a constant gap of 2 to 10 cm, preferably 3 to 5 cm. Therefore, two pairs of electrodes were provided so as to be perpendicular to each other. moreover,
orienting the rod-shaped infrared lamps bent 90° to each other to heat the substrate at least upwardly and downwardly;
It is preferable to add a means for equalizing the heat. i.e. 10
cm x 10 cm or 10 to 40 cm, e.g. 20 cm in the direction of the electrodes, and a width of 15 to 120 cm, e.g. 60 cm (20 pieces of 20 cm x 60 cm are arranged in one batch). ±
The variation shall be within 10℃.

かくのごとくにマルチチヤンバ方式への適用を
も考慮しているため、それぞれの反応容器内での
被膜の特性の向上に加えて、チヤンバ内壁に不要
の反応生成物が付着することを防ぎ、逆に加えて
供給した反応性気体の被膜になる割合、即ち収集
効率を高めている。このため絶縁性（石英）ホル
ダにより囲み、チムニー（煙突）状に基板の配置
されている筒状空間に反応性気体を供給フードに
選択的に導入させ、排気フード排気させるのが好
ましい。さらに基板の被形成面が実質的にチムニ
ーの内壁を構成せしめることが好ましい。 In this way, application to a multi-chamber system is also considered, so in addition to improving the properties of the coating within each reaction vessel, it also prevents unnecessary reaction products from adhering to the inner walls of the chamber, and vice versa. In addition, the rate at which the supplied reactive gas forms a film, that is, the collection efficiency is increased. For this reason, it is preferable to selectively introduce a reactive gas into a cylindrical space surrounded by an insulating (quartz) holder and in which the substrate is arranged in a chimney-like manner through a supply hood, and exhaust the gas through an exhaust hood. Furthermore, it is preferable that the surface of the substrate to be formed substantially constitutes the inner wall of the chimney.

図面においては、反応性気体の導入口、排気口
において供給フード、排気フードを設け、この間
の絶縁物ホルダで囲んだ基板の被形成面により実
質的に作られた筒状空間のみに選択的にプラズマ
反応による活性気体を導入せしめることによりチ
ヤンバ（反応容器）内の全空間に反応生成物が拡
散し広がることを防いだものである。かかる気相
反応装置により、形成された不純物のそれぞれの
半導体層から他の半導体層への混合を排除し、ま
たそれぞれの反応容器内に形成されるフレークを
少なくさせて、さらに複数の半導体層の積層界面
での混合の厚さ200〜300Åと従来よりも約1/10〜
１／５にするとともに、基板内、同一バツチの基板
間での膜厚のばらつきを±５％以内（例えば5000
Åの厚さとすると、そのばらつき±250Å以内）
とし得たこと特徴としている。 In the drawing, a supply hood and an exhaust hood are provided at the inlet and exhaust port for the reactive gas, and selectively fills only the cylindrical space substantially created by the formation surface of the substrate surrounded by the insulator holder between them. By introducing active gas from a plasma reaction, reaction products are prevented from diffusing and spreading throughout the entire space within the chamber (reaction container). Such a gas phase reactor eliminates the mixing of formed impurities from each semiconductor layer into other semiconductor layers, reduces the amount of flakes formed in each reaction vessel, and further improves the stability of multiple semiconductor layers. The thickness of the mixture at the lamination interface is 200 to 300 Å, approximately 1/10 to 1/10 that of the conventional one.
In addition to reducing the film thickness to 1/5, the variation in film thickness within a substrate or between substrates of the same batch should be within ±5% (for example, 5000
If the thickness is Å, the variation is within ±250 Å)
It is characterized by what was achieved.

以下に本発明の実施例を図面に従つて説明す
る。 Embodiments of the present invention will be described below with reference to the drawings.

実施例 １ 第２図に従つて本発明のプラズマ気相反応装置
の実施例を説明する。Example 1 An example of the plasma vapor phase reactor of the present invention will be described with reference to FIG.

この図面は、PIN接合、PIP接合、NIN接合ま
たはPINPIN…PIN接合等の基板上の半導体に、
異種導電型でありながらも、形成される半導体の
主成分または化学量論比の異なる半導体層をそれ
ぞれの半導体層をその前工程において形成された
半導体層の影響（混入）を受けずに積層させるた
めの多層に自動かつ連続的に形成するための装置
である。 This drawing shows how to connect semiconductors on a substrate such as PIN junction, PIP junction, NIN junction or PINPIN...PIN junction.
Laminating semiconductor layers of different conductivity types but with different main components or stoichiometric ratios without being influenced (contaminated) by semiconductor layers formed in the previous process. This is a device for automatically and continuously forming multi-layers.

図面においてはPI接合、IN接合をさらに複合
化してPIN接合を構成する３つのＰ、ＩおよびＮ
型の半導体層を積層して形成する３つの反応系
（、、）とさらに第１および第２の予備室
を有するマルチチヤンバ（ここでは３つの反応容
器）方式のプラズマ気相反応装置の装置例を示
す。 In the drawing, there are three P, I and N constituting a PIN junction by further compounding the PI junction and IN junction.
An example of a multi-chamber (in this case, three reaction vessels) type plasma vapor phase reactor, which has three reaction systems (,,) formed by laminating semiconductor layers of the same type, and a first and second preliminary chamber. show.

図面における系、、は３つの各反応容器
６，７，８を有し、それぞれの反応容器間に分離
部４４，４５，４６，４７を有している。またそ
れぞれ独立して反応性気体の導入フード１７，１
８，１９と排気フード１７′，１８′，１９′と側
面フード（図示せず）とを有し、反応性気体が供
給系または排気系から逆流、または他の系からの
反応性気体の混入を防いでいる。 The system in the drawings has three reaction vessels 6, 7, 8, and separation sections 44, 45, 46, 47 between the reaction vessels. In addition, reactive gas introduction hoods 17 and 1 are each independently installed.
8, 19, exhaust hoods 17', 18', 19', and side hoods (not shown) to prevent reactive gases from flowing back from the supply system or exhaust system, or from mixing with reactive gases from other systems. is prevented.

この装置は入り口側には第１の予備室５が設け
られ、まず扉４２より基板ホルダ（ホルダともい
う）７４に基板４を挿着し、この予備室に配置さ
せた。この被形成面を有する基板は被膜形成を行
わない裏面を互いに接し、２枚を一対として２〜
10cm好ましくは３〜５cmの間隙を有して林立させ
ている。この間隙は基板の反応性気体の流れ方向
の長さが10cm、15cm、20cmと長くなるにつれて、
３〜４cm、４〜５cm、５〜６cmと広げた。 This apparatus is provided with a first preliminary chamber 5 on the entrance side, and the substrate 4 is first inserted into a substrate holder (also referred to as holder) 74 through the door 42 and placed in this preliminary chamber. The back sides on which the film is not formed are in contact with each other, and two of the substrates having the surface to be formed are made into a pair.
They are arranged in a forest with a gap of 10 cm, preferably 3 to 5 cm. This gap increases as the length of the substrate in the flow direction of the reactive gas increases to 10 cm, 15 cm, and 20 cm.
It spread to 3-4 cm, 4-5 cm, and 5-6 cm.

例えば20cm×60cmの基板を20枚同時に形成させ
る場合、その間隙は６cmとした。さらにこの第１
の予備室５を真空ポンプ３５にてバルブを開けて
真空引きをした。この後予め真空引きがされてい
る反応容器６，７，８との分離用のゲート弁４
４，４５，４６，４７を開けて基板およびホルダ
を移した。例えば、予備室５より第１の反応容器
６に移し、さらにゲート弁４４を閉じることによ
り基板およびホルダを第１の反応容器６に移動さ
せたものである。この時、第１の反応容器６に保
持されていた基板１は第２の反応容器７に、また
第２の反応容器７に保持されていた基板２は第３
の反応容器８に、また第３の反応容器８に保持さ
れていた基板は出口側の第２の予備室９に同時に
ゲート弁４５，４６，４７を開けて移動させた。
この後ゲート弁４４，４５，４６，４７を閉め
た。 For example, when forming 20 substrates of 20 cm x 60 cm at the same time, the gap between them was set to 6 cm. Furthermore, this first
The preliminary chamber 5 was evacuated using the vacuum pump 35 by opening the valve. Gate valve 4 for separation from reaction vessels 6, 7, 8 which have been evacuated in advance after this
4, 45, 46, and 47 were opened and the substrate and holder were transferred. For example, the substrate and holder are transferred from the preliminary chamber 5 to the first reaction vessel 6, and then the gate valve 44 is closed to move the substrate and holder to the first reaction vessel 6. At this time, the substrate 1 held in the first reaction container 6 is transferred to the second reaction container 7, and the substrate 2 held in the second reaction container 7 is transferred to the third reaction container 7.
The substrates held in the second reaction vessel 8 and the third reaction vessel 8 were moved to the second preliminary chamber 9 on the exit side by simultaneously opening the gate valves 45, 46, and 47.
After this, the gate valves 44, 45, 46, and 47 were closed.

第２の予備室に移された基板はゲート弁４７が
閉じられた後４１より窒素が導入されて大気圧に
され、４３の扉より外へ出した。 After the gate valve 47 was closed, the substrate transferred to the second preliminary chamber was brought to atmospheric pressure by introducing nitrogen through the gate 41, and was taken out through the door 43.

即ちゲート弁の動きは扉４２，４３が大気圧で
開けられた得は分離部のゲート弁４４，４５，４
６，４７は閉じられ、各チヤンバにおいてはプラ
ズマ気相反応が行われている。また逆に扉４２，
４３が閉じられていて予備室５，９が十分真空引
きされた時は、ゲート弁４４，４５，４６，４７
が開けられ、各チヤンバの基板、ホルダは隣のチ
ヤンバに移動する機構を有している。 In other words, the gate valves 44, 45, 4 in the separation section move when the doors 42, 43 are opened at atmospheric pressure.
6 and 47 are closed, and a plasma gas phase reaction is performed in each chamber. On the other hand, the door 42,
43 is closed and the preliminary chambers 5, 9 are sufficiently evacuated, the gate valves 44, 45, 46, 47
It has a mechanism for opening the chamber and moving the substrate and holder of each chamber to the adjacent chamber.

系における第１の反応容器６でＰ型半導体層
をPCVD法により形成する場合を以下に示す。 A case in which a P-type semiconductor layer is formed by the PCVD method in the first reaction vessel 6 in the system will be described below.

反応系（反応容器６を含む）は10-3〜10torr
好ましくは0.01〜1torr例えば0.08torrとした。 The reaction system (including reaction vessel 6) is 10 -3 to 10 torr
Preferably it is 0.01 to 1 torr, for example 0.08 torr.

反応性気体は珪化物気体２４に対してシラン
（SinH2o+2ｎ＞１特にSiH4）、ジクロールシラン
（SiH2Cl2）、トリクロールシラン（SiHCl3）、四
フツ化珪素（SiF4）等があるが、取扱が容易なシ
ランを用いた。 The reactive gas is silane (SinH 2o+2 n>1, especially SiH 4 ), dichlorosilane (SiH 2 Cl 2 ), trichlorosilane (SiHCl 3 ), silicon tetrafluoride (SiF 4 ) with respect to the silicide gas 24. ), but we used silane, which is easy to handle.

本実施例のSixC1-x（０＜ｘ＜１）を形成するた
め、炭化物気体２３に対してはメタン（CH4）を
用いた。 In order to form SixC 1-x (0<x<1) in this example, methane (CH 4 ) was used for the carbide gas 23.

炭化珪素（SixC1-x０＜ｘ＜１）に対しては、
Ｐ型の不純物としてボロンを水素にて2000PPM
に希釈されたジボランより２５より供給した。ま
たガリユームをTMG（Ga（CH3）3）により1019〜
９×1021cm-3の濃度になるように加えてもよい。 For silicon carbide (SixC 1-x 0<x<1),
2000PPM of boron with hydrogen as a P-type impurity
diborane diluted to 25%. In addition, galiyum was treated with TMG (Ga(CH 3 ) 3 ) at 10 19 ~
It may be added to a concentration of 9×10 21 cm −3 .

必要に応じ水素（H2）または窒素（N2）を液
体窒素より気化して用いた。これらの反応性気体
はそれぞれの流量計３３およびバルブ３２を経
て、反応性気体の供給フード１７より高周波電源
１４の負電極６１を経て反応容器６に供給され
た。反応性気体は７０のホルダ７４に囲まれた筒
状空間内に供給され、この空間を構成する基板１
に被膜形成を行つた。さらに負電極６１と正電極
５１間に電気エネルギ例えば13.56MHzの高周波
エネルギ１４を加えてプラズマ反応せしめ、基板
上に反応生成物を被膜形成せしめた。 Hydrogen (H 2 ) or nitrogen (N 2 ) was vaporized from liquid nitrogen and used as necessary. These reactive gases were supplied to the reaction vessel 6 via the respective flowmeters 33 and valves 32, and from the reactive gas supply hood 17 via the negative electrode 61 of the high frequency power source 14. The reactive gas is supplied into a cylindrical space surrounded by 70 holders 74, and the substrate 1 constituting this space is
A film was formed on the surface. Furthermore, electric energy, for example, high frequency energy 14 of 13.56 MHz, was applied between the negative electrode 61 and the positive electrode 51 to cause a plasma reaction, and a reaction product was formed on the substrate.

基板は100〜400℃例えば200℃に赤外線ヒータ
１１，１１′により加熱した。 The substrate was heated to 100-400°C, for example 200°C, by infrared heaters 11, 11'.

この赤外線ヒータは、近赤外用ハロゲンランプ
（発光波長１〜3μ）ヒータまたは遠赤外用セラミ
ツクヒータ（発光波長８〜25μ）を用い、棒状を
有するため上方のヒータと下方のヒータとが互い
に直交する方向に配置して、この反応容器内にお
けるホルダにより取り囲まれた筒状空間を200±
10℃好ましくは±５℃以内に設置した。 This infrared heater uses a near-infrared halogen lamp (emission wavelength 1-3μ) heater or far-infrared ceramic heater (emission wavelength 8-25μ), and has a rod shape so that the upper heater and lower heater are perpendicular to each other. The cylindrical space surrounded by the holder in this reaction vessel is 200±
The temperature was set at 10°C, preferably within ±5°C.

この後、前記したが、この容器に前記した反応
性気体を導入し、さらに10〜500W例えば100Wに
高周波エネルギ１４を供給してプラズマ反応を起
こさせた。 Thereafter, as described above, the above-mentioned reactive gas was introduced into the container, and high-frequency energy 14 of 10 to 500 W, for example, 100 W was supplied to cause a plasma reaction.

さらに上下の電極（網状のステンレス製電極65
cm×65cm）６１，５１に直交して他の一対の電極
（網状のステンレス製電極25cm×65cm）７１，８
１（図示されず）にも同様に電気エネルギを加え
た。 Furthermore, the upper and lower electrodes (reticulated stainless steel electrodes 65
cm x 65cm) 61, 51, and another pair of electrodes (reticulated stainless steel electrodes 25cm x 65cm) 71, 8
1 (not shown) was similarly applied with electric energy.

ここでは13.56MHzを50Wの出力で加えた。即
ちアシスト電界（補助電界）により第１の電界の
端部での電界が弱くなる部分を中央部とほぼ同じ
ようにすることが可能になつた。 Here, 13.56MHz was added with an output of 50W. That is, it has become possible to make the portion where the electric field weakens at the ends of the first electric field by the assist electric field (auxiliary electric field) almost the same as the central portion.

かくしてＰ型半導体層はB2H6／SiH4＝0.5％、
CH4／（SiH4＋CH4）＝0.5％の条件にて、この反
応系で約100Åの厚さを有する薄膜（膜厚のば
らつき95〜103Å）として形成させた。Bg＝
2.0OeV、σ＝１×10-6〜３×10-6（Ωcm）-1であつ
た。 Thus, the P-type semiconductor layer has B 2 H 6 /SiH 4 =0.5%,
A thin film having a thickness of about 100 Å (film thickness variation: 95 to 103 Å) was formed using this reaction system under the conditions of CH 4 /(SiH 4 +CH 4 )=0.5%. Bg=
It was 2.0 OeV, σ=1×10 -6 to 3×10 -6 (Ωcm) -1 .

基板は導体基板（ステンレス、チタン、アルミ
ニユーム、その他の金属）、半導体（珪素、ゲル
マニユーム）、絶縁体（アルミナ、ガラス、有機
物質）または複合基板（アルミニユーム、ステン
レス上に絶縁薄を形成させた絶縁性表面を有する
可曲性基板またはガラス絶縁基板の上面に弗素が
添加された酸化スズ、ITO等の導電膜が単層また
はITO上にSnO2が形成された２層膜が形成され
たもの、さらにまたは絶縁基板上にＰまたはＮ型
の半導体が形成されたもの）を用いた。本実施例
のみならず本発明のすべてにおいてこれらを総称
して基板という。勿論この基板は可曲性であつて
もまた固い板であつてもよい。 The substrate can be a conductive substrate (stainless steel, titanium, aluminum, or other metal), a semiconductor (silicon, germanium), an insulator (alumina, glass, organic material), or a composite substrate (aluminum, an insulating layer formed on stainless steel). A flexible substrate or a glass insulating substrate having a single layer of a conductive film such as fluorine-doped tin oxide or ITO on the top surface, or a two-layer film of SnO 2 formed on ITO; or one in which a P or N type semiconductor is formed on an insulating substrate). These are collectively referred to as a substrate not only in this embodiment but also in all of the present invention. Of course, this substrate may be flexible or a rigid plate.

かくして１〜５分間プラズマ気相反応をさせ
て、Ｐ型不純物としてホウ素またはガリユームが
添加された炭化珪素膜を約100Åの厚さに作製し
た。さらにこの第１の半導体層上に基板を前記し
た操作順序に従つて第２の反応容器７に移動し、
ここで真性の半導体層を約5000Åの厚さに形成さ
せた。 In this way, a plasma vapor phase reaction was carried out for 1 to 5 minutes, and a silicon carbide film doped with boron or gallium as a P-type impurity was produced to a thickness of about 100 Å. Further, the substrate is placed on the first semiconductor layer and moved to the second reaction vessel 7 according to the above-described operation order,
Here, an intrinsic semiconductor layer was formed to a thickness of about 5000 Å.

即ち第１図における反応系において、半導体
の反応性気体としてシランを２８より、また、
1017cm-3以下のホウ素を添加するため、水素、シ
ラン等により５〜30PPMに希釈したB2H6を２７
より、また、キヤリアガスを必要に応じて２６よ
り供給した。 That is, in the reaction system shown in FIG. 1, silane is used as the reactive gas of the semiconductor, and
In order to add less than 10 17 cm -3 of boron, B 2 H 6 diluted to 5 to 30 PPM with hydrogen, silane, etc.
Additionally, carrier gas was supplied from 26 as needed.

反応性気体は基板２の被形成面にそつて上方よ
り下方に流れ、真空ポンプ３７に至る。系にお
いて４３の出口側よりみた縦断面図を第３図に示
す。 The reactive gas flows from above to below along the surface of the substrate 2 to be formed, and reaches the vacuum pump 37 . A longitudinal cross-sectional view of the system 43 viewed from the outlet side is shown in FIG.

第３図を概説する。 Figure 3 is outlined.

第３図は、第２の反応容器７を基板の移動方向
に見た図であり、アシスト電界を用いて被膜を形
成せしめている。 FIG. 3 is a view of the second reaction vessel 7 viewed in the direction of movement of the substrate, and a film is formed using an assist electric field.

図面において、ヒータ１２，１２′はジルコン
（ZrSiO4）発熱体を用い、8μ以上の光が十分に放
射できる遠赤外線ヒータとした。反応空間はヒー
タにより100〜400℃例えば250℃とした。反応性
気体は例えばシランを分解した。 In the drawings, heaters 12 and 12' are far-infrared heaters that use zircon (ZrSiO 4 ) heating elements and can sufficiently emit light of 8 μ or more. The reaction space was kept at 100-400°C, for example 250°C, by a heater. The reactive gas decomposed silane, for example.

さらに基板２に対し、その被形成面に概略平行
に第１の電界９０を一対の主の電極６２，５２に
より供給し、プラズマ気相反応を行つた。 Furthermore, a first electric field 90 was applied to the substrate 2 by a pair of main electrodes 62 and 52 approximately parallel to the surface on which the substrate 2 was formed, thereby performing a plasma vapor phase reaction.

さらに同時にアシスト電界９１を第２の一対を
なす電極７２，８２により供給して、それぞれが
高周波発振器１５および他の高周波発振器８５に
より連結している。反応性気体を２６，２７，２
８より供給フード１８、側面フード１８″、排気
フード１８′により真空ポンプ３７へ排気させた。
被膜としてシランによりアモルフアス珪素を作製
した場合、5000Åの厚さにSiH460cc／分、被膜
形成速度2.5Å／秒、基板（20cm×60cmを20枚、
延べ面積24000cm2）で圧力0.08torrとした。する
と中央部が5000Åとばらつき、縦方向の周辺部が
アシスト電界がない従来方法の場合は3000Å（ば
らつき±20％）であつたのが、本発明方法では
4500Å（±５％）ときわめて均一性を向上させる
ことができた。 Further, at the same time, an assist electric field 91 is supplied by a second pair of electrodes 72 and 82, which are connected by a high frequency oscillator 15 and another high frequency oscillator 85, respectively. Reactive gas 26,27,2
8 to a vacuum pump 37 through a supply hood 18, a side hood 18'', and an exhaust hood 18'.
When amorphous silicon was prepared using silane as a film, SiH 4 was applied to a thickness of 5000 Å at 60 cc/min, the film formation rate was 2.5 Å/sec, and the substrates (20 sheets of 20 cm x 60 cm) were used.
The total area was 24000 cm 2 ) and the pressure was 0.08 torr. As a result, the center part has a variation of 5000 Å, and the vertical peripheral part has a variation of 3000 Å (variation ± 20%) in the conventional method without an assist electric field, but with the method of the present invention.
We were able to significantly improve the uniformity to 4500 Å (±5%).

かくして第１の反応室にてプラズマ気相法によ
りＰ型半導体層を形成した上にLT CVD法によ
りＩ型半導体層を形成させてPI接合を構成させ
た。 Thus, in the first reaction chamber, a P-type semiconductor layer was formed by the plasma vapor phase method, and then an I-type semiconductor layer was formed by the LT CVD method to form a PI junction.

またかくして系にて約5000Åの厚さに形成さ
せた後、基板は前記した操作に従つて第２図の系
の反応容器８に移され、Ｎ型半導体層が形成さ
せた。このＮ型半導体層は、PCVD法によりフオ
スヒンをPH3／SiH4＝1.0％とし３１よりまたシ
ランを３０より、またキヤリアガスの水素を３８
よりSiH4／H2＝50％として供給し、系と同様
にして約200Åの厚さにＮ型の微結晶性または繊
維構造を有する多結晶の半導体層を形成させ、さ
らにその上面にメタンCH4／（SiH4＋CH4）＝0.1
として２９より供給してSixC1-x（０＜ｘ＜１）で
示されるＮ型半導体層を10〜200Åの厚さ例えば
50Åの厚さに積層して形成させたものである。そ
の他反応装置については系と同様である。 After being formed to a thickness of about 5000 Å in the system, the substrate was transferred to the reaction vessel 8 of the system shown in FIG. 2 according to the operations described above, and an N-type semiconductor layer was formed. This N-type semiconductor layer was made by PCVD using phosphin at PH 3 /SiH 4 = 1.0%, 31% silane, 30% silane, and carrier gas hydrogen at 38%.
In the same way as the system , a polycrystalline semiconductor layer with an N-type microcrystalline or fibrous structure was formed to a thickness of about 200 Å, and methane CH was added on the top surface. 4 / (SiH 4 + CH 4 ) = 0.1
For example, an N-type semiconductor layer represented by SixC 1-x (0<x<1) with a thickness of 10 to 200 Å is supplied from 29 as
It is formed by laminating layers to a thickness of 50 Å. Other reaction equipment is the same as the system.

かかる工程の後、第２の予備室９により外に
PIN接合を構成して出された基板上に100〜1500
Åの厚さのITOをさらにその上に反射性電極とし
てのアルミニユーム電極を真空蒸着法により約
1μの厚さに作り、ガラス基板上に（ITO＋SnO2）
表面電極−（PIN半導体）−（裏面電極）を構成さ
せた。 After this step, the second preliminary chamber 9 is used to release the
100 to 1500 on the board produced by configuring the PIN junction
On top of the ITO with a thickness of 1.5 Å, an aluminum electrode as a reflective electrode was deposited by vacuum evaporation.
Made to a thickness of 1μ and placed on a glass substrate (ITO + SnO 2 )
A front electrode (PIN semiconductor) and (back electrode) were constructed.

その光電変換装置としての特性は７〜９％平均
８％を10cm×10cmの基板でAM1（100mW／cm2）
の条件下にて真性効率特性として有し、集積化し
てハイブリツド型にした20cm×60cmのガラス基板
においても、３〜５％を実効効率で得ることがで
きた。この効率の向上は大きい面積の基板の周辺
部での膜厚が従来の3000ÅよりＩ層としての最適
の膜厚の5000Åとすることができたこと、さらに
同様に従来はＰまたはＮ型半導体層では膜厚がば
らつきすぎて十分な開放電圧がなかつたことに比
べて、本発明方法はきわめて均一な膜厚にさせる
ことができたことにより、その結果、１つの素子
で開放電圧は0.85〜0.9V（0.87±0.02V）であつた
が、短絡電流は20〜22mA／cm2と大きく、また
FFも0.70〜0.78と大きくかつそのばらつきもパネ
ル内、バツチ内で小さく工業的に本発明方法はき
わめて有効であることが判明した。 Its characteristics as a photoelectric conversion device are 7-9%, average 8%, AM1 (100mW/cm 2 ) on a 10cm x 10cm substrate.
Under these conditions, it was possible to obtain an effective efficiency of 3 to 5% even on a 20 cm x 60 cm glass substrate integrated into a hybrid type. This improvement in efficiency is due to the fact that the film thickness at the periphery of a large area substrate can be reduced from the conventional 3000 Å to 5000 Å, which is the optimum film thickness for an I layer. However, the method of the present invention was able to make the film thickness extremely uniform, and as a result, the open circuit voltage for one device was 0.85 to 0.9. V (0.87±0.02V), but the short circuit current was large at 20 to 22mA/ cm2 , and
The FF was large, ranging from 0.70 to 0.78, and its variation was small within panels and batches, proving that the method of the present invention is extremely effective industrially.

第４図は第３図における第２の反応系（）で
非単結晶珪素を0.5μの膜厚に形成した場合の分布
を示す。 FIG. 4 shows the distribution when non-single crystal silicon is formed to a thickness of 0.5 μm using the second reaction system () in FIG.

図面より明らかなように、基板２、主電極６
２，５２、アシスト電極７２，８２を配し、それ
ぞれの断面での厚さの分布を(B)、(C)、(D)、(E)に示
す。このすべての断面図において、第１図に比べ
てきわめて均一性を有し、実用上十分±５％以内
のばらつきになつていることが判明した。 As is clear from the drawing, the substrate 2, the main electrode 6
2, 52, and assist electrodes 72, 82 are arranged, and the thickness distribution in each cross section is shown in (B), (C), (D), and (E). It has been found that all of these cross-sectional views have extremely uniformity compared to FIG. 1, and the variation is within ±5%, which is sufficient for practical use.

さらにこの珪素または炭素の不対結合手を水素
によりSi−Ｈ、Ｃ−Ｈにて中和するのではなく、
Si−Ｆ、Ｃ−Ｆとハロゲン化物特に弗化物気体を
用いて実施してもよいことはいうまでもなく、こ
の濃度は10原子％以下、例えば２〜５原子％が好
ましかつた。 Furthermore, instead of neutralizing the dangling bonds of silicon or carbon with hydrogen, Si-H or C-H,
It goes without saying that Si--F, C--F and a halide gas, particularly a fluoride gas, may be used, and the concentration thereof is preferably 10 atomic % or less, for example 2 to 5 atomic %.

形成させる半導体の種類に関しては、前記した
ごとく、複数層ではなく族のSi、Ge、、
SixC1-x（０＜ｘ＜１）、SixGe1-x（０＜ｘ＜１）、
SixSn1-x（０＜ｘ＜１）単層であつても、またこ
れら以外にGaAs、GaAlAs、BP、CdS等の化合
物半導体であつてもよいことはいうまでもない。 Regarding the type of semiconductor to be formed, as mentioned above, it is not a multi-layer structure, but a group of Si, Ge,...
SixC 1-x (0<x<1), SixGe 1-x (0<x<1),
It goes without saying that it may be a single layer of SixSn 1-x (0<x<1) or may be a compound semiconductor such as GaAs, GaAlAs, BP, or CdS.

本発明は３つの反応容器を用いてマルチチヤン
バ方式でのPCVD法を示した。しかしこれを１つ
の反応容器とし、そこでPCVD法により窒化珪素
をシランとアンモニアとのPCVD反応により形成
させることは有効である。また酸化珪素をシラン
をN2OとのPCVD反応により形成させることも有
効である。 The present invention demonstrated a multi-chamber PCVD method using three reaction vessels. However, it is effective to use this as one reaction vessel and form silicon nitride there by a PCVD reaction between silane and ammonia using the PCVD method. It is also effective to form silicon oxide by a PCVD reaction of silane with N 2 O.

また酸化スズをSnCl4と窒素とのPCVD反応に
より、ITOをInCl3、SnCl4と窒素とのプラズマ気
相方法により形成することも有効である。 It is also effective to form tin oxide by a PCVD reaction of SnCl 4 and nitrogen, and to form ITO by a plasma vapor phase method of InCl 3 , SnCl 4 and nitrogen.

本発明で形成された非単結晶半導体被膜は、絶
縁ゲイト型電界効果半導体装置におけるＮ（ソー
ス）Ｉ（チヤネル形成領域）Ｎ（ドレイン）接合ま
たはPIP接合に対しても有効である。さらにPIN
ダイオードであつてエネルギバンド巾がＷ−Ｎ−
Ｗ（WIDE−NALLOW−WIDE）またはSixC1-x
−Si−SixC1-x（０＜ｘ＜１）構造のPIN接合型の
可視光レーザ、発光素子または光電変換装置を作
つてもよい。特に光入射光側のエネルギバンド巾
を大きくしたヘテロ接合構造を有するいわゆるＷ
（ＰまたはＮ型）−Ｎ（Ｉ型）（WIDE TO
NALLOW）と各反応室にて導電型のみではなく
生成物を異ならせてそれぞれに独立して作製して
積層させることが可能になり、工業的にきわめて
重要なものであると信ずる。 The non-single crystal semiconductor film formed according to the present invention is also effective for N (source), I (channel forming region), N (drain) junctions or PIP junctions in insulated gate field effect semiconductor devices. More PIN
It is a diode and the energy band width is W-N-
W (WIDE−NALLOW−WIDE) or SixC 1-x
-Si-SixC 1-x (0<x<1) structure PIN junction type visible light laser, light emitting element, or photoelectric conversion device may be made. In particular, the so-called W has a heterojunction structure with a large energy band width on the incident light side.
(P or N type) - N (I type) (WIDE TO
We believe that this technology is extremely important industrially, as it makes it possible to independently manufacture and stack products of different conductivity types in each reaction chamber with NALLOW).

前記実施例において、分離部は単にゲイト弁の
みではなく、２つのゲート弁と１つのバツフア室
を系１と系２との間に設けてＰ型半導体の不純物
のＩ型半導体層中への混入をさらに防ぎ、特性を
向上せしめることは有効であつた。 In the above embodiment, the separation section is not just a gate valve, but two gate valves and one buffer chamber are provided between system 1 and system 2 to prevent the impurities of the P-type semiconductor from mixing into the I-type semiconductor layer. It was effective to further prevent this and improve the characteristics.

また本発明の実施例は第２図に示すマルチチヤ
ンバ方式であり、そのすべての反応容器にてアシ
スト電界を供給した。しかし必要に応じ、この一
部を従来の一対の電極のみとするPCVD法または
プラズマを用いない光CVD法、LT CVD法を採
用して複合被膜を形成してもよい。 Further, the embodiment of the present invention was of a multi-chamber type as shown in FIG. 2, and an assist electric field was supplied to all the reaction vessels. However, if necessary, a composite film may be formed by employing a conventional PCVD method using only a pair of electrodes, an optical CVD method that does not use plasma, or an LT CVD method.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の方法で得られた基板上の膜厚の
不均一性を示す。第２図、第３図は本発明を実施
するための半導体膜形成用製造装置の概略を示
す。第４図は本発明方法によつて得られた基板の
膜厚の均一性を示す。 FIG. 1 shows the non-uniformity of film thickness on a substrate obtained by a conventional method. FIGS. 2 and 3 schematically show a manufacturing apparatus for forming a semiconductor film for carrying out the present invention. FIG. 4 shows the uniformity of the film thickness of the substrate obtained by the method of the present invention.

Claims (1)

【特許請求の範囲】 １ 互いに直交する第１の電界と第２の電界を設
け、導体、半導体または絶縁体の被膜を形成する
基板の被形成面に対し概略垂直な方向に基板を移
動させて、前記第１の電界と第２の電界の直交領
域内で、被形成面が第１の電界と第２の電界に対
し概略平行になるように基板を設置し、さらに、
反応性気体が被形成面に沿う方向に流れるように
したことを特徴とするプラズマ気相反応方法。 ２ 複数の基板を互いに離間して概略平行に配置
する手段と、互いに直交する第１の電界と第２の
電界を設ける電極手段と、被膜が形成される基板
の被形成面に対し概略垂直方向に前記複数の基板
を移動させる手段と、反応性気体を第１の電界に
沿つて導入排気する手段とを有し、第１の電界と
第２の電界の直交領域内で、被形成面が第１の電
界と第２の電界に対し概略平行になるように基板
を設置することを特徴とするプラズマ気相反応用
製造装置。[Claims] 1. A first electric field and a second electric field that are orthogonal to each other are provided, and the substrate is moved in a direction approximately perpendicular to the surface of the substrate on which a conductor, semiconductor, or insulator film is to be formed. , a substrate is installed in a region orthogonal to the first electric field and the second electric field so that the surface to be formed is approximately parallel to the first electric field and the second electric field, and further,
A plasma vapor phase reaction method characterized in that a reactive gas is caused to flow in a direction along a surface on which formation is to be performed. 2. Means for arranging a plurality of substrates in a spaced apart manner from each other and approximately parallel to each other; electrode means for providing a first electric field and a second electric field orthogonal to each other; means for moving the plurality of substrates, and means for introducing and exhausting a reactive gas along the first electric field, and the surface to be formed is formed in a region orthogonal to the first electric field and the second electric field. A plasma gas phase applied manufacturing apparatus characterized in that a substrate is installed so as to be approximately parallel to a first electric field and a second electric field.
JP58151407A 1983-08-19 1983-08-19 Plasmic vapor-phase reacting method and device thereof Granted JPS6043820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58151407A JPS6043820A (en) 1983-08-19 1983-08-19 Plasmic vapor-phase reacting method and device thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58151407A JPS6043820A (en) 1983-08-19 1983-08-19 Plasmic vapor-phase reacting method and device thereof

Publications (2)

Publication Number Publication Date
JPS6043820A JPS6043820A (en) 1985-03-08
JPH0463537B2 true JPH0463537B2 (en) 1992-10-12

Family

ID=15517916

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58151407A Granted JPS6043820A (en) 1983-08-19 1983-08-19 Plasmic vapor-phase reacting method and device thereof

Country Status (1)

Country Link
JP (1) JPS6043820A (en)

Also Published As

Publication number Publication date
JPS6043820A (en) 1985-03-08

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